From 2aa66b1b4ebdefa7facf8c28cde49b039eb0d3cf Mon Sep 17 00:00:00 2001
From: chengy2 <31397594+chengy2@users.noreply.github.com>
Date: Tue, 30 Apr 2024 05:48:47 +0800
Subject: [PATCH] [HC32] support HC32F472 & remove residual files
---
.github/workflows/bsp_buildings.yml | 1 +
bsp/hc32/README.md | 1 +
bsp/hc32/ev_hc32f472_lqfp100/.config | 1060 +
bsp/hc32/ev_hc32f472_lqfp100/.gitignore | 42 +
bsp/hc32/ev_hc32f472_lqfp100/Kconfig | 21 +
bsp/hc32/ev_hc32f472_lqfp100/README.md | 125 +
bsp/hc32/ev_hc32f472_lqfp100/SConscript | 15 +
bsp/hc32/ev_hc32f472_lqfp100/SConstruct | 64 +
.../applications/SConscript | 15 +
.../ev_hc32f472_lqfp100/applications/main.c | 32 +
.../applications/xtal32_fcm.c | 99 +
bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig | 671 +
bsp/hc32/ev_hc32f472_lqfp100/board/SConscript | 31 +
bsp/hc32/ev_hc32f472_lqfp100/board/board.c | 113 +
bsp/hc32/ev_hc32f472_lqfp100/board/board.h | 54 +
.../ev_hc32f472_lqfp100/board/board_config.c | 499 +
.../ev_hc32f472_lqfp100/board/board_config.h | 329 +
.../board/config/adc_config.h | 155 +
.../board/config/can_config.h | 139 +
.../board/config/dac_config.h | 43 +
.../board/config/dma_config.h | 273 +
.../board/config/gpio_config.h | 176 +
.../board/config/i2c_config.h | 332 +
.../board/config/irq_config.h | 215 +
.../board/config/pm_config.h | 100 +
.../board/config/pulse_encoder_config.h | 545 +
.../board/config/pwm_tmr_config.h | 882 +
.../board/config/qspi_config.h | 75 +
.../board/config/spi_config.h | 377 +
.../board/config/timer_config.h | 115 +
.../board/config/uart_config.h | 449 +
.../ev_hc32f472_lqfp100/board/drv_config.h | 39 +
.../ev_hc32f472_lqfp100/board/hc32f4xx_conf.h | 136 +
.../board/linker_scripts/link.icf | 116 +
.../board/linker_scripts/link.ld | 276 +
.../board/linker_scripts/link.sct | 22 +
.../ev_hc32f472_lqfp100/board/ports/fal_cfg.h | 43 +
.../board/ports/tca9539_port.h | 67 +
.../ev_hc32f472_lqfp100/figures/board.png | Bin 0 -> 9670538 bytes
bsp/hc32/ev_hc32f472_lqfp100/project.ewd | 2974 +
bsp/hc32/ev_hc32f472_lqfp100/project.ewp | 2240 +
bsp/hc32/ev_hc32f472_lqfp100/project.eww | 10 +
bsp/hc32/ev_hc32f472_lqfp100/project.uvoptx | 189 +
bsp/hc32/ev_hc32f472_lqfp100/project.uvprojx | 1219 +
bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h | 271 +
bsp/hc32/ev_hc32f472_lqfp100/rtconfig.py | 150 +
bsp/hc32/ev_hc32f472_lqfp100/template.ewp | 1927 +
bsp/hc32/ev_hc32f472_lqfp100/template.eww | 10 +
bsp/hc32/ev_hc32f472_lqfp100/template.uvoptx | 189 +
bsp/hc32/ev_hc32f472_lqfp100/template.uvprojx | 391 +
bsp/hc32/libraries/.ignore_format.yml | 1 +
.../hc32_drivers/drv_flash/drv_flash_f4.c | 8 +
bsp/hc32/libraries/hc32_drivers/drv_gpio.c | 5 +
bsp/hc32/libraries/hc32_drivers/drv_irq.c | 2 +-
bsp/hc32/libraries/hc32_drivers/drv_irq.h | 2 +-
bsp/hc32/libraries/hc32_drivers/drv_pm.c | 4 +-
bsp/hc32/libraries/hc32_drivers/drv_qspi.c | 361 +-
bsp/hc32/libraries/hc32_drivers/drv_qspi.h | 4 +
bsp/hc32/libraries/hc32_drivers/drv_spi.c | 23 +-
bsp/hc32/libraries/hc32_drivers/drv_usart.c | 76 +-
bsp/hc32/libraries/hc32_drivers/drv_usart.h | 2 +-
.../libraries/hc32_drivers/drv_usart_v2.c | 72 +-
.../libraries/hc32_drivers/drv_usart_v2.h | 2 +-
.../hc32/iec60730_class_b_stl/stl_common.h | 145 -
.../hc32/iec60730_class_b_stl/stl_conf.h | 106 -
.../stl_test_item/inc/stl_sw_crc32.h | 93 -
.../stl_test_item/inc/stl_test_cpu.h | 85 -
.../stl_test_item/inc/stl_test_flash.h | 85 -
.../stl_test_item/inc/stl_test_interrupt.h | 99 -
.../stl_test_item/inc/stl_test_pc.h | 84 -
.../stl_test_item/inc/stl_test_ram.h | 88 -
.../src/EWARM/stl_test_cpu_cm0_startup.s | 372 -
.../src/EWARM/stl_test_cpu_cm4_startup.s | 420 -
.../src/EWARM/stl_test_cpu_runtime.s | 245 -
.../src/EWARM/stl_test_full_ram_startup.s | 186 -
.../stl_test_item/src/EWARM/stl_test_pc.s | 148 -
.../src/MDK/stl_test_cpu_cm0_startup.s | 378 -
.../src/MDK/stl_test_cpu_cm4_startup.s | 426 -
.../src/MDK/stl_test_cpu_runtime.s | 251 -
.../src/MDK/stl_test_full_ram_startup.s | 191 -
.../stl_test_item/src/MDK/stl_test_pc.s | 147 -
.../stl_test_item/src/stl_sw_crc32.c | 154 -
.../stl_test_item/src/stl_test_flash.c | 179 -
.../stl_test_item/src/stl_test_interrupt.c | 165 -
.../stl_test_item/src/stl_test_ram_runtime.c | 269 -
.../iec60730_class_b_stl/stl_test_runtime.c | 145 -
.../hc32/iec60730_class_b_stl/stl_utility.c | 236 -
.../hc32/iec60730_class_b_stl/stl_utility.h | 107 -
.../config/linker/HC32F460_ram.icf | 58 -
.../hc32f460_ddl/config/linker/HC32F460xC.icf | 50 -
.../hc32f460_ddl/config/linker/HC32F460xE.icf | 50 -
.../hc32/iec60730_class_b_stl/stl_common.h | 145 -
.../hc32/iec60730_class_b_stl/stl_conf.h | 106 -
.../stl_test_item/inc/stl_sw_crc32.h | 93 -
.../stl_test_item/inc/stl_test_cpu.h | 85 -
.../stl_test_item/inc/stl_test_flash.h | 85 -
.../stl_test_item/inc/stl_test_interrupt.h | 99 -
.../stl_test_item/inc/stl_test_ram.h | 88 -
.../src/EWARM/stl_test_cpu_cm0_startup.s | 372 -
.../src/EWARM/stl_test_cpu_cm4_startup.s | 420 -
.../src/EWARM/stl_test_cpu_runtime.s | 245 -
.../src/EWARM/stl_test_cpu_startup.s | 357 -
.../src/EWARM/stl_test_full_ram_startup.s | 186 -
.../stl_test_item/src/EWARM/stl_test_pc.s | 148 -
.../src/MDK/stl_test_cpu_cm0_startup.s | 378 -
.../src/MDK/stl_test_cpu_cm4_startup.s | 426 -
.../src/MDK/stl_test_cpu_runtime.s | 251 -
.../src/MDK/stl_test_cpu_startup.s | 363 -
.../src/MDK/stl_test_full_ram_startup.s | 191 -
.../stl_test_item/src/MDK/stl_test_pc.s | 147 -
.../stl_test_item/src/stl_sw_crc32.c | 154 -
.../stl_test_item/src/stl_test_flash.c | 179 -
.../stl_test_item/src/stl_test_interrupt.c | 165 -
.../stl_test_item/src/stl_test_ram_runtime.c | 269 -
.../iec60730_class_b_stl/stl_test_runtime.c | 145 -
.../iec60730_class_b_stl/stl_test_runtime.h | 114 -
.../iec60730_class_b_stl/stl_test_startup.c | 120 -
.../hc32/iec60730_class_b_stl/stl_utility.c | 236 -
.../hc32/iec60730_class_b_stl/stl_utility.h | 107 -
.../usb_dev_cdc_msc_wrapper.c | 334 -
.../usb_dev_cdc_msc_wrapper.h | 79 -
.../custom_hid/usb_dev_custom_hid_class.c | 380 -
.../custom_hid/usb_dev_custom_hid_class.h | 130 -
.../usb_dev_hid_cdc_wrapper.c | 362 -
.../usb_dev_hid_cdc_wrapper.h | 74 -
.../hid_keyboard/usb_dev_keyboard_class.c | 330 -
.../hid_keyboard/usb_dev_keyboard_class.h | 99 -
.../hid_mouse/usb_dev_mouse_class.c | 346 -
.../hid_mouse/usb_dev_mouse_class.h | 99 -
.../usb_dev_hid_msc_wrapper.c | 273 -
.../usb_dev_hid_msc_wrapper.h | 80 -
.../device_class/msc/usb_dev_msc_bot.c | 267 -
.../device_class/msc/usb_dev_msc_bot.h | 137 -
.../device_class/msc/usb_dev_msc_class.c | 264 -
.../device_class/msc/usb_dev_msc_class.h | 94 -
.../device_class/msc/usb_dev_msc_data.c | 111 -
.../device_class/msc/usb_dev_msc_data.h | 92 -
.../device_class/msc/usb_dev_msc_mem.h | 90 -
.../device_class/msc/usb_dev_msc_scsi.c | 552 -
.../device_class/msc/usb_dev_msc_scsi.h | 167 -
.../single_cdc/usb_dev_cdc_class.c | 427 -
.../single_cdc/usb_dev_cdc_class.h | 121 -
.../usb_device_lib/device_core/usb_dev_core.c | 344 -
.../usb_device_lib/device_core/usb_dev_core.h | 84 -
.../device_core/usb_dev_ctrleptrans.c | 159 -
.../device_core/usb_dev_ctrleptrans.h | 83 -
.../usb_device_lib/device_core/usb_dev_def.h | 155 -
.../device_core/usb_dev_driver.c | 402 -
.../device_core/usb_dev_driver.h | 90 -
.../usb_device_lib/device_core/usb_dev_int.c | 458 -
.../usb_device_lib/device_core/usb_dev_int.h | 136 -
.../device_core/usb_dev_stdreq.c | 609 -
.../device_core/usb_dev_stdreq.h | 82 -
.../host_class/cdc/usb_host_cdc_class.c | 681 -
.../host_class/cdc/usb_host_cdc_class.h | 165 -
.../host_class/cdc/usb_host_cdc_ctrl.c | 174 -
.../host_class/cdc/usb_host_cdc_ctrl.h | 221 -
.../host_class/hid/usb_host_hid_class.c | 434 -
.../host_class/hid/usb_host_hid_class.h | 167 -
.../host_class/hid/usb_host_hid_keyboardapp.c | 268 -
.../host_class/hid/usb_host_hid_keyboardapp.h | 99 -
.../host_class/hid/usb_host_hid_mouseapp.c | 111 -
.../host_class/hid/usb_host_hid_mouseapp.h | 92 -
.../host_class/msc/usb_host_msc_bot.c | 466 -
.../host_class/msc/usb_host_msc_bot.h | 162 -
.../host_class/msc/usb_host_msc_class.c | 377 -
.../host_class/msc/usb_host_msc_class.h | 110 -
.../host_class/msc/usb_host_msc_fatfs.c | 240 -
.../host_class/msc/usb_host_msc_scsi.c | 524 -
.../host_class/msc/usb_host_msc_scsi.h | 135 -
.../usb_host_lib/host_core/usb_host_cfgch.c | 203 -
.../usb_host_lib/host_core/usb_host_cfgch.h | 101 -
.../usb_host_lib/host_core/usb_host_core.c | 549 -
.../usb_host_lib/host_core/usb_host_core.h | 97 -
.../host_core/usb_host_ctrltrans.c | 319 -
.../host_core/usb_host_ctrltrans.h | 86 -
.../usb/usb_host_lib/host_core/usb_host_def.h | 430 -
.../usb_host_lib/host_core/usb_host_driver.c | 235 -
.../usb_host_lib/host_core/usb_host_driver.h | 90 -
.../usb/usb_host_lib/host_core/usb_host_int.c | 566 -
.../usb/usb_host_lib/host_core/usb_host_int.h | 127 -
.../usb_host_lib/host_core/usb_host_stdreq.c | 483 -
.../usb_host_lib/host_core/usb_host_stdreq.h | 107 -
.../hc32f460_ddl/midwares/hc32/usb/usb_lib.h | 197 -
bsp/hc32/libraries/hc32f472_ddl/ChangeLog.md | 570 +
bsp/hc32/libraries/hc32f472_ddl/LICENSE | 29 +
bsp/hc32/libraries/hc32f472_ddl/SConscript | 96 +
.../Device/HDSC/hc32f4xx/Include/hc32f472.h | 15706 ++++
.../Device/HDSC/hc32f4xx/Include/hc32f4xx.h} | 54 +-
.../HDSC/hc32f4xx/Include/system_hc32f472.h} | 94 +-
.../ARM/flashloader/HC32F472_128K_0.FLM | Bin 0 -> 31656 bytes
.../ARM/flashloader/HC32F472_128K_1.FLM | Bin 0 -> 31656 bytes
.../Source/ARM/flashloader/HC32F472_256K.FLM | Bin 0 -> 31644 bytes
.../Source/ARM/flashloader/HC32F472_512K.FLM | Bin 0 -> 31644 bytes
.../Source/ARM/flashloader/HC32F472_RAM.FLM | Bin 0 -> 13460 bytes
.../Source/ARM/flashloader/HC32F472_otp.FLM | Bin 0 -> 31644 bytes
.../hc32f4xx/Source/ARM/flashloader/ram.ini | 16 +
.../HDSC/hc32f4xx/Source/ARM/sfr/HC32F472.SFR | Bin 0 -> 2230007 bytes
.../hc32f4xx/Source/ARM/startup_hc32f472.s | 718 +
.../hc32f4xx/Source/GCC/startup_hc32f472.S | 613 +
.../HDSC/hc32f4xx/Source/GCC/svd/HC32F472.svd | 73876 ++++++++++++++++
.../Source/IAR/flashloader/FlashHC32F472.mac | 16 +
.../Source/IAR/flashloader/FlashHC32F472.out | Bin 0 -> 48532 bytes
.../IAR/flashloader/FlashHC32F472_otp.flash | 10 +
.../IAR/flashloader/FlashHC32F472_otp.out | Bin 0 -> 47940 bytes
.../IAR/flashloader/FlashHC32F472_qspi.flash | 9 +
.../IAR/flashloader/FlashHC32F472_qspi.out | Bin 0 -> 50048 bytes
.../IAR/flashloader/FlashHC32F472xC.board | 16 +
.../IAR/flashloader/FlashHC32F472xC.flash | 10 +
.../flashloader/FlashHC32F472xC_dual.board | 16 +
.../flashloader/FlashHC32F472xC_dual_0.flash | 10 +
.../flashloader/FlashHC32F472xC_dual_1.flash | 10 +
.../IAR/flashloader/FlashHC32F472xE.board | 16 +
.../IAR/flashloader/FlashHC32F472xE.flash | 10 +
.../hc32f4xx/Source/IAR/startup_hc32f472.s | 1210 +
.../HDSC/hc32f4xx/Source/IAR/svd/HC32F472.svd | 73876 ++++++++++++++++
.../HDSC/hc32f4xx/Source/system_hc32f472.c | 205 +
.../cmsis/Include/arm_common_tables.h | 517 +
.../cmsis/Include/arm_const_structs.h | 76 +
.../cmsis/Include/arm_helium_utils.h | 348 +
.../hc32f472_ddl/cmsis/Include/arm_math.h | 8970 ++
.../cmsis/Include/arm_mve_tables.h | 235 +
.../hc32f472_ddl/cmsis/Include/arm_vec_math.h | 372 +
.../cmsis/Include/cachel1_armv7.h | 411 +
.../hc32f472_ddl/cmsis/Include/cmsis_armcc.h | 885 +
.../cmsis/Include/cmsis_armclang.h | 1467 +
.../cmsis/Include/cmsis_armclang_ltm.h | 1893 +
.../cmsis/Include/cmsis_compiler.h | 283 +
.../hc32f472_ddl/cmsis/Include/cmsis_gcc.h | 2177 +
.../hc32f472_ddl/cmsis/Include/cmsis_iccarm.h | 968 +
.../cmsis/Include/cmsis_version.h | 39 +
.../cmsis/Include/core_armv81mml.h | 4191 +
.../cmsis/Include/core_armv8mbl.h | 2222 +
.../cmsis/Include/core_armv8mml.h | 3196 +
.../hc32f472_ddl/cmsis/Include/core_cm0.h | 952 +
.../hc32f472_ddl/cmsis/Include/core_cm0plus.h | 1087 +
.../hc32f472_ddl/cmsis/Include/core_cm1.h | 979 +
.../hc32f472_ddl/cmsis/Include/core_cm23.h | 2297 +
.../hc32f472_ddl/cmsis/Include/core_cm3.h | 1943 +
.../hc32f472_ddl/cmsis/Include/core_cm33.h | 3264 +
.../hc32f472_ddl/cmsis/Include/core_cm35p.h | 3264 +
.../hc32f472_ddl/cmsis/Include/core_cm4.h | 2129 +
.../hc32f472_ddl/cmsis/Include/core_cm55.h | 4215 +
.../hc32f472_ddl/cmsis/Include/core_cm7.h | 2362 +
.../hc32f472_ddl/cmsis/Include/core_sc000.h | 1030 +
.../hc32f472_ddl/cmsis/Include/core_sc300.h | 1917 +
.../hc32f472_ddl/cmsis/Include/mpu_armv7.h | 275 +
.../hc32f472_ddl/cmsis/Include/mpu_armv8.h | 352 +
.../hc32f472_ddl/cmsis/Include/pmu_armv8.h | 337 +
.../hc32f472_ddl/cmsis/Include/tz_context.h | 70 +
.../hc32f472_ddl/hc32_ll_driver/inc/hc32_ll.h | 343 +
.../hc32_ll_driver/inc/hc32_ll_adc.h | 567 +
.../hc32_ll_driver/inc/hc32_ll_aes.h} | 73 +-
.../hc32_ll_driver/inc/hc32_ll_aos.h | 190 +
.../hc32_ll_driver/inc/hc32_ll_can.h | 721 +
.../hc32_ll_driver/inc/hc32_ll_clk.h | 700 +
.../hc32_ll_driver/inc/hc32_ll_cmp.h | 487 +
.../hc32_ll_driver/inc/hc32_ll_crc.h | 164 +
.../hc32_ll_driver/inc/hc32_ll_ctc.h | 249 +
.../hc32_ll_driver/inc/hc32_ll_dac.h | 190 +
.../hc32_ll_driver/inc/hc32_ll_dbgc.h | 159 +
.../hc32_ll_driver/inc/hc32_ll_dcu.h | 269 +
.../hc32_ll_driver/inc/hc32_ll_def.h | 394 +
.../hc32_ll_driver/inc/hc32_ll_dma.h | 608 +
.../hc32_ll_driver/inc/hc32_ll_efm.h | 704 +
.../hc32_ll_driver/inc/hc32_ll_emb.h | 586 +
.../hc32_ll_driver/inc/hc32_ll_event_port.h | 231 +
.../hc32_ll_driver/inc/hc32_ll_fcg.h | 225 +
.../hc32_ll_driver/inc/hc32_ll_fcm.h | 291 +
.../hc32_ll_driver/inc/hc32_ll_fmac.h | 203 +
.../hc32_ll_driver/inc/hc32_ll_gpio.h | 469 +
.../hc32_ll_driver/inc/hc32_ll_hash.h | 216 +
.../hc32_ll_driver/inc/hc32_ll_i2c.h | 396 +
.../hc32_ll_driver/inc/hc32_ll_icg.h | 440 +
.../hc32_ll_driver/inc/hc32_ll_interrupts.h | 479 +
.../hc32_ll_driver/inc/hc32_ll_keyscan.h | 241 +
.../hc32_ll_driver/inc/hc32_ll_mau.h} | 76 +-
.../hc32_ll_driver/inc/hc32_ll_mdio.h | 269 +
.../hc32_ll_driver/inc/hc32_ll_mpu.h | 456 +
.../hc32_ll_driver/inc/hc32_ll_ots.h | 204 +
.../hc32_ll_driver/inc/hc32_ll_pla.h | 214 +
.../hc32_ll_driver/inc/hc32_ll_pwc.h | 653 +
.../hc32_ll_driver/inc/hc32_ll_qspi.h | 445 +
.../hc32_ll_driver/inc/hc32_ll_rmu.h | 224 +
.../hc32_ll_driver/inc/hc32_ll_rtc.h | 368 +
.../hc32_ll_driver/inc/hc32_ll_smc.h | 365 +
.../hc32_ll_driver/inc/hc32_ll_spi.h | 509 +
.../hc32_ll_driver/inc/hc32_ll_sram.h | 234 +
.../hc32_ll_driver/inc/hc32_ll_swdt.h | 227 +
.../hc32_ll_driver/inc/hc32_ll_tmr0.h | 228 +
.../hc32_ll_driver/inc/hc32_ll_tmr2.h | 356 +
.../hc32_ll_driver/inc/hc32_ll_tmr4.h | 828 +
.../hc32_ll_driver/inc/hc32_ll_tmr6.h | 935 +
.../hc32_ll_driver/inc/hc32_ll_tmra.h | 545 +
.../hc32_ll_driver/inc/hc32_ll_trng.h} | 82 +-
.../hc32_ll_driver/inc/hc32_ll_usart.h | 543 +
.../hc32_ll_driver/inc/hc32_ll_usb.h | 688 +
.../hc32_ll_driver/inc/hc32_ll_utility.h} | 96 +-
.../hc32_ll_driver/inc/hc32_ll_vref.h | 138 +
.../hc32_ll_driver/inc/hc32_ll_wdt.h | 228 +
.../hc32f472_ddl/hc32_ll_driver/src/hc32_ll.c | 170 +
.../hc32_ll_driver/src/hc32_ll_adc.c | 1143 +
.../hc32_ll_driver/src/hc32_ll_aes.c | 316 +
.../hc32_ll_driver/src/hc32_ll_aos.c | 230 +
.../hc32_ll_driver/src/hc32_ll_can.c | 1564 +
.../hc32_ll_driver/src/hc32_ll_clk.c | 1537 +
.../hc32_ll_driver/src/hc32_ll_cmp.c | 852 +
.../hc32_ll_driver/src/hc32_ll_crc.c | 567 +
.../hc32_ll_driver/src/hc32_ll_ctc.c | 525 +
.../hc32_ll_driver/src/hc32_ll_dac.c | 569 +
.../hc32_ll_driver/src/hc32_ll_dbgc.c | 175 +
.../hc32_ll_driver/src/hc32_ll_dcu.c | 552 +
.../hc32_ll_driver/src/hc32_ll_dma.c | 1357 +
.../hc32_ll_driver/src/hc32_ll_efm.c | 1643 +
.../hc32_ll_driver/src/hc32_ll_emb.c | 823 +
.../hc32_ll_driver/src/hc32_ll_event_port.c | 442 +
.../hc32_ll_driver/src/hc32_ll_fcg.c | 194 +
.../hc32_ll_driver/src/hc32_ll_fcm.c | 396 +
.../hc32_ll_driver/src/hc32_ll_fmac.c | 372 +
.../hc32_ll_driver/src/hc32_ll_gpio.c | 745 +
.../hc32_ll_driver/src/hc32_ll_hash.c | 626 +
.../hc32_ll_driver/src/hc32_ll_i2c.c | 1383 +
.../hc32_ll_driver/src/hc32_ll_icg.c} | 130 +-
.../hc32_ll_driver/src/hc32_ll_interrupts.c | 765 +
.../hc32_ll_driver/src/hc32_ll_keyscan.c | 258 +
.../hc32_ll_driver/src/hc32_ll_mau.c | 306 +
.../hc32_ll_driver/src/hc32_ll_mdio.c | 608 +
.../hc32_ll_driver/src/hc32_ll_mpu.c | 1208 +
.../hc32_ll_driver/src/hc32_ll_ots.c | 419 +
.../hc32_ll_driver/src/hc32_ll_pla.c | 420 +
.../hc32_ll_driver/src/hc32_ll_pwc.c | 1191 +
.../hc32_ll_driver/src/hc32_ll_qspi.c | 494 +
.../hc32_ll_driver/src/hc32_ll_rmu.c | 291 +
.../hc32_ll_driver/src/hc32_ll_rtc.c | 946 +
.../hc32_ll_driver/src/hc32_ll_smc.c | 527 +
.../hc32_ll_driver/src/hc32_ll_spi.c | 1151 +
.../hc32_ll_driver/src/hc32_ll_sram.c | 358 +
.../hc32_ll_driver/src/hc32_ll_swdt.c | 257 +
.../hc32_ll_driver/src/hc32_ll_tmr0.c | 624 +
.../hc32_ll_driver/src/hc32_ll_tmr2.c | 808 +
.../hc32_ll_driver/src/hc32_ll_tmr4.c | 2400 +
.../hc32_ll_driver/src/hc32_ll_tmr6.c | 1879 +
.../hc32_ll_driver/src/hc32_ll_tmra.c | 1162 +
.../hc32_ll_driver/src/hc32_ll_trng.c | 261 +
.../hc32_ll_driver/src/hc32_ll_usart.c | 2179 +
.../hc32_ll_driver/src/hc32_ll_usb.c | 1348 +
.../hc32_ll_driver/src/hc32_ll_utility.c | 440 +
.../hc32_ll_driver/src/hc32_ll_vref.c | 236 +
.../hc32_ll_driver/src/hc32_ll_wdt.c | 257 +
.../config/linker/HC32F4A0_RAM.icf | 51 -
.../hc32f4a0_ddl/config/linker/HC32F4A0xG.icf | 53 -
.../hc32f4a0_ddl/config/linker/HC32F4A0xI.icf | 53 -
.../hc32/iec60730_class_b_stl/stl_common.h | 145 -
.../hc32/iec60730_class_b_stl/stl_conf.h | 106 -
.../stl_test_item/inc/stl_sw_crc32.h | 93 -
.../stl_test_item/inc/stl_test_cpu.h | 85 -
.../stl_test_item/inc/stl_test_flash.h | 85 -
.../stl_test_item/inc/stl_test_interrupt.h | 99 -
.../stl_test_item/inc/stl_test_pc.h | 84 -
.../stl_test_item/inc/stl_test_ram.h | 88 -
.../src/EWARM/stl_test_cpu_cm0_startup.s | 372 -
.../src/EWARM/stl_test_cpu_cm4_startup.s | 420 -
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.../src/EWARM/stl_test_cpu_startup.s | 357 -
.../src/EWARM/stl_test_full_ram_startup.s | 186 -
.../stl_test_item/src/EWARM/stl_test_pc.s | 148 -
.../src/MDK/stl_test_cpu_cm0_startup.s | 378 -
.../src/MDK/stl_test_cpu_cm4_startup.s | 426 -
.../src/MDK/stl_test_cpu_runtime.s | 251 -
.../src/MDK/stl_test_cpu_startup.s | 363 -
.../src/MDK/stl_test_full_ram_startup.s | 191 -
.../stl_test_item/src/MDK/stl_test_pc.s | 147 -
.../stl_test_item/src/stl_sw_crc32.c | 154 -
.../stl_test_item/src/stl_test_flash.c | 179 -
.../stl_test_item/src/stl_test_interrupt.c | 165 -
.../stl_test_item/src/stl_test_ram_runtime.c | 269 -
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.../hc32/iec60730_class_b_stl/stl_utility.c | 236 -
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.../usb_dev_cdc_msc_wrapper.c | 334 -
.../usb_dev_cdc_msc_wrapper.h | 79 -
.../custom_hid/usb_dev_custom_hid_class.c | 380 -
.../custom_hid/usb_dev_custom_hid_class.h | 130 -
.../usb_dev_hid_cdc_wrapper.c | 362 -
.../usb_dev_hid_cdc_wrapper.h | 74 -
.../hid_keyboard/usb_dev_keyboard_class.c | 330 -
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.../hid_mouse/usb_dev_mouse_class.c | 346 -
.../hid_mouse/usb_dev_mouse_class.h | 99 -
.../usb_dev_hid_msc_wrapper.c | 273 -
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.../device_class/msc/usb_dev_msc_mem.h | 90 -
.../device_class/msc/usb_dev_msc_scsi.c | 552 -
.../device_class/msc/usb_dev_msc_scsi.h | 167 -
.../single_cdc/usb_dev_cdc_class.c | 427 -
.../single_cdc/usb_dev_cdc_class.h | 121 -
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.../usb_device_lib/device_core/usb_dev_core.h | 84 -
.../device_core/usb_dev_ctrleptrans.c | 159 -
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.../usb_device_lib/device_core/usb_dev_def.h | 155 -
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.../host_class/cdc/usb_host_cdc_class.c | 681 -
.../host_class/cdc/usb_host_cdc_class.h | 165 -
.../host_class/cdc/usb_host_cdc_ctrl.c | 174 -
.../host_class/cdc/usb_host_cdc_ctrl.h | 221 -
.../host_class/hid/usb_host_hid_class.c | 434 -
.../host_class/hid/usb_host_hid_class.h | 167 -
.../host_class/hid/usb_host_hid_keyboardapp.c | 268 -
.../host_class/hid/usb_host_hid_keyboardapp.h | 99 -
.../host_class/hid/usb_host_hid_mouseapp.c | 111 -
.../host_class/hid/usb_host_hid_mouseapp.h | 92 -
.../host_class/msc/usb_host_msc_bot.c | 466 -
.../host_class/msc/usb_host_msc_bot.h | 162 -
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.../host_class/msc/usb_host_msc_class.h | 110 -
.../host_class/msc/usb_host_msc_fatfs.c | 240 -
.../host_class/msc/usb_host_msc_scsi.c | 524 -
.../host_class/msc/usb_host_msc_scsi.h | 135 -
.../usb_host_lib/host_core/usb_host_cfgch.c | 203 -
.../usb_host_lib/host_core/usb_host_cfgch.h | 101 -
.../usb_host_lib/host_core/usb_host_core.c | 549 -
.../usb_host_lib/host_core/usb_host_core.h | 97 -
.../host_core/usb_host_ctrltrans.c | 319 -
.../usb/usb_host_lib/host_core/usb_host_def.h | 430 -
.../usb_host_lib/host_core/usb_host_driver.c | 235 -
.../usb_host_lib/host_core/usb_host_driver.h | 90 -
.../usb/usb_host_lib/host_core/usb_host_int.c | 572 -
.../usb/usb_host_lib/host_core/usb_host_int.h | 127 -
.../usb_host_lib/host_core/usb_host_stdreq.c | 483 -
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.../hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h | 197 -
bsp/hc32/platform/SConscript | 12 +
bsp/hc32/platform/fal/SConscript | 19 +
bsp/hc32/platform/fal/fal_flash_sfud_nor.c | 91 +
bsp/hc32/platform/sfud/SConscript | 18 +
bsp/hc32/platform/sfud/drv_spi_flash.c | 140 +
bsp/hc32/platform/tca9539/SConscript | 18 +
bsp/hc32/platform/tca9539/tca9539.c | 325 +
bsp/hc32/platform/tca9539/tca9539.h | 85 +
453 files changed, 295736 insertions(+), 47893 deletions(-)
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/.config
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/.gitignore
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/Kconfig
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/README.md
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/SConscript
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/SConstruct
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/applications/SConscript
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/applications/main.c
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/SConscript
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create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.sct
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/figures/board.png
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/project.ewd
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create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/project.uvoptx
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create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/rtconfig.py
create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/template.ewp
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create mode 100644 bsp/hc32/ev_hc32f472_lqfp100/template.uvoptx
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delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c
delete mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c
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delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c
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delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c
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delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c
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delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h
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delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_int.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h
delete mode 100644 bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/usb/usb_lib.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/ChangeLog.md
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/LICENSE
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/SConscript
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Include/hc32f472.h
rename bsp/hc32/libraries/{hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h => hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h} (77%)
rename bsp/hc32/libraries/{hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h => hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f472.h} (51%)
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F472_128K_0.FLM
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F472_128K_1.FLM
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F472_256K.FLM
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F472_512K.FLM
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F472_RAM.FLM
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/flashloader/HC32F472_otp.FLM
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f472.s
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f472.S
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F472.svd
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472.mac
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472.out
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472_otp.flash
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472_otp.out
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472_qspi.flash
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472_qspi.out
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472xC.board
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472xC.flash
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472xC_dual.board
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/flashloader/FlashHC32F472xE.flash
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f472.s
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F472.svd
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f472.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_common_tables.h
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_helium_utils.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_math.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_mve_tables.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/arm_vec_math.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cachel1_armv7.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armcc.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armclang.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_armclang_ltm.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_compiler.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_gcc.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_iccarm.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/cmsis_version.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv81mml.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv8mbl.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_armv8mml.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm0.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm0plus.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm1.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm23.h
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm35p.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm4.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm55.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_cm7.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_sc000.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/core_sc300.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/mpu_armv7.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/mpu_armv8.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/pmu_armv8.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/cmsis/Include/tz_context.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_adc.h
rename bsp/hc32/libraries/{hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h => hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_aes.h} (63%)
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_aos.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_can.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_clk.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_cmp.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_crc.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_ctc.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dac.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dbgc.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dcu.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_def.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_dma.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_efm.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_emb.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_event_port.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fcg.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fcm.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_fmac.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_gpio.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_hash.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_i2c.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_icg.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_interrupts.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_keyscan.h
rename bsp/hc32/libraries/{hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.h => hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mau.h} (58%)
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mdio.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_mpu.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_ots.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_pla.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_pwc.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_qspi.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_rmu.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_rtc.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_smc.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_spi.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_sram.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_swdt.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr0.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr2.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr4.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmr6.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_tmra.h
rename bsp/hc32/libraries/{hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h => hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_trng.h} (53%)
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_usart.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_usb.h
rename bsp/hc32/libraries/{hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h => hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_utility.h} (53%)
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_vref.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/inc/hc32_ll_wdt.h
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_adc.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_aes.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_aos.c
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_clk.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_cmp.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_crc.c
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_gpio.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_hash.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_i2c.c
rename bsp/hc32/libraries/{hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c => hc32f472_ddl/hc32_ll_driver/src/hc32_ll_icg.c} (57%)
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_keyscan.c
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_qspi.c
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create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_rtc.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_smc.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_spi.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_sram.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_swdt.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr0.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr2.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr4.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmr6.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_tmra.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_trng.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_usart.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_usb.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_utility.c
create mode 100644 bsp/hc32/libraries/hc32f472_ddl/hc32_ll_driver/src/hc32_ll_vref.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/cdc_msc_composite/usb_dev_cdc_msc_wrapper.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/custom_hid/usb_dev_custom_hid_class.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_keyboard/usb_dev_keyboard_class.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/hid_mouse/usb_dev_mouse_class.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_data.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_mem.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/msc/usb_dev_msc_scsi.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_class/single_cdc/usb_dev_cdc_class.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_core.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_ctrleptrans.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_def.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_driver.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_int.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_device_lib/device_core/usb_dev_stdreq.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_class.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/cdc/usb_host_cdc_ctrl.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_class.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_keyboardapp.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/hid/usb_host_hid_mouseapp.c
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_bot.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_class.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_fatfs.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_class/msc/usb_host_msc_scsi.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_cfgch.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_core.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_ctrltrans.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_def.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_driver.h
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delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.c
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_host_lib/host_core/usb_host_stdreq.h
delete mode 100644 bsp/hc32/libraries/hc32f4a0_ddl/midwares/hc32/usb/usb_lib.h
create mode 100644 bsp/hc32/platform/SConscript
create mode 100644 bsp/hc32/platform/fal/SConscript
create mode 100644 bsp/hc32/platform/fal/fal_flash_sfud_nor.c
create mode 100644 bsp/hc32/platform/sfud/SConscript
create mode 100644 bsp/hc32/platform/sfud/drv_spi_flash.c
create mode 100644 bsp/hc32/platform/tca9539/SConscript
create mode 100644 bsp/hc32/platform/tca9539/tca9539.c
create mode 100644 bsp/hc32/platform/tca9539/tca9539.h
diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml
index 6e959fa124..893cc8023b 100644
--- a/.github/workflows/bsp_buildings.yml
+++ b/.github/workflows/bsp_buildings.yml
@@ -84,6 +84,7 @@ jobs:
- "hc32/ev_hc32f4a0_lqfp176"
- "hc32/ev_hc32f448_lqfp80"
- "hc32/ev_hc32f460_lqfp100_v2"
+ - "hc32/ev_hc32f472_lqfp100"
- "hc32l196"
- "mm32/mm32f3270-100ask-pitaya"
- "mm32f327x"
diff --git a/bsp/hc32/README.md b/bsp/hc32/README.md
index e815037a35..5ab5ea2643 100644
--- a/bsp/hc32/README.md
+++ b/bsp/hc32/README.md
@@ -10,6 +10,7 @@ HC32 系列 BSP 目前支持情况如下表所示：
| [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 |
| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
| [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 |
+| [ev_hc32f472_lqfp100](ev_hc32f472_lqfp100) | 小华 官方 EV_F472_LQ100 开发板 |
| **M1 系列** | |
| **M4 系列** | |
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/.config b/bsp/hc32/ev_hc32f472_lqfp100/.config
new file mode 100644
index 0000000000..bec9351bc7
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/.config
@@ -0,0 +1,1060 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_NANO is not set
+# CONFIG_RT_USING_AMP is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_USING_TINY_FFS is not set
+
+#
+# klibc optimization
+#
+# CONFIG_RT_KLIBC_USING_STDLIB is not set
+# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set
+# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set
+CONFIG_RT_USING_DEBUG=y
+CONFIG_RT_DEBUGING_COLOR=y
+CONFIG_RT_DEBUGING_CONTEXT=y
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
+# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
+CONFIG_RT_VER_NUM=0x50200
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
+# CONFIG_RT_USING_CACHE is not set
+CONFIG_RT_USING_HW_ATOMIC=y
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M4=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_FINSH_USING_OPTION_COMPLETION=y
+
+#
+# DFS: device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_RT_USING_DM is not set
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_KTIME is not set
+# CONFIG_RT_USING_HWTIMER is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+
+#
+# ISO-ANSI C layer
+#
+
+#
+# Timezone and Daylight Saving Time
+#
+# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set
+CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y
+CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8
+CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0
+CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RESOURCE_ID is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_RT_TRACE is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+# CONFIG_PKG_USING_MLIBC is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_CST816X is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_AIP650 is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_BT_ECB02C is not set
+# CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_SPI_TOOLS is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_QPID is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_KISSFFT is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects and Demos
+#
+# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# CONFIG_PKG_USING_ARDUINO_TICKER is not set
+# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_SOC_FAMILY_HC32=y
+CONFIG_SOC_SERIES_HC32F4=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_HC32F472MC=y
+
+#
+# On-chip Drivers
+#
+CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y
+CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y
+CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y
+CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y
+
+#
+# Onboard Peripheral Drivers
+#
+# CONFIG_BSP_USING_TCA9539 is not set
+# CONFIG_BSP_USING_SPI_FLASH is not set
+CONFIG_BSP_USING_EXT_IO=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART1 is not set
+CONFIG_BSP_USING_UART2=y
+CONFIG_BSP_UART2_RX_USING_DMA=y
+CONFIG_BSP_UART2_TX_USING_DMA=y
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_DAC is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_WDT_TMR is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_PM is not set
+# CONFIG_BSP_USING_HWCRYPTO is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_QSPI is not set
+# CONFIG_BSP_USING_PULSE_ENCODER is not set
+# CONFIG_BSP_USING_HWTIMER is not set
+# CONFIG_BSP_USING_SENSOR is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/.gitignore b/bsp/hc32/ev_hc32f472_lqfp100/.gitignore
new file mode 100644
index 0000000000..7221bde019
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/.gitignore
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/Kconfig b/bsp/hc32/ev_hc32f472_lqfp100/Kconfig
new file mode 100644
index 0000000000..79b160b856
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+ string
+ option env="BSP_ROOT"
+ default "."
+
+config RTT_DIR
+ string
+ option env="RTT_ROOT"
+ default "../../.."
+
+config PKGS_DIR
+ string
+ option env="PKGS_ROOT"
+ default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/README.md b/bsp/hc32/ev_hc32f472_lqfp100/README.md
new file mode 100644
index 0000000000..d92669bed8
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/README.md
@@ -0,0 +1,125 @@
+# XHSC EV_F472_LQ100_Rev1.0 开发板 BSP 说明
+
+## 简介
+
+本文档为小华半导体为 EV_F472_LQ100_Rev1.0 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+EV_F472_LQ100_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F472PETI 芯片，基于 ARM Cortex-M4 内核，最高主频 120 MHz，具有丰富的板载资源，可以充分发挥 HC32F472PETI 的芯片性能。
+
+开发板外观如下图所示：
+
+ 
+
+EV_F472_LQ100_Rev1.0 开发板常用 **板载资源** 如下：
+
+- **MCU**
+ - HC32F472PETI
+ - 主频120MHz
+ - 512KB FLASH
+ - 68KB RAM
+- **外部Memory**
+ - BL24C256（EEPROM, 256Kbits）
+ - W25Q64（SPI NOR，64MB）
+ - IS62WV51216（SRAM， 1MB）
+- **常用外设**
+ - LED: 4 个，User LED（LED0，LED1，LED2，LED5）。
+ - 按键: 9 个，矩阵键盘（K1~K9）， WAKEUP（K10），RESET（K0）
+- **常用接口**
+ - USB转串口
+ - CAN DB9接口 * 3
+ - SmartCard接口
+ - I2C/USART/SPI接口
+- **调试接口**
+ - 板载DAP调试器
+ - 标准JTAG/SWD/Trace
+
+开发板更多详细信息请参考小华半导体半导体[EV_F472_LQ100_Rev1.0](https://www.xhsc.com.cn)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注** |
+| :------------ | :-----------: | :-----------------------------------: |
+| USB 转串口 | 支持 | 使用 UART2 |
+| LED | 支持 | LED1~4 |
+
+| **片上外设** | **支持情况** | **备注** |
+| :------------ | :-----------: | :-----------------------------------: |
+| GPIO | 支持 | PA0, PA1... PF8 ---> PIN: 0, 1...88 |
+| I2C | 支持 | 软件模拟
硬件I2C1~2
I2C1支持EEPROM（BL24C256） |
+| SPI | 支持 | SPI1~3
SPI1支持W25Q |
+| QSPI | 支持 | 支持W25Q |
+| UART | 支持 | UART1~6
UART2为console使用 |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+ 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+ 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用Type-A to MircoUSB线连接开发板和PC供电。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED5会周期性闪烁。
+
+USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
+
+```
+ \ | /
+- RT - Thread Operating System
+ / | \ 5.0.1 build Feb 4 2024 16:44:26
+ 2006 - 2022 Copyright by RT-Thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+## 注意事项
+无
+## 联系人信息
+
+维护人:
+
+- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：
\ No newline at end of file
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/SConscript b/bsp/hc32/ev_hc32f472_lqfp100/SConscript
new file mode 100644
index 0000000000..20f7689c53
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/SConstruct b/bsp/hc32/ev_hc32f472_lqfp100/SConstruct
new file mode 100644
index 0000000000..ccb90b0a4f
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/SConstruct
@@ -0,0 +1,64 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+ RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+ RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+ from building import *
+except:
+ print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+ print(RTT_ROOT)
+ exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+ AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+ CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+ AR = rtconfig.AR, ARFLAGS = '-rc',
+ CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+ LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+ env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+ env.Replace(ARFLAGS = [''])
+ env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+ libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+ libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hc32_library = 'hc32f472_ddl'
+rtconfig.BSP_LIBRARY_TYPE = hc32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
+
+# include platform
+platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
+objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/applications/SConscript b/bsp/hc32/ev_hc32f472_lqfp100/applications/SConscript
new file mode 100644
index 0000000000..9bb9abae89
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/applications/SConscript
@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+ if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+ group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/applications/main.c b/bsp/hc32/ev_hc32f472_lqfp100/applications/main.c
new file mode 100644
index 0000000000..e6f0882ec2
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/applications/main.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#include
+#include
+#include
+
+/* defined the LED_GREEN pin: PC9 */
+#define LED_GREEN_PIN GET_PIN(C, 9)
+
+int main(void)
+{
+ /* set LED_GREEN_PIN pin mode to output */
+ rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
+
+ while (1)
+ {
+ rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
+ rt_thread_mdelay(500);
+ rt_pin_write(LED_GREEN_PIN, PIN_LOW);
+ rt_thread_mdelay(500);
+ }
+}
+
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c
new file mode 100644
index 0000000000..0e35671323
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+#include
+#include
+#include
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+
+#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
+
+/**
+ * @brief This thread is used to monitor whether XTAL32 is stable.
+ * This thread only runs once after the system starts.
+ * When stability is detected or 2s times out, the thread will end.
+ * (When a timeout occurs it will be prompted via rt_kprintf)
+ */
+void xtal32_fcm_thread_entry(void *parameter)
+{
+ stc_fcm_init_t stcFcmInit;
+ uint32_t u32TimeOut = 0UL;
+ uint32_t u32Time = 200UL; /* 200*10ms = 2s */
+
+ /* FCM config */
+ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
+ (void)FCM_StructInit(&stcFcmInit);
+ stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
+ stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
+ stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
+ stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
+ stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
+ stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
+ stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
+ (void)FCM_Init(&stcFcmInit);
+ /* Enable FCM, to ensure xtal32 stable */
+ FCM_Cmd(ENABLE);
+
+ while (1)
+ {
+ if (SET == FCM_GetStatus(FCM_FLAG_END))
+ {
+ FCM_ClearStatus(FCM_FLAG_END);
+ if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
+ {
+ FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
+ }
+ else
+ {
+ (void)FCM_DeInit();
+ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+ /* XTAL32 stabled */
+ break;
+ }
+ }
+ u32TimeOut++;
+ if (u32TimeOut > u32Time)
+ {
+ (void)FCM_DeInit();
+ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+ rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
+ break;
+ }
+ rt_thread_mdelay(10);
+ }
+}
+
+int xtal32_fcm_thread_create(void)
+{
+ rt_thread_t tid;
+
+ tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
+ XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
+ if (tid != RT_NULL)
+ {
+ rt_thread_startup(tid);
+ }
+ else
+ {
+ rt_kprintf("create xtal32_fcm thread err!");
+ }
+ return RT_EOK;
+}
+INIT_APP_EXPORT(xtal32_fcm_thread_create);
+
+#endif
+
+
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig b/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig
new file mode 100644
index 0000000000..2570a6215e
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig
@@ -0,0 +1,671 @@
+menu "Hardware Drivers Config"
+
+config SOC_HC32F472MC
+ bool
+ select SOC_SERIES_HC32F4
+ select RT_USING_COMPONENTS_INIT
+ select RT_USING_USER_MAIN
+ default y
+
+menu "On-chip Drivers"
+ menuconfig BSP_USING_ON_CHIP_FLASH_CACHE
+ bool "Enable on-chip Flash Cache"
+ default y
+ if BSP_USING_ON_CHIP_FLASH_CACHE
+ config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE
+ bool "Enable on-chip Flash ICODE Cache"
+ default y
+ config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE
+ bool "Enable on-chip Flash DCODE Cache"
+ default y
+ config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH
+ bool "Enable on-chip Flash ICODE Prefetch"
+ default y
+ endif
+endmenu
+
+menu "Onboard Peripheral Drivers"
+ config BSP_USING_TCA9539
+ bool "Enable TCA9539"
+ select BSP_USING_I2C
+ select BSP_USING_I2C1
+ default n
+
+ config BSP_USING_SPI_FLASH
+ bool "Enable SPI FLASH (w25q64 spi1)"
+ select BSP_USING_SPI
+ select BSP_USING_SPI1
+ select BSP_USING_ON_CHIP_FLASH
+ select RT_USING_SFUD
+ select RT_USING_DFS
+ select RT_USING_FAL
+ select RT_USING_MTD_NOR
+ default n
+
+ config BSP_USING_EXT_IO
+ bool
+ default y
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+ config BSP_USING_GPIO
+ bool "Enable GPIO"
+ select RT_USING_PIN
+ default y
+
+ menuconfig BSP_USING_UART
+ bool "Enable UART"
+ default y
+ select RT_USING_SERIAL
+ if BSP_USING_UART
+ menuconfig BSP_USING_UART1
+ bool "Enable UART1"
+ default y
+ if BSP_USING_UART1
+ config BSP_UART1_RX_USING_DMA
+ bool "Enable UART1 RX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART1_TX_USING_DMA
+ bool "Enable UART1 TX DMA"
+ depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART1_RX_BUFSIZE
+ int "Set UART1 RX buffer size"
+ range 64 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+
+ config BSP_UART1_TX_BUFSIZE
+ int "Set UART1 TX buffer size"
+ range 0 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+ endif
+
+ menuconfig BSP_USING_UART2
+ bool "Enable UART2"
+ default n
+ if BSP_USING_UART2
+ config BSP_UART2_RX_USING_DMA
+ bool "Enable UART2 RX DMA"
+ depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART2_TX_USING_DMA
+ bool "Enable UART2 TX DMA"
+ depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART2_RX_BUFSIZE
+ int "Set UART2 RX buffer size"
+ range 64 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+
+ config BSP_UART2_TX_BUFSIZE
+ int "Set UART2 TX buffer size"
+ range 0 65535
+ depends on RT_USING_SERIAL_V2
+ default 0
+ endif
+
+ menuconfig BSP_USING_UART3
+ bool "Enable UART3"
+ default n
+ if BSP_USING_UART3
+ config BSP_UART3_RX_BUFSIZE
+ int "Set UART3 RX buffer size"
+ range 64 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+
+ config BSP_UART3_TX_BUFSIZE
+ int "Set UART3 TX buffer size"
+ range 0 65535
+ depends on RT_USING_SERIAL_V2
+ default 0
+ endif
+
+ menuconfig BSP_USING_UART4
+ bool "Enable UART4"
+ default n
+ if BSP_USING_UART4
+ config BSP_UART4_RX_USING_DMA
+ bool "Enable UART4 RX DMA"
+ depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART4_TX_USING_DMA
+ bool "Enable UART4 TX DMA"
+ depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART4_RX_BUFSIZE
+ int "Set UART4 RX buffer size"
+ range 64 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+
+ config BSP_UART4_TX_BUFSIZE
+ int "Set UART4 TX buffer size"
+ range 0 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+ endif
+
+ menuconfig BSP_USING_UART5
+ bool "Enable UART5"
+ default n
+ if BSP_USING_UART5
+ config BSP_UART5_RX_USING_DMA
+ bool "Enable UART5 RX DMA"
+ depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART5_TX_USING_DMA
+ bool "Enable UART5 TX DMA"
+ depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+ default n
+
+ config BSP_UART5_RX_BUFSIZE
+ int "Set UART5 RX buffer size"
+ range 64 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+
+ config BSP_UART5_TX_BUFSIZE
+ int "Set UART5 TX buffer size"
+ range 0 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+ endif
+
+ menuconfig BSP_USING_UART6
+ bool "Enable UART6"
+ default n
+ if BSP_USING_UART6
+ config BSP_UART6_RX_BUFSIZE
+ int "Set UART6 RX buffer size"
+ range 64 65535
+ depends on RT_USING_SERIAL_V2
+ default 256
+
+ config BSP_UART6_TX_BUFSIZE
+ int "Set UART6 TX buffer size"
+ range 0 65535
+ depends on RT_USING_SERIAL_V2
+ default 0
+ endif
+ endif
+
+ menuconfig BSP_USING_I2C
+ bool "Enable I2C BUS"
+ default n
+ select RT_USING_I2C
+
+ if BSP_USING_I2C
+ menuconfig BSP_USING_I2C1_SW
+ bool "Enable I2C1 BUS (software simulation)"
+ default n
+ select RT_USING_I2C_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_I2C1_SW
+ config BSP_I2C1_SCL_PIN
+ int "i2c1 scl pin number"
+ range 1 176
+ default 51
+ config BSP_I2C1_SDA_PIN
+ int "I2C1 sda pin number"
+ range 1 176
+ default 90
+ endif
+ endif
+
+ if BSP_USING_I2C
+ config BSP_I2C_USING_DMA
+ bool
+ default n
+ config BSP_USING_I2C_HW
+ bool
+ default n
+
+ menuconfig BSP_USING_I2C1
+ bool "Enable I2C1 BUS"
+ default n
+ select BSP_USING_I2C_HW
+ if BSP_USING_I2C1
+ config BSP_I2C1_USING_DMA
+ bool
+ default n
+ config BSP_I2C1_TX_USING_DMA
+ bool "Enable I2C1 TX DMA"
+ default n
+ select BSP_I2C_USING_DMA
+ select BSP_I2C1_USING_DMA
+ config BSP_I2C1_RX_USING_DMA
+ bool "Enable I2C1 RX DMA"
+ default n
+ select BSP_I2C_USING_DMA
+ select BSP_I2C1_USING_DMA
+ endif
+
+ menuconfig BSP_USING_I2C2
+ bool "Enable I2C2 BUS"
+ default n
+ select BSP_USING_I2C_HW
+ if BSP_USING_I2C2
+ config BSP_I2C2_USING_DMA
+ bool
+ default n
+ config BSP_I2C2_TX_USING_DMA
+ bool "Enable I2C2 TX DMA"
+ default n
+ select BSP_I2C_USING_DMA
+ select BSP_I2C2_USING_DMA
+ config BSP_I2C2_RX_USING_DMA
+ bool "Enable I2C2 RX DMA"
+ default n
+ select BSP_I2C_USING_DMA
+ select BSP_I2C2_USING_DMA
+ endif
+ endif
+
+ config BSP_USING_ON_CHIP_FLASH
+ bool "Enable on-chip FLASH"
+ default n
+
+ menuconfig BSP_USING_SPI
+ bool "Enable SPI BUS"
+ default n
+ select RT_USING_SPI
+ if BSP_USING_SPI
+ config BSP_SPI_USING_DMA
+ bool
+ default n
+
+ menuconfig BSP_USING_SPI1
+ bool "Enable SPI1 BUS"
+ default n
+ if BSP_USING_SPI1
+ config BSP_SPI1_TX_USING_DMA
+ bool "Enable SPI1 TX DMA"
+ select BSP_SPI_USING_DMA
+ default n
+ config BSP_SPI1_RX_USING_DMA
+ bool "Enable SPI1 RX DMA"
+ select BSP_SPI_USING_DMA
+ select BSP_SPI1_TX_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI2
+ bool "Enable SPI2 BUS"
+ default n
+ if BSP_USING_SPI2
+ config BSP_SPI2_TX_USING_DMA
+ bool "Enable SPI2 TX DMA"
+ select BSP_SPI_USING_DMA
+ default n
+ config BSP_SPI2_RX_USING_DMA
+ bool "Enable SPI2 RX DMA"
+ select BSP_SPI_USING_DMA
+ select BSP_SPI2_TX_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI3
+ bool "Enable SPI3 BUS"
+ default n
+ if BSP_USING_SPI3
+ config BSP_SPI3_TX_USING_DMA
+ bool "Enable SPI3 TX DMA"
+ select BSP_SPI_USING_DMA
+ default n
+ config BSP_SPI3_RX_USING_DMA
+ bool "Enable SPI3 RX DMA"
+ select BSP_SPI_USING_DMA
+ select BSP_SPI3_TX_USING_DMA
+ default n
+ endif
+
+ menuconfig BSP_USING_SPI4
+ bool "Enable SPI4 BUS"
+ default n
+ if BSP_USING_SPI4
+ config BSP_SPI4_TX_USING_DMA
+ bool "Enable SPI4 TX DMA"
+ select BSP_SPI_USING_DMA
+ default n
+ config BSP_SPI4_RX_USING_DMA
+ bool "Enable SPI4 RX DMA"
+ select BSP_SPI_USING_DMA
+ select BSP_SPI4_TX_USING_DMA
+ default n
+ endif
+ endif
+
+ menuconfig BSP_USING_ADC
+ bool "Enable ADC"
+ default n
+ select RT_USING_ADC
+ if BSP_USING_ADC
+ menuconfig BSP_USING_ADC1
+ bool "Enable ADC1"
+ default n
+ if BSP_USING_ADC1
+ config BSP_ADC1_USING_DMA
+ bool "using adc1 dma"
+ default n
+ endif
+ menuconfig BSP_USING_ADC2
+ bool "Enable ADC2"
+ default n
+ if BSP_USING_ADC2
+ config BSP_ADC2_USING_DMA
+ bool "using adc2 dma"
+ default n
+ endif
+ menuconfig BSP_USING_ADC3
+ bool "Enable ADC3"
+ default n
+ if BSP_USING_ADC3
+ config BSP_ADC3_USING_DMA
+ bool "using adc3 dma"
+ default n
+ endif
+ endif
+
+ menuconfig BSP_USING_DAC
+ bool "Enable DAC"
+ default n
+ select RT_USING_DAC
+ if BSP_USING_DAC
+ config BSP_USING_DAC1
+ bool "using dac1"
+ default n
+ config BSP_USING_DAC2
+ bool "using dac2"
+ default n
+ endif
+
+ menuconfig BSP_USING_CAN
+ bool "Enable CAN"
+ default n
+ select RT_USING_CAN
+ select RT_CAN_USING_HDR
+ select BSP_USING_TCA9539
+ if BSP_USING_CAN
+ config BSP_USING_CAN1
+ bool "using can1"
+ default n
+ config BSP_USING_CAN2
+ bool "using can2"
+ default n
+ endif
+
+ menuconfig BSP_USING_WDT_TMR
+ bool "Enable Watchdog Timer"
+ default n
+ select RT_USING_WDT
+ if BSP_USING_WDT_TMR
+ choice
+ prompt "Select SWDT/WDT"
+ default BSP_USING_SWDT
+
+ config BSP_USING_SWDT
+ bool "SWDT(3.72hour(max))"
+ config BSP_USING_WDT
+ bool "WDT(10.7s(max))"
+ endchoice
+
+ config BSP_WDT_CONTINUE_COUNT
+ bool "Low Power Mode Keeps Counting"
+ default n
+ endif
+
+ menuconfig BSP_USING_RTC
+ bool "Enable RTC"
+ select RT_USING_RTC
+ default n
+ if BSP_USING_RTC
+ choice
+ prompt "Select clock source"
+ default BSP_RTC_USING_XTAL32
+
+ config BSP_RTC_USING_XTAL32
+ bool "RTC USING XTAL32"
+
+ config BSP_RTC_USING_LRC
+ bool "RTC USING LRC"
+ endchoice
+ endif
+
+ menuconfig BSP_USING_PM
+ bool "Enable PM"
+ default n
+ select RT_USING_PM
+ if BSP_USING_PM
+ choice
+ prompt "Select WKTM Clock Src"
+ default BSP_USING_WKTM_LRC
+
+ config BSP_USING_WKTM_XTAL32
+ bool "Using Xtal32"
+ config BSP_USING_WKTM_LRC
+ bool "Using LRC"
+ if BSP_RTC_USING_XTAL32
+ config BSP_USING_WKTM_64HZ
+ bool "Using 64HZ(Note:must use XTAL32 and run RTC)"
+ endif
+ endchoice
+ endif
+
+ menuconfig BSP_USING_HWCRYPTO
+ bool "Using Hardware Crypto drivers"
+ default n
+ select RT_USING_HWCRYPTO
+ if BSP_USING_HWCRYPTO
+ config BSP_USING_UQID
+ bool "Enable UQID (unique id)"
+ default n
+
+ config BSP_USING_RNG
+ bool "Using Hardware RNG"
+ default n
+ select RT_HWCRYPTO_USING_RNG
+
+ config BSP_USING_CRC
+ bool "Using Hardware CRC"
+ default n
+ select RT_HWCRYPTO_USING_CRC
+
+ config BSP_USING_AES
+ bool "Using Hardware AES"
+ default n
+ select RT_HWCRYPTO_USING_AES
+ if BSP_USING_AES
+ choice
+ prompt "Select AES Mode"
+ default BSP_USING_AES_ECB
+
+ config BSP_USING_AES_ECB
+ bool "ECB mode"
+ select RT_HWCRYPTO_USING_AES_ECB
+ endchoice
+ endif
+
+ config BSP_USING_HASH
+ bool "Using Hardware Hash"
+ default n
+ select RT_HWCRYPTO_USING_SHA2
+ if BSP_USING_HASH
+ choice
+ prompt "Select Hash Mode"
+ default BSP_USING_SHA2_256
+
+ config BSP_USING_SHA2_256
+ bool "SHA2_256 Mode"
+ select RT_HWCRYPTO_USING_SHA2_256
+ endchoice
+ endif
+
+ endif
+
+ menuconfig BSP_USING_PWM
+ bool "Enable output PWM"
+ default n
+ select RT_USING_PWM
+ if BSP_USING_PWM
+ menuconfig BSP_USING_PWM_TMRA
+ bool "Enable timerA output PWM"
+ default n
+ if BSP_USING_PWM_TMRA
+ menuconfig BSP_USING_PWM_TMRA_1
+ bool "Enable timerA-1 output PWM"
+ default n
+ if BSP_USING_PWM_TMRA_1
+ config BSP_USING_PWM_TMRA_1_CH1
+ bool "Enable timerA-1 channel1"
+ default n
+ config BSP_USING_PWM_TMRA_1_CH2
+ bool "Enable timerA-1 channel2"
+ default n
+ endif
+ menuconfig BSP_USING_PWM_TMRA_2
+ bool "Enable timerA-2 output PWM"
+ default n
+ if BSP_USING_PWM_TMRA_2
+ config BSP_USING_PWM_TMRA_2_CH1
+ bool "Enable timerA-2 channel1"
+ default n
+ config BSP_USING_PWM_TMRA_2_CH2
+ bool "Enable timerA-2 channel2"
+ default n
+ endif
+ endif
+ menuconfig BSP_USING_PWM_TMR4
+ bool "Enable timer4 output PWM"
+ default n
+ if BSP_USING_PWM_TMR4
+ menuconfig BSP_USING_PWM_TMR4_1
+ bool "Enable timer4-1 output PWM"
+ default n
+ if BSP_USING_PWM_TMR4_1
+ config BSP_USING_PWM_TMR4_1_OUH
+ bool "Enable TMR4_1_OUH channel0"
+ default n
+ config BSP_USING_PWM_TMR4_1_OUL
+ bool "Enable TMR4_1_OUL channel1"
+ default n
+ config BSP_USING_PWM_TMR4_1_OVH
+ bool "Enable TMR4_1_OVH channel2"
+ default n
+ config BSP_USING_PWM_TMR4_1_OVL
+ bool "Enable TMR4_1_OVL channel3"
+ default n
+ config BSP_USING_PWM_TMR4_1_OWH
+ bool "Enable TMR4_1_OWH channel4"
+ default n
+ config BSP_USING_PWM_TMR4_1_OWL
+ bool "Enable TMR4_1_OWL channel5"
+ default n
+ endif
+ endif
+ menuconfig BSP_USING_PWM_TMR6
+ bool "Enable timer6 output PWM"
+ default n
+ if BSP_USING_PWM_TMR6
+ menuconfig BSP_USING_PWM_TMR6_1
+ bool "Enable timer6-1 output PWM"
+ default n
+ if BSP_USING_PWM_TMR6_1
+ config BSP_USING_PWM_TMR6_1_A
+ bool "Enable TMR6_1_A channel0"
+ default n
+ config BSP_USING_PWM_TMR6_1_B
+ bool "Enable TMR6_1_B channel1"
+ default n
+ endif
+ endif
+ endif
+
+ menuconfig BSP_USING_QSPI
+ bool "Enable QSPI BUS"
+ select RT_USING_QSPI
+ select RT_USING_SPI
+ default n
+ if BSP_USING_QSPI
+ config BSP_QSPI_USING_DMA
+ bool "Enable QSPI DMA support"
+ default n
+ config BSP_QSPI_USING_SOFT_CS
+ bool "Enable QSPI Soft CS Pin"
+ default n
+ endif
+
+ menuconfig BSP_USING_PULSE_ENCODER
+ bool "Enable Pulse Encoder"
+ default n
+ select RT_USING_PULSE_ENCODER
+ if BSP_USING_PULSE_ENCODER
+ menuconfig BSP_USING_TMRA_PULSE_ENCODER
+ bool "Use TIMERA As The Pulse Encoder"
+ default n
+ if BSP_USING_TMRA_PULSE_ENCODER
+ config BSP_USING_PULSE_ENCODER_TMRA_1
+ bool "Use TIMERA_1 As The Pulse Encoder"
+ default n
+ endif
+ menuconfig BSP_USING_TMR6_PULSE_ENCODER
+ bool "Use TIMER6 As The Pulse Encoder"
+ default n
+ if BSP_USING_TMR6_PULSE_ENCODER
+ config BSP_USING_PULSE_ENCODER_TMR6_1
+ bool "Use TIMER6_1 As The Pulse Encoder"
+ default n
+ endif
+ endif
+
+ menuconfig BSP_USING_HWTIMER
+ bool "Enable Hw Timer"
+ default n
+ select RT_USING_HWTIMER
+ if BSP_USING_HWTIMER
+ config BSP_USING_TMRA_1
+ bool "Use Timer_a1 As The Hw Timer"
+ default n
+ config BSP_USING_TMRA_2
+ bool "Use Timer_a2 As The Hw Timer"
+ default n
+ config BSP_USING_TMRA_3
+ bool "Use Timer_a3 As The Hw Timer"
+ default n
+ config BSP_USING_TMRA_4
+ bool "Use Timer_a4 As The Hw Timer"
+ default n
+ config BSP_USING_TMRA_5
+ bool "Use Timer_a5 As The Hw Timer"
+ default n
+ endif
+
+ menuconfig BSP_USING_SENSOR
+ bool "Enable SENSOR"
+ default n
+ select RT_USING_HWTIMER
+ if BSP_USING_SENSOR
+ config BSP_USING_TMR0_2B
+ bool "Use KEYSCAN"
+ select RT_USING_KEYSCAN
+ default n
+ endif
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/SConscript b/bsp/hc32/ev_hc32f472_lqfp100/board/SConscript
new file mode 100644
index 0000000000..429909d14a
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/SConscript
@@ -0,0 +1,31 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+board_config.c
+''')
+
+path = [cwd]
+path += [cwd + '/ports']
+path += [cwd + '/config']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+ src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f472.S']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+ src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f472.s']
+elif rtconfig.PLATFORM in ['iccarm']:
+ src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f472.s']
+
+CPPDEFINES = ['HC32F472', '__DEBUG']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board.c b/bsp/hc32/ev_hc32f472_lqfp100/board/board.c
new file mode 100644
index 0000000000..27458288c8
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#include "board.h"
+#include "board_config.h"
+
+/* unlock/lock peripheral */
+#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
+ LL_PERIPH_PWC_CLK_RMU)
+#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG)
+
+/** System Base Configuration
+*/
+void SystemBase_Config(void)
+{
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
+ EFM_ICacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
+ EFM_DCacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
+ EFM_PrefetchCmd(ENABLE);
+#endif
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+ stc_clock_xtal_init_t stcXtalInit;
+ stc_clock_pll_init_t stcPLLHInit;
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+ stc_clock_xtal32_init_t stcXtal32Init;
+#endif
+
+ /* PCLK0, HCLK Max 200MHz */
+ /* PCLK1, PCLK4 Max 100MHz */
+ /* PCLK2, EXCLK Max 60MHz */
+ /* PCLK3 Max 50MHz */
+ CLK_SetClockDiv(CLK_BUS_CLK_ALL,
+ (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
+ CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 |
+ CLK_HCLK_DIV1));
+
+ GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
+ (void)CLK_XtalStructInit(&stcXtalInit);
+ /* Config Xtal and enable Xtal */
+ stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
+ stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
+ stcXtalInit.u8State = CLK_XTAL_ON;
+ stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
+ (void)CLK_XtalInit(&stcXtalInit);
+
+ (void)CLK_PLLStructInit(&stcPLLHInit);
+ /* VCO = (12/1)*40 = 480MHz*/
+ stcPLLHInit.u8PLLState = CLK_PLL_ON;
+ stcPLLHInit.PLLCFGR = 0UL;
+ stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
+ stcPLLHInit.PLLCFGR_f.PLLN = 40UL - 1UL;
+ stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
+ stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+ stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+ stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
+ (void)CLK_PLLInit(&stcPLLHInit);
+
+ /* 0-wait @ 40MHz */
+ (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE2);
+ /* 2 cycles for 100 ~ 150MHz */
+ GPIO_SetReadWaitCycle(GPIO_RD_WAIT2);
+ CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+ /* Xtal32 config */
+ GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
+ (void)CLK_Xtal32StructInit(&stcXtal32Init);
+ stcXtal32Init.u8State = CLK_XTAL32_ON;
+ stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
+ stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
+ (void)CLK_Xtal32Init(&stcXtal32Init);
+#endif
+}
+
+/** Peripheral Clock Configuration
+*/
+void PeripheralClock_Config(void)
+{
+#if defined(BSP_USING_CAN1)
+ CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+#if defined(BSP_USING_CAN2)
+ CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+
+#if defined(RT_USING_ADC)
+ CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
+#endif
+}
+
+/** Peripheral Registers Unlock
+*/
+void PeripheralRegister_Unlock(void)
+{
+ LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
+}
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board.h b/bsp/hc32/ev_hc32f472_lqfp100/board/board.h
new file mode 100644
index 0000000000..507ecca31f
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include
+#include "hc32_ll.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
+#define HC32_FLASH_SIZE (512 * 1024)
+#define HC32_FLASH_START_ADDRESS (0)
+#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
+
+#define HC32_SRAM_SIZE (64)
+#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RW_IRAM2$$ZI$$Limit;
+#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN (&__bss_end)
+#endif
+
+#define HEAP_END HC32_SRAM_END
+
+void PeripheralRegister_Unlock(void);
+void PeripheralClock_Config(void);
+void SystemBase_Config(void);
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c
new file mode 100644
index 0000000000..35f186d5b4
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#include
+#include "board_config.h"
+#if defined(RT_USING_CAN)
+#include "tca9539_port.h"
+#endif
+
+/**
+ * The below functions will initialize HC32 board.
+ */
+
+#if defined RT_USING_SERIAL
+rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
+{
+ rt_err_t result = RT_EOK;
+
+ switch ((rt_uint32_t)USARTx)
+ {
+#if defined(BSP_USING_UART1)
+ case (rt_uint32_t)CM_USART1:
+ /* Configure USART RX/TX pin. */
+ GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC);
+ GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC);
+ break;
+#endif
+#if defined(BSP_USING_UART2)
+ case (rt_uint32_t)CM_USART2:
+ /* Configure USART RX/TX pin. */
+ GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, USART2_RX_FUNC);
+ GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, USART2_TX_FUNC);
+ break;
+#endif
+#if defined(BSP_USING_UART5)
+ case (rt_uint32_t)CM_USART5:
+ /* Configure USART RX/TX pin. */
+ GPIO_SetFunc(USART5_RX_PORT, USART5_RX_PIN, USART5_RX_FUNC);
+ GPIO_SetFunc(USART5_TX_PORT, USART5_TX_PIN, USART5_TX_FUNC);
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+
+ return result;
+}
+#endif
+
+#if defined(RT_USING_I2C)
+rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx)
+{
+ rt_err_t result = RT_EOK;
+ stc_gpio_init_t stcGpioInit;
+ (void)GPIO_StructInit(&stcGpioInit);
+
+ switch ((rt_uint32_t)I2Cx)
+ {
+#if defined(BSP_USING_I2C1)
+ case (rt_uint32_t)CM_I2C1:
+ /* Configure I2C1 SDA/SCL pin. */
+ GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC);
+ GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC);
+ break;
+#endif
+#if defined(BSP_USING_I2C2)
+ case (rt_uint32_t)CM_I2C2:
+ /* Configure I2C2 SDA/SCL pin. */
+ GPIO_SetFunc(I2C2_SDA_PORT, I2C2_SDA_PIN, I2C2_SDA_FUNC);
+ GPIO_SetFunc(I2C2_SCL_PORT, I2C2_SCL_PIN, I2C2_SCL_FUNC);
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+ return result;
+}
+#endif
+
+#if defined(RT_USING_ADC)
+rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
+{
+ rt_err_t result = RT_EOK;
+ stc_gpio_init_t stcGpioInit;
+
+ (void)GPIO_StructInit(&stcGpioInit);
+ stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+ switch ((rt_uint32_t)ADCx)
+ {
+#if defined(BSP_USING_ADC1)
+ case (rt_uint32_t)CM_ADC1:
+ (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
+ break;
+#endif
+#if defined(BSP_USING_ADC2)
+ case (rt_uint32_t)CM_ADC2:
+ (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
+ break;
+#endif
+#if defined(BSP_USING_ADC3)
+ case (rt_uint32_t)CM_ADC3:
+ (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+
+ return result;
+}
+#endif
+
+#if defined(RT_USING_DAC)
+rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
+{
+ rt_err_t result = RT_EOK;
+ stc_gpio_init_t stcGpioInit;
+
+ (void)GPIO_StructInit(&stcGpioInit);
+ stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+ switch ((rt_uint32_t)DACx)
+ {
+#if defined(BSP_USING_DAC1)
+ case (rt_uint32_t)CM_DAC1:
+ (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
+ (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+
+ return result;
+}
+#endif
+
+#if defined(RT_USING_CAN)
+void CanPhyEnable(void)
+{
+#if defined(BSP_USING_CAN1)
+ TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET);
+ TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT);
+#endif
+#if defined(BSP_USING_CAN2)
+ TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET);
+ TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
+#endif
+}
+rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
+{
+ rt_err_t result = RT_EOK;
+
+ switch ((rt_uint32_t)CANx)
+ {
+#if defined(BSP_USING_CAN1)
+ case (rt_uint32_t)CM_CAN1:
+ GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
+ GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
+ break;
+#endif
+#if defined(BSP_USING_CAN2)
+ case (rt_uint32_t)CM_CAN2:
+ GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC);
+ GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC);
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+
+ return result;
+}
+#endif
+
+
+#if defined (RT_USING_SPI)
+rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
+{
+ rt_err_t result = RT_EOK;
+#if defined(BSP_USING_SPI1)
+ stc_gpio_init_t stcGpioInit;
+#endif
+
+ switch ((rt_uint32_t)CM_SPIx)
+ {
+#if defined(BSP_USING_SPI1)
+ case (rt_uint32_t)CM_SPI1:
+ GPIO_StructInit(&stcGpioInit);
+ stcGpioInit.u16PinState = PIN_STAT_SET;
+ stcGpioInit.u16PinDir = PIN_DIR_OUT;
+ GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
+ GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
+
+ (void)GPIO_StructInit(&stcGpioInit);
+ stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+ stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
+ (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
+ (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
+ (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
+ GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
+ GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
+ GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+
+ return result;
+}
+#endif
+
+#if defined(RT_USING_PWM)
+#if defined(BSP_USING_PWM_TMRA)
+rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
+{
+ rt_err_t result = RT_EOK;
+ switch ((rt_uint32_t)TMRAx)
+ {
+#if defined(BSP_USING_PWM_TMRA_1)
+ case (rt_uint32_t)CM_TMRA_1:
+#ifdef BSP_USING_PWM_TMRA_1_CH1
+ GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH2
+ GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH3
+ GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH4
+ GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
+#endif
+ break;
+#endif
+#if defined(BSP_USING_PWM_TMRA_2)
+ case (rt_uint32_t)CM_TMRA_2:
+#ifdef BSP_USING_PWM_TMRA_2_CH1
+ GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH2
+ GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH3
+ GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH4
+ GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC);
+#endif
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+
+ return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR4)
+rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
+{
+ rt_err_t result = RT_EOK;
+ switch ((rt_uint32_t)TMR4x)
+ {
+#if defined(BSP_USING_PWM_TMR4_1)
+ case (rt_uint32_t)CM_TMR4_1:
+#ifdef BSP_USING_PWM_TMR4_1_OUH
+ GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OUL
+ GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVH
+ GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVL
+ GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWH
+ GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWL
+ GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC);
+#endif
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+ return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR6)
+rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
+{
+ rt_err_t result = RT_EOK;
+ switch ((rt_uint32_t)TMR6x)
+ {
+#if defined(BSP_USING_PWM_TMR6_1)
+ case (rt_uint32_t)CM_TMR6_1:
+#ifdef BSP_USING_PWM_TMR6_1_A
+ GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR6_1_B
+ GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC);
+#endif
+ break;
+#endif
+ default:
+ result = -RT_ERROR;
+ break;
+ }
+
+ return result;
+}
+#endif
+#endif
+
+#ifdef RT_USING_PM
+#define EFM_ERASE_TIME_MAX_IN_MILLISECOND (20)
+#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
+
+static void _pm_sleep_common_init(rt_bool_t b_disable_unused_clk)
+{
+ CLK_Xtal32Cmd(ENABLE);
+
+ rt_tick_t tick_start = rt_tick_get_millisecond();
+ rt_err_t rt_stat = RT_EOK;
+ //wait flash idle
+ while (SET != EFM_GetStatus(EFM_FLAG_RDY))
+ {
+ if (rt_tick_get_millisecond() - tick_start > EFM_ERASE_TIME_MAX_IN_MILLISECOND)
+ {
+ rt_stat = RT_ERROR;
+ break;
+ }
+ }
+ RT_ASSERT(rt_stat == RT_EOK);
+
+ if (b_disable_unused_clk)
+ {
+ uint32_t cur_clk_src = READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW);
+
+ switch (cur_clk_src)
+ {
+ case CLK_SYSCLK_SRC_HRC:
+ CLK_PLLCmd(DISABLE);
+ CLK_MrcCmd(DISABLE);
+ CLK_LrcCmd(DISABLE);
+ CLK_XtalCmd(DISABLE);
+ PWC_LDO_Cmd(PWC_LDO_PLL, DISABLE);
+ break;
+ case CLK_SYSCLK_SRC_MRC:
+ CLK_PLLCmd(DISABLE);
+ CLK_HrcCmd(DISABLE);
+ CLK_LrcCmd(DISABLE);
+ CLK_XtalCmd(DISABLE);
+ PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+ break;
+ case CLK_SYSCLK_SRC_XTAL:
+ CLK_PLLCmd(DISABLE);
+ CLK_HrcCmd(DISABLE);
+ CLK_MrcCmd(DISABLE);
+ CLK_LrcCmd(DISABLE);
+ PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+ break;
+ case CLK_SYSCLK_SRC_XTAL32:
+ CLK_PLLCmd(DISABLE);
+ CLK_HrcCmd(DISABLE);
+ CLK_MrcCmd(DISABLE);
+ CLK_LrcCmd(DISABLE);
+ CLK_XtalCmd(DISABLE);
+ PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+ break;
+ case CLK_SYSCLK_SRC_PLL:
+ if (CLK_PLL_SRC_XTAL == PLL_SRC)
+ {
+ CLK_HrcCmd(DISABLE);
+ }
+ else
+ {
+ CLK_XtalCmd(DISABLE);
+ }
+ CLK_MrcCmd(DISABLE);
+ CLK_LrcCmd(DISABLE);
+ PWC_LDO_Cmd(PWC_LDO_HRC, DISABLE);
+
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+void rt_hw_board_pm_sleep_deep_init(void)
+{
+#if (PM_SLEEP_DEEP_CFG_CLK == PWC_STOP_CLK_KEEP)
+ _pm_sleep_common_init(RT_TRUE);
+#else
+ _pm_sleep_common_init(RT_FALSE);
+ CLK_PLLCmd(DISABLE);
+ CLK_HrcCmd(DISABLE);
+ CLK_LrcCmd(DISABLE);
+ CLK_XtalCmd(DISABLE);
+ PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+#endif
+}
+
+void rt_hw_board_pm_sleep_shutdown_init(void)
+{
+ _pm_sleep_common_init(RT_TRUE);
+}
+
+void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
+{
+ switch (run_mode)
+ {
+ case PM_RUN_MODE_HIGH_SPEED:
+ case PM_RUN_MODE_NORMAL_SPEED:
+ SystemClock_Config();
+ break;
+
+ case PM_RUN_MODE_LOW_SPEED:
+ CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
+
+ default:
+ break;
+ }
+}
+#endif
+
+#if defined(BSP_USING_QSPI)
+rt_err_t rt_hw_qspi_board_init(void)
+{
+ stc_gpio_init_t stcGpioInit;
+
+ (void)GPIO_StructInit(&stcGpioInit);
+ stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+#ifndef BSP_QSPI_USING_SOFT_CS
+ (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit);
+ GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC);
+#endif
+ (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
+ (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);
+ (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit);
+ (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit);
+ (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit);
+ GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC);
+ GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC);
+ GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC);
+ GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC);
+ GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC);
+
+ return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMRA_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmra_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+ GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC);
+ GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC);
+#endif
+ return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMR6_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+ GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC);
+ GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC);
+#endif
+ return RT_EOK;
+}
+#endif
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h
new file mode 100644
index 0000000000..aed469db44
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+
+#ifndef __BOARD_CONFIG_H__
+#define __BOARD_CONFIG_H__
+
+#include
+#include "hc32_ll.h"
+#include "drv_config.h"
+
+
+/************************* XTAL port **********************/
+#define XTAL_PORT (GPIO_PORT_F)
+#define XTAL_IN_PIN (GPIO_PIN_00)
+#define XTAL_OUT_PIN (GPIO_PIN_01)
+
+/************************ USART port **********************/
+#if defined(BSP_USING_UART1)
+ #define USART1_RX_PORT (GPIO_PORT_E)
+ #define USART1_RX_PIN (GPIO_PIN_03)
+ #define USART1_RX_FUNC (GPIO_FUNC_33)
+
+ #define USART1_TX_PORT (GPIO_PORT_E)
+ #define USART1_TX_PIN (GPIO_PIN_04)
+ #define USART1_TX_FUNC (GPIO_FUNC_32)
+#endif
+
+#if defined(BSP_USING_UART2)
+ #define USART2_RX_PORT (GPIO_PORT_F)
+ #define USART2_RX_PIN (GPIO_PIN_02)
+ #define USART2_RX_FUNC (GPIO_FUNC_35)
+
+ #define USART2_TX_PORT (GPIO_PORT_C)
+ #define USART2_TX_PIN (GPIO_PIN_13)
+ #define USART2_TX_FUNC (GPIO_FUNC_34)
+#endif
+
+#if defined(BSP_USING_UART5)
+ #define USART5_RX_PORT (GPIO_PORT_E)
+ #define USART5_RX_PIN (GPIO_PIN_05)
+ #define USART5_RX_FUNC (GPIO_FUNC_41)
+
+ #define USART5_TX_PORT (GPIO_PORT_E)
+ #define USART5_TX_PIN (GPIO_PIN_06)
+ #define USART5_TX_FUNC (GPIO_FUNC_40)
+#endif
+
+/************************ I2C port **********************/
+#if defined(BSP_USING_I2C1)
+ #define I2C1_SDA_PORT (GPIO_PORT_B)
+ #define I2C1_SDA_PIN (GPIO_PIN_09)
+ #define I2C1_SDA_FUNC (GPIO_FUNC_54)
+
+ #define I2C1_SCL_PORT (GPIO_PORT_B)
+ #define I2C1_SCL_PIN (GPIO_PIN_06)
+ #define I2C1_SCL_FUNC (GPIO_FUNC_55)
+#endif
+ // TODO, ch2/3 for test only
+#if defined(BSP_USING_I2C2)
+ #define I2C2_SDA_PORT (GPIO_PORT_A)
+ #define I2C2_SDA_PIN (GPIO_PIN_09)
+ #define I2C2_SDA_FUNC (GPIO_FUNC_56)
+
+ #define I2C2_SCL_PORT (GPIO_PORT_A)
+ #define I2C2_SCL_PIN (GPIO_PIN_10)
+ #define I2C2_SCL_FUNC (GPIO_FUNC_57)
+#endif
+
+#if defined(BSP_USING_I2C3)
+ #define I2C3_SDA_PORT (GPIO_PORT_A)
+ #define I2C3_SDA_PIN (GPIO_PIN_09)
+ #define I2C3_SDA_FUNC (GPIO_FUNC_58)
+
+ #define I2C3_SCL_PORT (GPIO_PORT_A)
+ #define I2C3_SCL_PIN (GPIO_PIN_10)
+ #define I2C3_SCL_FUNC (GPIO_FUNC_59)
+#endif
+
+/*********** ADC configure *********/
+#if defined(BSP_USING_ADC1)
+ #define ADC1_CH_PORT (GPIO_PORT_A)
+ #define ADC1_CH_PIN (GPIO_PIN_06)
+#endif
+
+#if defined(BSP_USING_ADC2)
+ #define ADC2_CH_PORT (GPIO_PORT_C)
+ #define ADC2_CH_PIN (GPIO_PIN_04)
+#endif
+
+#if defined(BSP_USING_ADC3)
+ #define ADC3_CH_PORT (GPIO_PORT_C)
+ #define ADC3_CH_PIN (GPIO_PIN_01)
+#endif
+
+/*********** DAC configure *********/
+#if defined(BSP_USING_DAC1)
+ #define DAC1_CH1_PORT (GPIO_PORT_A)
+ #define DAC1_CH1_PIN (GPIO_PIN_04)
+ #define DAC1_CH2_PORT (GPIO_PORT_A)
+ #define DAC1_CH2_PIN (GPIO_PIN_05)
+#endif
+
+/*********** CAN configure *********/
+#if defined(BSP_USING_CAN1)
+ #define CAN1_TX_PORT (GPIO_PORT_D)
+ #define CAN1_TX_PIN (GPIO_PIN_12)
+ #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60)
+
+ #define CAN1_RX_PORT (GPIO_PORT_D)
+ #define CAN1_RX_PIN (GPIO_PIN_13)
+ #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61)
+#endif
+
+#if defined(BSP_USING_CAN2)
+ #define CAN2_TX_PORT (GPIO_PORT_C)
+ #define CAN2_TX_PIN (GPIO_PIN_07)
+ #define CAN2_TX_PIN_FUNC (GPIO_FUNC_60)
+
+ #define CAN2_RX_PORT (GPIO_PORT_D)
+ #define CAN2_RX_PIN (GPIO_PIN_11)
+ #define CAN2_RX_PIN_FUNC (GPIO_FUNC_61)
+#endif
+
+#if defined(BSP_USING_CAN3)
+ #define CAN3_TX_PORT (GPIO_PORT_C)
+ #define CAN3_TX_PIN (GPIO_PIN_06)
+ #define CAN3_TX_PIN_FUNC (GPIO_FUNC_62)
+
+ #define CAN3_RX_PORT (GPIO_PORT_A)
+ #define CAN3_RX_PIN (GPIO_PIN_05)
+ #define CAN3_RX_PIN_FUNC (GPIO_FUNC_63)
+#endif
+
+/************************* SPI port ***********************/
+#if defined(BSP_USING_SPI1)
+ #define SPI1_CS_PORT (GPIO_PORT_B)
+ #define SPI1_CS_PIN (GPIO_PIN_12)
+
+ #define SPI1_SCK_PORT (GPIO_PORT_B)
+ #define SPI1_SCK_PIN (GPIO_PIN_13)
+ #define SPI1_SCK_FUNC (GPIO_FUNC_6)
+
+ #define SPI1_MOSI_PORT (GPIO_PORT_A)
+ #define SPI1_MOSI_PIN (GPIO_PIN_07)
+ #define SPI1_MOSI_FUNC (GPIO_FUNC_6)
+
+ #define SPI1_MISO_PORT (GPIO_PORT_B)
+ #define SPI1_MISO_PIN (GPIO_PIN_14)
+ #define SPI1_MISO_FUNC (GPIO_FUNC_6)
+
+ #define SPI1_WP_PORT (GPIO_PORT_B)
+ #define SPI1_WP_PIN (GPIO_PIN_10)
+
+ #define SPI1_HOLD_PORT (GPIO_PORT_B)
+ #define SPI1_HOLD_PIN (GPIO_PIN_11)
+#endif
+
+/************************ RTC/PM *****************************/
+#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
+ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+ #define XTAL32_PORT (GPIO_PORT_C)
+ #define XTAL32_IN_PIN (GPIO_PIN_14)
+ #define XTAL32_OUT_PIN (GPIO_PIN_15)
+ #endif
+#endif
+
+#if defined(RT_USING_PWM)
+ /*********** PWM_TMRA configure *********/
+ #if defined(BSP_USING_PWM_TMRA_1)
+ #if defined(BSP_USING_PWM_TMRA_1_CH1)
+ #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
+ #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
+ #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
+ #endif
+ #if defined(BSP_USING_PWM_TMRA_1_CH2)
+ #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
+ #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
+ #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
+ #endif
+ #if defined(BSP_USING_PWM_TMRA_1_CH3)
+ #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
+ #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
+ #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
+ #endif
+ #if defined(BSP_USING_PWM_TMRA_1_CH4)
+ #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
+ #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
+ #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
+ #endif
+ #endif
+
+ #if defined(BSP_USING_PWM_TMRA_2)
+ #if defined(BSP_USING_PWM_TMRA_2_CH1)
+ #define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A)
+ #define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00)
+ #define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4)
+ #endif
+ #if defined(BSP_USING_PWM_TMRA_2_CH2)
+ #define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A)
+ #define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01)
+ #define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4)
+ #endif
+ #if defined(BSP_USING_PWM_TMRA_2_CH3)
+ #define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A)
+ #define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02)
+ #define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4)
+ #endif
+ #if defined(BSP_USING_PWM_TMRA_2_CH4)
+ #define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A)
+ #define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03)
+ #define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4)
+ #endif
+ #endif
+
+ /*********** PWM_TMR4 configure *********/
+ #if defined(BSP_USING_PWM_TMR4_1)
+ #if defined(BSP_USING_PWM_TMR4_1_OUH)
+ #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A)
+ #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08)
+ #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2)
+ #endif
+ #if defined(BSP_USING_PWM_TMR4_1_OUL)
+ #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A)
+ #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07)
+ #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2)
+ #endif
+ #if defined(BSP_USING_PWM_TMR4_1_OVH)
+ #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A)
+ #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09)
+ #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2)
+ #endif
+ #if defined(BSP_USING_PWM_TMR4_1_OVL)
+ #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B)
+ #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00)
+ #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2)
+ #endif
+ #if defined(BSP_USING_PWM_TMR4_1_OWH)
+ #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A)
+ #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10)
+ #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2)
+ #endif
+ #if defined(BSP_USING_PWM_TMR4_1_OWL)
+ #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B)
+ #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01)
+ #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2)
+ #endif
+ #endif
+
+ /*********** PWM_TMR6 configure *********/
+ #if defined(BSP_USING_PWM_TMR6_1)
+ #if defined(BSP_USING_PWM_TMR6_1_A)
+ #define PWM_TMR6_1_A_PORT (GPIO_PORT_A)
+ #define PWM_TMR6_1_A_PIN (GPIO_PIN_08)
+ #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
+ #endif
+ #if defined(BSP_USING_PWM_TMR6_1_B)
+ #define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
+ #define PWM_TMR6_1_B_PIN (GPIO_PIN_07)
+ #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
+ #endif
+ #endif
+
+#endif
+
+#if defined(BSP_USING_QSPI)
+ #ifndef BSP_QSPI_USING_SOFT_CS
+ /* QSSN */
+ #define QSPI_FLASH_CS_PORT (GPIO_PORT_B)
+ #define QSPI_FLASH_CS_PIN (GPIO_PIN_12)
+ #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_5)
+ #endif
+ /* QSCK */
+ #define QSPI_FLASH_SCK_PORT (GPIO_PORT_B)
+ #define QSPI_FLASH_SCK_PIN (GPIO_PIN_13)
+ #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_5)
+ /* QSIO0 */
+ #define QSPI_FLASH_IO0_PORT (GPIO_PORT_A)
+ #define QSPI_FLASH_IO0_PIN (GPIO_PIN_07)
+ #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_5)
+ /* QSIO1 */
+ #define QSPI_FLASH_IO1_PORT (GPIO_PORT_B)
+ #define QSPI_FLASH_IO1_PIN (GPIO_PIN_14)
+ #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_5)
+ /* QSIO2 */
+ #define QSPI_FLASH_IO2_PORT (GPIO_PORT_B)
+ #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10)
+ #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_4)
+ /* QSIO3 */
+ #define QSPI_FLASH_IO3_PORT (GPIO_PORT_B)
+ #define QSPI_FLASH_IO3_PIN (GPIO_PIN_11)
+ #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_4)
+#endif
+
+/*********** TMRA_PULSE_ENCODER configure *********/
+#if defined(RT_USING_PULSE_ENCODER)
+ #if defined(BSP_USING_TMRA_PULSE_ENCODER)
+ #if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+ #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
+ #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
+ #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
+ #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
+ #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
+ #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
+ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+ #endif /* BSP_USING_TMRA_PULSE_ENCODER */
+
+ #if defined(BSP_USING_TMR6_PULSE_ENCODER)
+ #if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+ #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_A)
+ #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_08)
+ #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
+ #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_A)
+ #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_07)
+ #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
+ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+ #endif /* BSP_USING_TMR6_PULSE_ENCODER */
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif
+
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h
new file mode 100644
index 0000000000..7fdc0d3e0f
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_INIT_PARAMS
+#define ADC1_INIT_PARAMS \
+ { \
+ .name = "adc1", \
+ .vref = 3300, \
+ .resolution = ADC_RESOLUTION_12BIT, \
+ .data_align = ADC_DATAALIGN_RIGHT, \
+ .eoc_poll_time_max = 100, \
+ .hard_trig_enable = RT_FALSE, \
+ .hard_trig_src = ADC_HARDTRIG_EVT0, \
+ .internal_trig0_comtrg0_enable = RT_FALSE, \
+ .internal_trig0_comtrg1_enable = RT_FALSE, \
+ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
+ .internal_trig1_comtrg0_enable = RT_FALSE, \
+ .internal_trig1_comtrg1_enable = RT_FALSE, \
+ .internal_trig1_sel = EVT_SRC_MAX, \
+ .continue_conv_mode_enable = RT_FALSE, \
+ .data_reg_auto_clear = RT_TRUE, \
+ }
+#endif /* ADC1_INIT_PARAMS */
+
+#if defined (BSP_ADC1_USING_DMA)
+#ifndef ADC1_EOCA_DMA_CONFIG
+#define ADC1_EOCA_DMA_CONFIG \
+ { \
+ .Instance = ADC1_EOCA_DMA_INSTANCE, \
+ .channel = ADC1_EOCA_DMA_CHANNEL, \
+ .clock = ADC1_EOCA_DMA_CLOCK, \
+ .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_ADC1_EOCA, \
+ .flag = ADC1_EOCA_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = ADC1_EOCA_DMA_IRQn, \
+ .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
+ .int_src = ADC1_EOCA_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* ADC1_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC1_USING_DMA */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_INIT_PARAMS
+#define ADC2_INIT_PARAMS \
+ { \
+ .name = "adc2", \
+ .vref = 3300, \
+ .resolution = ADC_RESOLUTION_12BIT, \
+ .data_align = ADC_DATAALIGN_RIGHT, \
+ .eoc_poll_time_max = 100, \
+ .hard_trig_enable = RT_FALSE, \
+ .hard_trig_src = ADC_HARDTRIG_EVT0, \
+ .internal_trig0_comtrg0_enable = RT_FALSE, \
+ .internal_trig0_comtrg1_enable = RT_FALSE, \
+ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
+ .internal_trig1_comtrg0_enable = RT_FALSE, \
+ .internal_trig1_comtrg1_enable = RT_FALSE, \
+ .internal_trig1_sel = EVT_SRC_MAX, \
+ .continue_conv_mode_enable = RT_FALSE, \
+ .data_reg_auto_clear = RT_TRUE, \
+ }
+#endif /* ADC2_INIT_PARAMS */
+
+#if defined (BSP_ADC2_USING_DMA)
+#ifndef ADC2_EOCA_DMA_CONFIG
+#define ADC2_EOCA_DMA_CONFIG \
+ { \
+ .Instance = ADC2_EOCA_DMA_INSTANCE, \
+ .channel = ADC2_EOCA_DMA_CHANNEL, \
+ .clock = ADC2_EOCA_DMA_CLOCK, \
+ .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_ADC2_EOCA, \
+ .flag = ADC2_EOCA_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = ADC2_EOCA_DMA_IRQn, \
+ .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
+ .int_src = ADC2_EOCA_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* ADC2_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC2_USING_DMA */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_INIT_PARAMS
+#define ADC3_INIT_PARAMS \
+ { \
+ .name = "adc3", \
+ .vref = 3300, \
+ .resolution = ADC_RESOLUTION_12BIT, \
+ .data_align = ADC_DATAALIGN_RIGHT, \
+ .eoc_poll_time_max = 100, \
+ .hard_trig_enable = RT_FALSE, \
+ .hard_trig_src = ADC_HARDTRIG_EVT0, \
+ .internal_trig0_comtrg0_enable = RT_FALSE, \
+ .internal_trig0_comtrg1_enable = RT_FALSE, \
+ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
+ .internal_trig1_comtrg0_enable = RT_FALSE, \
+ .internal_trig1_comtrg1_enable = RT_FALSE, \
+ .internal_trig1_sel = EVT_SRC_MAX, \
+ .continue_conv_mode_enable = RT_FALSE, \
+ .data_reg_auto_clear = RT_TRUE, \
+ }
+#endif /* ADC3_INIT_PARAMS */
+
+#if defined (BSP_ADC3_USING_DMA)
+#ifndef ADC3_EOCA_DMA_CONFIG
+#define ADC3_EOCA_DMA_CONFIG \
+ { \
+ .Instance = ADC3_EOCA_DMA_INSTANCE, \
+ .channel = ADC3_EOCA_DMA_CHANNEL, \
+ .clock = ADC3_EOCA_DMA_CLOCK, \
+ .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_ADC3_EOCA, \
+ .flag = ADC3_EOCA_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = ADC3_EOCA_DMA_IRQn, \
+ .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
+ .int_src = ADC3_EOCA_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* ADC3_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC3_USING_DMA */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h
new file mode 100644
index 0000000000..eb25e85687
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_CAN1
+#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
+#endif
+#define CAN1_NAME ("can1")
+#ifndef CAN1_INIT_PARAMS
+#define CAN1_INIT_PARAMS \
+ { \
+ .name = CAN1_NAME, \
+ .single_trans_mode = RT_FALSE \
+ }
+#endif /* CAN1_INIT_PARAMS */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN2_CANFD_MODE (CAN_FD_MD_ISO)
+#endif
+#define CAN2_NAME ("can2")
+#ifndef CAN2_INIT_PARAMS
+#define CAN2_INIT_PARAMS \
+ { \
+ .name = CAN2_NAME, \
+ .single_trans_mode = RT_FALSE \
+ }
+#endif /* CAN2_INIT_PARAMS */
+#endif /* BSP_USING_CAN2 */
+
+/* Bit time config
+ Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
+
+ Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
+ TQ = u32Prescaler / CANClock.
+ Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
+
+ The following bit time configures are based on CAN Clock 40M
+*/
+#define CAN_BIT_TIME_CONFIG_1M_BAUD \
+ { \
+ .u32Prescaler = 2, \
+ .u32TimeSeg1 = 16, \
+ .u32TimeSeg2 = 4, \
+ .u32SJW = 4 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_800K_BAUD \
+ { \
+ .u32Prescaler = 2, \
+ .u32TimeSeg1 = 20, \
+ .u32TimeSeg2 = 5, \
+ .u32SJW = 4 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_500K_BAUD \
+ { \
+ .u32Prescaler = 4, \
+ .u32TimeSeg1 = 16, \
+ .u32TimeSeg2 = 4, \
+ .u32SJW = 4 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_250K_BAUD \
+ { \
+ .u32Prescaler = 8, \
+ .u32TimeSeg1 = 16, \
+ .u32TimeSeg2 = 4, \
+ .u32SJW = 4 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_125K_BAUD \
+ { \
+ .u32Prescaler = 16, \
+ .u32TimeSeg1 = 16, \
+ .u32TimeSeg2 = 4, \
+ .u32SJW = 4 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_100K_BAUD \
+ { \
+ .u32Prescaler = 20, \
+ .u32TimeSeg1 = 16, \
+ .u32TimeSeg2 = 4, \
+ .u32SJW = 4 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_50K_BAUD \
+ { \
+ .u32Prescaler = 40, \
+ .u32TimeSeg1 = 16, \
+ .u32TimeSeg2 = 4, \
+ .u32SJW = 4 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_20K_BAUD \
+ { \
+ .u32Prescaler = 100, \
+ .u32TimeSeg1 = 16, \
+ .u32TimeSeg2 = 4, \
+ .u32SJW = 4 \
+ }
+
+#define CAN_BIT_TIME_CONFIG_10K_BAUD \
+ { \
+ .u32Prescaler = 200, \
+ .u32TimeSeg1 = 16, \
+ .u32TimeSeg2 = 4, \
+ .u32SJW = 4 \
+ }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAN_CONFIG_H__ */
+
+
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h
new file mode 100644
index 0000000000..10de0c1734
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_INIT_PARAMS
+#define DAC1_INIT_PARAMS \
+ { \
+ .name = "dac1", \
+ }
+#endif /* DAC1_INIT_PARAMS */
+#endif /* BSP_USING_DAC1 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_INIT_PARAMS
+#define DAC2_INIT_PARAMS \
+ { \
+ .name = "dac2", \
+ }
+#endif /* DAC2_INIT_PARAMS */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h
new file mode 100644
index 0000000000..b5202f3eb9
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 ch0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_RX_DMA_INSTANCE CM_DMA1
+#define SPI1_RX_DMA_CHANNEL DMA_CH0
+#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
+#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
+#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
+#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
+#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
+
+#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_RX_DMA_INSTANCE CM_DMA1
+#define SPI3_RX_DMA_CHANNEL DMA_CH0
+#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0
+#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
+#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
+#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
+#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
+
+#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
+#define I2C1_TX_DMA_INSTANCE CM_DMA1
+#define I2C1_TX_DMA_CHANNEL DMA_CH0
+#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
+#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
+#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
+#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
+#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
+#endif
+
+/* DMA1 ch1 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_TX_DMA_INSTANCE CM_DMA1
+#define SPI1_TX_DMA_CHANNEL DMA_CH1
+#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
+#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
+#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
+#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
+#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
+
+#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_TX_DMA_INSTANCE CM_DMA1
+#define SPI3_TX_DMA_CHANNEL DMA_CH1
+#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1
+#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
+#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
+#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
+#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
+
+#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
+#define I2C1_RX_DMA_INSTANCE CM_DMA1
+#define I2C1_RX_DMA_CHANNEL DMA_CH1
+#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
+#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
+#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
+#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
+#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
+#endif
+
+/* DMA1 ch2 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_RX_DMA_INSTANCE CM_DMA1
+#define SPI2_RX_DMA_CHANNEL DMA_CH2
+#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
+#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
+#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
+#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
+#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
+
+#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
+#define I2C2_TX_DMA_INSTANCE CM_DMA1
+#define I2C2_TX_DMA_CHANNEL DMA_CH2
+#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
+#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
+#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
+#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
+#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
+#endif
+
+/* DMA1 ch3 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_TX_DMA_INSTANCE CM_DMA1
+#define SPI2_TX_DMA_CHANNEL DMA_CH3
+#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
+#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
+#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
+#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
+#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
+
+
+#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
+#define I2C2_RX_DMA_INSTANCE CM_DMA1
+#define I2C2_RX_DMA_CHANNEL DMA_CH3
+#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
+#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
+#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
+#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
+#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
+
+#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
+#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
+#define ADC1_EOCA_DMA_CHANNEL DMA_CH3
+#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3
+#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
+#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
+#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
+#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3
+
+#endif
+
+/* DMA1 ch4 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_RX_DMA_INSTANCE CM_DMA1
+#define UART5_RX_DMA_CHANNEL DMA_CH4
+#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4
+#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
+#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
+#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
+#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
+
+#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
+#define ADC2_EOCA_DMA_INSTANCE CM_DMA1
+#define ADC2_EOCA_DMA_CHANNEL DMA_CH4
+#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4
+#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
+#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
+#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
+#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4
+#endif
+
+/* DMA1 ch5 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_TX_DMA_INSTANCE CM_DMA1
+#define UART5_TX_DMA_CHANNEL DMA_CH5
+#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5
+#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
+#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
+#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
+#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
+
+#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
+#define ADC3_EOCA_DMA_INSTANCE CM_DMA1
+#define ADC3_EOCA_DMA_CHANNEL DMA_CH5
+#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5
+#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
+#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
+#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
+#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5
+#endif
+
+/* DMA2 ch0 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_RX_DMA_INSTANCE CM_DMA2
+#define UART1_RX_DMA_CHANNEL DMA_CH0
+#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
+#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
+#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
+#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
+#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
+
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_INSTANCE CM_DMA2
+#define QSPI_DMA_CHANNEL DMA_CH0
+#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0
+#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
+#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
+#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
+#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0
+#endif
+
+/* DMA2 ch1 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_TX_DMA_INSTANCE CM_DMA2
+#define UART1_TX_DMA_CHANNEL DMA_CH1
+#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
+#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
+#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
+#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
+#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
+#endif
+
+/* DMA2 ch2 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_RX_DMA_INSTANCE CM_DMA2
+#define UART2_RX_DMA_CHANNEL DMA_CH2
+#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
+#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
+#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
+#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
+#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
+#endif
+
+/* DMA2 ch3 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_TX_DMA_INSTANCE CM_DMA2
+#define UART2_TX_DMA_CHANNEL DMA_CH3
+#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
+#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
+#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
+#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
+#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
+#endif
+
+/* DMA2 ch4 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_RX_DMA_INSTANCE CM_DMA2
+#define UART4_RX_DMA_CHANNEL DMA_CH4
+#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4
+#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
+#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
+#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
+#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
+#endif
+
+/* DMA2 ch5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_TX_DMA_INSTANCE CM_DMA2
+#define UART4_TX_DMA_CHANNEL DMA_CH5
+#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5
+#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
+#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
+#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
+#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h
new file mode 100644
index 0000000000..a0bbb41e1a
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __GPIO_CONFIG_H__
+#define __GPIO_CONFIG_H__
+
+#include
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(RT_USING_PIN)
+
+#ifndef EXTINT0_IRQ_CONFIG
+#define EXTINT0_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT0_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT0_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ0, \
+ }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT1_IRQ_CONFIG
+#define EXTINT1_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT1_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT1_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ1, \
+ }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT2_IRQ_CONFIG
+#define EXTINT2_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT2_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT2_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ2, \
+ }
+#endif /* EXTINT2_IRQ_CONFIG */
+
+#ifndef EXTINT3_IRQ_CONFIG
+#define EXTINT3_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT3_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT3_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ3, \
+ }
+#endif /* EXTINT3_IRQ_CONFIG */
+
+#ifndef EXTINT4_IRQ_CONFIG
+#define EXTINT4_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT4_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT4_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ4, \
+ }
+#endif /* EXTINT4_IRQ_CONFIG */
+
+#ifndef EXTINT5_IRQ_CONFIG
+#define EXTINT5_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT5_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT5_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ5, \
+ }
+#endif /* EXTINT5_IRQ_CONFIG */
+
+#ifndef EXTINT6_IRQ_CONFIG
+#define EXTINT6_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT6_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT6_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ6, \
+ }
+#endif /* EXTINT6_IRQ_CONFIG */
+
+#ifndef EXTINT7_IRQ_CONFIG
+#define EXTINT7_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT7_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT7_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ7, \
+ }
+#endif /* EXTINT7_IRQ_CONFIG */
+
+#ifndef EXTINT8_IRQ_CONFIG
+#define EXTINT8_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT8_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT8_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ8, \
+ }
+#endif /* EXTINT8_IRQ_CONFIG */
+
+#ifndef EXTINT9_IRQ_CONFIG
+#define EXTINT9_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT9_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT9_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ9, \
+ }
+#endif /* EXTINT9_IRQ_CONFIG */
+
+#ifndef EXTINT10_IRQ_CONFIG
+#define EXTINT10_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT10_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT10_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ10, \
+ }
+#endif /* EXTINT10_IRQ_CONFIG */
+
+#ifndef EXTINT11_IRQ_CONFIG
+#define EXTINT11_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT11_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT11_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ11, \
+ }
+#endif /* EXTINT11_IRQ_CONFIG */
+
+#ifndef EXTINT12_IRQ_CONFIG
+#define EXTINT12_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT12_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT12_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ12, \
+ }
+#endif /* EXTINT12_IRQ_CONFIG */
+
+#ifndef EXTINT13_IRQ_CONFIG
+#define EXTINT13_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT13_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT13_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ13, \
+ }
+#endif /* EXTINT13_IRQ_CONFIG */
+
+#ifndef EXTINT14_IRQ_CONFIG
+#define EXTINT14_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT14_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT14_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ14, \
+ }
+#endif /* EXTINT14_IRQ_CONFIG */
+
+#ifndef EXTINT15_IRQ_CONFIG
+#define EXTINT15_IRQ_CONFIG \
+ { \
+ .irq_num = BSP_EXTINT15_IRQ_NUM, \
+ .irq_prio = BSP_EXTINT15_IRQ_PRIO, \
+ .int_src = INT_SRC_PORT_EIRQ15, \
+ }
+#endif /* EXTINT15_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h
new file mode 100644
index 0000000000..8f7c6b6296
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __I2C_CONFIG_H__
+#define __I2C_CONFIG_H__
+
+#include
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_I2C1)
+#ifndef I2C1_CONFIG
+#define I2C1_CONFIG \
+ { \
+ .name = "i2c1", \
+ .Instance = CM_I2C1, \
+ .clock = FCG1_PERIPH_I2C1, \
+ .baudrate = 100000UL, \
+ .timeout = 10000UL, \
+ }
+#endif /* I2C1_CONFIG */
+#endif
+
+#if defined(BSP_I2C1_USING_DMA)
+#ifndef I2C1_TX_DMA_CONFIG
+#define I2C1_TX_DMA_CONFIG \
+ { \
+ .Instance = I2C1_TX_DMA_INSTANCE, \
+ .channel = I2C1_TX_DMA_CHANNEL, \
+ .clock = I2C1_TX_DMA_CLOCK, \
+ .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C1_TEI, \
+ .flag = I2C1_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C1_TX_DMA_IRQn, \
+ .irq_prio = I2C1_TX_DMA_INT_PRIO, \
+ .int_src = I2C1_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C1_TX_DMA_CONFIG */
+
+#ifndef I2C1_RX_DMA_CONFIG
+#define I2C1_RX_DMA_CONFIG \
+ { \
+ .Instance = I2C1_RX_DMA_INSTANCE, \
+ .channel = I2C1_RX_DMA_CHANNEL, \
+ .clock = I2C1_RX_DMA_CLOCK, \
+ .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C1_RXI, \
+ .flag = I2C1_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C1_RX_DMA_IRQn, \
+ .irq_prio = I2C1_RX_DMA_INT_PRIO, \
+ .int_src = I2C1_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C1_RX_DMA_CONFIG */
+#endif /* BSP_I2C1_USING_DMA */
+
+#if defined(BSP_USING_I2C2)
+#ifndef I2C2_CONFIG
+#define I2C2_CONFIG \
+ { \
+ .name = "i2c2", \
+ .Instance = CM_I2C2, \
+ .clock = FCG1_PERIPH_I2C2, \
+ .baudrate = 100000UL, \
+ .timeout = 10000UL, \
+ }
+#endif /* I2C2_CONFIG */
+
+#if defined(BSP_I2C2_USING_DMA)
+#ifndef I2C2_TX_DMA_CONFIG
+#define I2C2_TX_DMA_CONFIG \
+ { \
+ .Instance = I2C2_TX_DMA_INSTANCE, \
+ .channel = I2C2_TX_DMA_CHANNEL, \
+ .clock = I2C2_TX_DMA_CLOCK, \
+ .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C2_TEI, \
+ .flag = I2C2_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C2_TX_DMA_IRQn, \
+ .irq_prio = I2C2_TX_DMA_INT_PRIO, \
+ .int_src = I2C2_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C2_TX_DMA_CONFIG */
+
+#ifndef I2C2_RX_DMA_CONFIG
+#define I2C2_RX_DMA_CONFIG \
+ { \
+ .Instance = I2C2_RX_DMA_INSTANCE, \
+ .channel = I2C2_RX_DMA_CHANNEL, \
+ .clock = I2C2_RX_DMA_CLOCK, \
+ .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C2_RXI, \
+ .flag = I2C2_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C2_RX_DMA_IRQn, \
+ .irq_prio = I2C2_RX_DMA_INT_PRIO, \
+ .int_src = I2C2_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C2_RX_DMA_CONFIG */
+#endif /* BSP_I2C2_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C3)
+#ifndef I2C3_CONFIG
+#define I2C3_CONFIG \
+ { \
+ .name = "i2c3", \
+ .Instance = CM_I2C3, \
+ .clock = FCG1_PERIPH_I2C3, \
+ .baudrate = 100000UL, \
+ .timeout = 10000UL, \
+ }
+#endif /* I2C3_CONFIG */
+
+#if defined(BSP_I2C3_USING_DMA)
+#ifndef I2C3_TX_DMA_CONFIG
+#define I2C3_TX_DMA_CONFIG \
+ { \
+ .Instance = I2C3_TX_DMA_INSTANCE, \
+ .channel = I2C3_TX_DMA_CHANNEL, \
+ .clock = I2C3_TX_DMA_CLOCK, \
+ .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C3_TEI, \
+ .flag = I2C3_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C3_TX_DMA_IRQn, \
+ .irq_prio = I2C3_TX_DMA_INT_PRIO, \
+ .int_src = I2C3_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C3_TX_DMA_CONFIG */
+
+#ifndef I2C3_RX_DMA_CONFIG
+#define I2C3_RX_DMA_CONFIG \
+ { \
+ .Instance = I2C3_RX_DMA_INSTANCE, \
+ .channel = I2C3_RX_DMA_CHANNEL, \
+ .clock = I2C3_RX_DMA_CLOCK, \
+ .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C3_RXI, \
+ .flag = I2C3_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C3_RX_DMA_IRQn, \
+ .irq_prio = I2C3_RX_DMA_INT_PRIO, \
+ .int_src = I2C3_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C3_RX_DMA_CONFIG */
+#endif /* BSP_I2C3_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C4)
+#ifndef I2C4_CONFIG
+#define I2C4_CONFIG \
+ { \
+ .name = "i2c4", \
+ .Instance = CM_I2C4, \
+ .clock = FCG1_PERIPH_I2C4, \
+ .baudrate = 100000UL, \
+ .timeout = 10000UL, \
+ }
+#endif /* I2C4_CONFIG */
+
+#if defined(BSP_I2C4_USING_DMA)
+#ifndef I2C4_TX_DMA_CONFIG
+#define I2C4_TX_DMA_CONFIG \
+ { \
+ .Instance = I2C4_TX_DMA_INSTANCE, \
+ .channel = I2C4_TX_DMA_CHANNEL, \
+ .clock = I2C4_TX_DMA_CLOCK, \
+ .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C4_TEI, \
+ .flag = I2C4_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C4_TX_DMA_IRQn, \
+ .irq_prio = I2C4_TX_DMA_INT_PRIO, \
+ .int_src = I2C4_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C4_TX_DMA_CONFIG */
+
+#ifndef I2C4_RX_DMA_CONFIG
+#define I2C4_RX_DMA_CONFIG \
+ { \
+ .Instance = I2C4_RX_DMA_INSTANCE, \
+ .channel = I2C4_RX_DMA_CHANNEL, \
+ .clock = I2C4_RX_DMA_CLOCK, \
+ .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C4_RXI, \
+ .flag = I2C4_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C4_RX_DMA_IRQn, \
+ .irq_prio = I2C4_RX_DMA_INT_PRIO, \
+ .int_src = I2C4_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C4_RX_DMA_CONFIG */
+#endif /* BSP_I2C4_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C5)
+#ifndef I2C5_CONFIG
+#define I2C5_CONFIG \
+ { \
+ .name = "i2c5", \
+ .Instance = CM_I2C5, \
+ .clock = FCG1_PERIPH_I2C5, \
+ .baudrate = 100000UL, \
+ .timeout = 10000UL, \
+ }
+#endif /* I2C5_CONFIG */
+
+#if defined(BSP_I2C5_USING_DMA)
+#ifndef I2C5_TX_DMA_CONFIG
+#define I2C5_TX_DMA_CONFIG \
+ { \
+ .Instance = I2C5_TX_DMA_INSTANCE, \
+ .channel = I2C5_TX_DMA_CHANNEL, \
+ .clock = I2C5_TX_DMA_CLOCK, \
+ .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C5_TEI, \
+ .flag = I2C5_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C5_TX_DMA_IRQn, \
+ .irq_prio = I2C5_TX_DMA_INT_PRIO, \
+ .int_src = I2C5_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C5_TX_DMA_CONFIG */
+
+#ifndef I2C5_RX_DMA_CONFIG
+#define I2C5_RX_DMA_CONFIG \
+ { \
+ .Instance = I2C5_RX_DMA_INSTANCE, \
+ .channel = I2C5_RX_DMA_CHANNEL, \
+ .clock = I2C5_RX_DMA_CLOCK, \
+ .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C5_RXI, \
+ .flag = I2C5_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C5_RX_DMA_IRQn, \
+ .irq_prio = I2C5_RX_DMA_INT_PRIO, \
+ .int_src = I2C5_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C5_RX_DMA_CONFIG */
+#endif /* BSP_I2C5_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C6)
+#ifndef I2C6_CONFIG
+#define I2C6_CONFIG \
+ { \
+ .name = "i2c6", \
+ .Instance = CM_I2C6, \
+ .clock = FCG1_PERIPH_I2C6, \
+ .baudrate = 100000UL, \
+ .timeout = 10000UL, \
+ }
+#endif /* I2C6_CONFIG */
+
+#if defined(BSP_I2C6_USING_DMA)
+#ifndef I2C6_TX_DMA_CONFIG
+#define I2C6_TX_DMA_CONFIG \
+ { \
+ .Instance = I2C6_TX_DMA_INSTANCE, \
+ .channel = I2C6_TX_DMA_CHANNEL, \
+ .clock = I2C6_TX_DMA_CLOCK, \
+ .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C6_TEI, \
+ .flag = I2C6_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C6_TX_DMA_IRQn, \
+ .irq_prio = I2C6_TX_DMA_INT_PRIO, \
+ .int_src = I2C6_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C6_TX_DMA_CONFIG */
+
+#ifndef I2C6_RX_DMA_CONFIG
+#define I2C6_RX_DMA_CONFIG \
+ { \
+ .Instance = I2C6_RX_DMA_INSTANCE, \
+ .channel = I2C6_RX_DMA_CHANNEL, \
+ .clock = I2C6_RX_DMA_CLOCK, \
+ .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_I2C6_RXI, \
+ .flag = I2C6_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = I2C6_RX_DMA_IRQn, \
+ .irq_prio = I2C6_RX_DMA_INT_PRIO, \
+ .int_src = I2C6_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* I2C6_RX_DMA_CONFIG */
+#endif /* BSP_I2C6_USING_DMA */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h
new file mode 100644
index 0000000000..352d0f195b
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __IRQ_CONFIG_H__
+#define __IRQ_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
+#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
+#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
+#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
+#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
+#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
+#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
+#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
+#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
+#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
+#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
+#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
+#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
+#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
+#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
+#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
+#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+
+/* DMA1 ch0 */
+#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
+#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch1 */
+#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
+#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch2 */
+#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
+#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch3 */
+#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
+#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch4 */
+#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
+#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch5 */
+#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
+#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+
+/* DMA2 ch0 */
+#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn
+#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch1 */
+#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn
+#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch2 */
+#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn
+#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch3 */
+#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn
+#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch4 */
+#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn
+#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch5 */
+#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn
+#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+
+#if defined(BSP_USING_UART1)
+#define BSP_UART1_IRQ_NUM USART1_IRQn
+#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
+ defined(RT_USING_SERIAL_V2)
+#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
+#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#define BSP_UART2_IRQ_NUM USART2_IRQn
+#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
+ defined(RT_USING_SERIAL_V2)
+#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
+#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#define BSP_UART3_IRQ_NUM USART3_IRQn
+#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#define BSP_UART4_IRQ_NUM USART4_IRQn
+#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
+ defined(RT_USING_SERIAL_V2)
+#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
+#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#define BSP_UART5_IRQ_NUM USART5_IRQn
+#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \
+ defined(RT_USING_SERIAL_V2)
+#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn
+#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#define BSP_UART6_IRQ_NUM USART6_IRQn
+#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_SPI1)
+#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn
+#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI2)
+#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn
+#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI3)
+#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn
+#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI4)
+#define BSP_SPI4_ERR_IRQ_NUM SPI4_IRQn
+#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined (BSP_USING_QSPI)
+#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
+#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_QSPI */
+
+#if defined(BSP_USING_TMRA_1)
+#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
+#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_1 */
+
+#if defined(BSP_USING_TMRA_2)
+#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
+#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_2 */
+
+#if defined(BSP_USING_TMRA_3)
+#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
+#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_3 */
+
+#if defined(BSP_USING_TMRA_4)
+#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
+#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_4 */
+
+#if defined(BSP_USING_TMRA_5)
+#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
+#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_5 */
+
+#if defined(BSP_USING_TMRA_6)
+#define BSP_USING_TMRA_6_IRQ_NUM TMRA_6_OVF_UDF_IRQn
+#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_6 */
+
+#if defined(BSP_USING_CAN1)
+#define BSP_CAN1_IRQ_NUM MCAN1_INT0_IRQn
+#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_CAN1 */
+
+#if defined(RT_USING_ALARM)
+#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
+#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
+#endif/* RT_USING_ALARM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h
new file mode 100644
index 0000000000..e77cc0f20e
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __PM_CONFIG_H__
+#define __PM_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PM
+extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
+
+#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
+#define PM_TICKLESS_TIMER_ENABLE_MASK \
+( (1UL << PM_SLEEP_MODE_IDLE) | \
+ (1UL << PM_SLEEP_MODE_DEEP))
+#endif
+
+/**
+ * @brief run mode config @ref pm_run_mode_config structure
+ */
+#ifndef PM_RUN_MODE_CFG
+#define PM_RUN_MODE_CFG \
+ { \
+ .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
+ }
+#endif /* PM_RUN_MODE_CFG */
+
+/**
+ * @brief sleep idle config @ref pm_sleep_mode_idle_config structure
+ */
+#ifndef PM_SLEEP_IDLE_CFG
+#define PM_SLEEP_IDLE_CFG \
+{ \
+ .pwc_sleep_type = PWC_SLEEP_WFE_INT, \
+}
+#endif /*PM_SLEEP_IDLE_CFG*/
+
+/**
+ * @brief sleep deep config @ref pm_sleep_mode_deep_config structure
+ */
+#ifndef PM_SLEEP_DEEP_CFG
+#define PM_SLEEP_DEEP_CFG \
+{ \
+ { \
+ .u16Clock = PWC_STOP_CLK_KEEP, \
+ .u8StopDrv = PWC_STOP_DRV_HIGH, \
+ .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
+ .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
+ }, \
+ .pwc_stop_type = PWC_STOP_WFE_INT, \
+}
+#endif /*PM_SLEEP_DEEP_CFG*/
+
+/**
+ * @brief sleep standby config @ref pm_sleep_mode_standby_config structure
+ */
+#ifndef PM_SLEEP_STANDBY_CFG
+#define PM_SLEEP_STANDBY_CFG \
+{ \
+ { \
+ .u8Mode = PWC_PD_MD1, \
+ .u8IOState = PWC_PD_IO_KEEP1, \
+ .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
+ }, \
+}
+#endif /*PM_SLEEP_STANDBY_CFG*/
+
+/**
+ * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
+ */
+#ifndef PM_SLEEP_SHUTDOWN_CFG
+#define PM_SLEEP_SHUTDOWN_CFG \
+{ \
+ { \
+ .u8Mode = PWC_PD_MD3, \
+ .u8IOState = PWC_PD_IO_KEEP1, \
+ .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
+ }, \
+}
+#endif /*PM_SLEEP_SHUTDOWN_CFG*/
+
+#endif /* BSP_USING_PM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PM_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h
new file mode 100644
index 0000000000..47a947c6ab
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h
@@ -0,0 +1,545 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_PULSE_ENCODER)
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
+#ifndef PULSE_ENCODER_TMRA_1_CONFIG
+#define PULSE_ENCODER_TMRA_1_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_1, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_1, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_1_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_1_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a1" \
+ }
+#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
+#ifndef PULSE_ENCODER_TMRA_2_CONFIG
+#define PULSE_ENCODER_TMRA_2_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_2, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_2, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_2_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_2_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a2" \
+ }
+#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
+#ifndef PULSE_ENCODER_TMRA_3_CONFIG
+#define PULSE_ENCODER_TMRA_3_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_3, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_3, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_3_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_3_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a3" \
+ }
+#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
+#ifndef PULSE_ENCODER_TMRA_4_CONFIG
+#define PULSE_ENCODER_TMRA_4_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_4, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_4, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_4_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_4_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a4" \
+ }
+#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
+#ifndef PULSE_ENCODER_TMRA_5_CONFIG
+#define PULSE_ENCODER_TMRA_5_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_5, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_5, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_5_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_5_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a5" \
+ }
+#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
+#ifndef PULSE_ENCODER_TMRA_6_CONFIG
+#define PULSE_ENCODER_TMRA_6_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_6, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_6, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_6_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_6_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a6" \
+ }
+#endif /* PULSE_ENCODER_TMRA_6_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_7
+#ifndef PULSE_ENCODER_TMRA_7_CONFIG
+#define PULSE_ENCODER_TMRA_7_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_7, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_7, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_7_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_7_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a7" \
+ }
+#endif /* PULSE_ENCODER_TMRA_7_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_8
+#ifndef PULSE_ENCODER_TMRA_8_CONFIG
+#define PULSE_ENCODER_TMRA_8_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_8, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_8, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_8_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_8_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a8" \
+ }
+#endif /* PULSE_ENCODER_TMRA_8_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_9
+#ifndef PULSE_ENCODER_TMRA_9_CONFIG
+#define PULSE_ENCODER_TMRA_9_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_9, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_9, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_9_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_9_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a9" \
+ }
+#endif /* PULSE_ENCODER_TMRA_9_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_10
+#ifndef PULSE_ENCODER_TMRA_10_CONFIG
+#define PULSE_ENCODER_TMRA_10_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_10, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_10, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_10_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_10_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a10" \
+ }
+#endif /* PULSE_ENCODER_TMRA_10_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_11
+#ifndef PULSE_ENCODER_TMRA_11_CONFIG
+#define PULSE_ENCODER_TMRA_11_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_11, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_11, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_11_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_11_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a11" \
+ }
+#endif /* PULSE_ENCODER_TMRA_11_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_12
+#ifndef PULSE_ENCODER_TMRA_12_CONFIG
+#define PULSE_ENCODER_TMRA_12_CONFIG \
+ { \
+ .tmr_handler = CM_TMRA_12, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMRA_12, \
+ .hw_count = \
+ { \
+ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
+ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMRA_12_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMRA_12_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_a12" \
+ }
+#endif /* PULSE_ENCODER_TMRA_12_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
+#ifndef PULSE_ENCODER_TMR6_1_CONFIG
+#define PULSE_ENCODER_TMR6_1_CONFIG \
+ { \
+ .tmr_handler = CM_TMR6_1, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMR6_1, \
+ .hw_count = \
+ { \
+ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
+ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMR6_1_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMR6_1_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_61" \
+ }
+#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
+#ifndef PULSE_ENCODER_TMR6_2_CONFIG
+#define PULSE_ENCODER_TMR6_2_CONFIG \
+ { \
+ .tmr_handler = CM_TMR6_2, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMR6_2, \
+ .hw_count = \
+ { \
+ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
+ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMR6_2_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMR6_2_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_62" \
+ }
+#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
+#ifndef PULSE_ENCODER_TMR6_3_CONFIG
+#define PULSE_ENCODER_TMR6_3_CONFIG \
+ { \
+ .tmr_handler = CM_TMR6_3, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMR6_3, \
+ .hw_count = \
+ { \
+ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
+ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMR6_3_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMR6_3_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_63" \
+ }
+#endif /* PULSE_ENCODER_TMR6_3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_4
+#ifndef PULSE_ENCODER_TMR6_4_CONFIG
+#define PULSE_ENCODER_TMR6_4_CONFIG \
+ { \
+ .tmr_handler = CM_TMR6_4, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMR6_4, \
+ .hw_count = \
+ { \
+ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
+ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMR6_4_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMR6_4_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_64" \
+ }
+#endif /* PULSE_ENCODER_TMR6_4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_5
+#ifndef PULSE_ENCODER_TMR6_5_CONFIG
+#define PULSE_ENCODER_TMR6_5_CONFIG \
+ { \
+ .tmr_handler = CM_TMR6_5, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMR6_5, \
+ .hw_count = \
+ { \
+ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
+ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMR6_5_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMR6_5_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_65" \
+ }
+#endif /* PULSE_ENCODER_TMR6_5_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_6
+#ifndef PULSE_ENCODER_TMR6_6_CONFIG
+#define PULSE_ENCODER_TMR6_6_CONFIG \
+ { \
+ .tmr_handler = CM_TMR6_6, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMR6_6, \
+ .hw_count = \
+ { \
+ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
+ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMR6_6_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMR6_6_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_66" \
+ }
+#endif /* PULSE_ENCODER_TMR6_6_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_7
+#ifndef PULSE_ENCODER_TMR6_7_CONFIG
+#define PULSE_ENCODER_TMR6_7_CONFIG \
+ { \
+ .tmr_handler = CM_TMR6_7, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMR6_7, \
+ .hw_count = \
+ { \
+ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
+ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMR6_7_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMR6_7_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_67" \
+ }
+#endif /* PULSE_ENCODER_TMR6_7_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_8
+#ifndef PULSE_ENCODER_TMR6_8_CONFIG
+#define PULSE_ENCODER_TMR6_8_CONFIG \
+ { \
+ .tmr_handler = CM_TMR6_8, \
+ .u32Fcg2Periph = FCG2_PERIPH_TMR6_8, \
+ .hw_count = \
+ { \
+ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
+ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
+ }, \
+ .isr = \
+ { \
+ .enIntSrc_OVF = INT_SRC_TMR6_8_OVF, \
+ .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \
+ .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \
+ .enIntSrc_UDF = INT_SRC_TMR6_8_UDF, \
+ .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \
+ .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \
+ }, \
+ .u32PeriodValue = 1000UL, \
+ .name = "pulse_68" \
+ }
+#endif /* PULSE_ENCODER_TMR6_8_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */
+
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h
new file mode 100644
index 0000000000..f20d64d50d
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h
@@ -0,0 +1,882 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __PWM_TMR_CONFIG_H__
+#define __PWM_TMR_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM_TMRA
+
+#ifdef BSP_USING_PWM_TMRA_1
+#ifndef PWM_TMRA_1_CONFIG
+#define PWM_TMRA_1_CONFIG \
+ { \
+ .name = "pwm_a1", \
+ .instance = CM_TMRA_1, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_1_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_1 */
+
+#ifdef BSP_USING_PWM_TMRA_2
+#ifndef PWM_TMRA_2_CONFIG
+#define PWM_TMRA_2_CONFIG \
+ { \
+ .name = "pwm_a2", \
+ .instance = CM_TMRA_2, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_2_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_2 */
+
+#ifdef BSP_USING_PWM_TMRA_3
+#ifndef PWM_TMRA_3_CONFIG
+#define PWM_TMRA_3_CONFIG \
+ { \
+ .name = "pwm_a3", \
+ .instance = CM_TMRA_3, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_3_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_3 */
+
+#ifdef BSP_USING_PWM_TMRA_4
+#ifndef PWM_TMRA_4_CONFIG
+#define PWM_TMRA_4_CONFIG \
+ { \
+ .name = "pwm_a4", \
+ .instance = CM_TMRA_4, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_4_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_4 */
+
+#ifdef BSP_USING_PWM_TMRA_5
+#ifndef PWM_TMRA_5_CONFIG
+#define PWM_TMRA_5_CONFIG \
+ { \
+ .name = "pwm_a5", \
+ .instance = CM_TMRA_5, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_5_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_5 */
+
+#ifdef BSP_USING_PWM_TMRA_6
+#ifndef PWM_TMRA_6_CONFIG
+#define PWM_TMRA_6_CONFIG \
+ { \
+ .name = "pwm_a6", \
+ .instance = CM_TMRA_6, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_6_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_6 */
+
+#ifdef BSP_USING_PWM_TMRA_7
+#ifndef PWM_TMRA_7_CONFIG
+#define PWM_TMRA_7_CONFIG \
+ { \
+ .name = "pwm_a7", \
+ .instance = CM_TMRA_7, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_7_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_7 */
+
+#ifdef BSP_USING_PWM_TMRA_8
+#ifndef PWM_TMRA_8_CONFIG
+#define PWM_TMRA_8_CONFIG \
+ { \
+ .name = "pwm_a8", \
+ .instance = CM_TMRA_8, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_8_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_8 */
+
+#ifdef BSP_USING_PWM_TMRA_9
+#ifndef PWM_TMRA_9_CONFIG
+#define PWM_TMRA_9_CONFIG \
+ { \
+ .name = "pwm_a9", \
+ .instance = CM_TMRA_9, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_9_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_9 */
+
+#ifdef BSP_USING_PWM_TMRA_10
+#ifndef PWM_TMRA_10_CONFIG
+#define PWM_TMRA_10_CONFIG \
+ { \
+ .name = "pwm_a10", \
+ .instance = CM_TMRA_10, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_10_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_10 */
+
+#ifdef BSP_USING_PWM_TMRA_11
+#ifndef PWM_TMRA_11_CONFIG
+#define PWM_TMRA_11_CONFIG \
+ { \
+ .name = "pwm_a11", \
+ .instance = CM_TMRA_11, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_11_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_11 */
+
+#ifdef BSP_USING_PWM_TMRA_12
+#ifndef PWM_TMRA_12_CONFIG
+#define PWM_TMRA_12_CONFIG \
+ { \
+ .name = "pwm_a12", \
+ .instance = CM_TMRA_12, \
+ .channel = 0, \
+ .stcTmraInit = \
+ { \
+ .u8CountSrc = TMRA_CNT_SRC_SW, \
+ .u32PeriodValue = 0xFFFF, \
+ .sw_count = \
+ { \
+ .u8ClockDiv = TMRA_CLK_DIV1, \
+ .u8CountMode = TMRA_MD_SAWTOOTH, \
+ .u8CountDir = TMRA_DIR_DOWN, \
+ }, \
+ .u8CountReload = TMRA_CNT_RELOAD_ENABLE\
+ }, \
+ .stcPwmInit = \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u16StartPolarity = TMRA_PWM_LOW, \
+ .u16StopPolarity = TMRA_PWM_LOW, \
+ .u16CompareMatchPolarity = TMRA_PWM_HIGH, \
+ .u16PeriodMatchPolarity = TMRA_PWM_LOW, \
+ }, \
+ }
+#endif /* PWM_TMRA_12_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_12 */
+
+#endif /* BSP_USING_PWM_TMRA */
+
+#ifdef BSP_USING_PWM_TMR4
+
+#ifdef BSP_USING_PWM_TMR4_1
+#ifndef PWM_TMR4_1_CONFIG
+#define PWM_TMR4_1_CONFIG \
+ { \
+ .name = "pwm_t41", \
+ .instance = CM_TMR4_1, \
+ .channel = 0, \
+ .stcTmr4Init = \
+ { \
+ .u16ClockDiv = TMR4_CLK_DIV1, \
+ .u16PeriodValue = 0xFFFFU, \
+ .u16CountMode = TMR4_MD_SAWTOOTH, \
+ .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
+ }, \
+ .stcTmr4OcInit = \
+ { \
+ .u16CompareValue = 0x0000, \
+ .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
+ .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
+ .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
+ .u16BufLinkTransObject = 0U, \
+ }, \
+ .stcTmr4PwmInit = \
+ { \
+ .u16Mode = TMR4_PWM_MD_THROUGH, \
+ .u16ClockDiv = TMR4_PWM_CLK_DIV1, \
+ .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+ }, \
+ }
+#endif /* PWM_TMR4_1_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_1 */
+
+#ifdef BSP_USING_PWM_TMR4_2
+#ifndef PWM_TMR4_2_CONFIG
+#define PWM_TMR4_2_CONFIG \
+ { \
+ .name = "pwm_t42", \
+ .instance = CM_TMR4_2, \
+ .channel = 0, \
+ .stcTmr4Init = \
+ { \
+ .u16ClockDiv = TMR4_CLK_DIV1, \
+ .u16PeriodValue = 0xFFFFU, \
+ .u16CountMode = TMR4_MD_SAWTOOTH, \
+ .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
+ }, \
+ .stcTmr4OcInit = \
+ { \
+ .u16CompareValue = 0x0000, \
+ .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
+ .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
+ .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
+ .u16BufLinkTransObject = 0U, \
+ }, \
+ .stcTmr4PwmInit = \
+ { \
+ .u16Mode = TMR4_PWM_MD_THROUGH, \
+ .u16ClockDiv = TMR4_PWM_CLK_DIV1, \
+ .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+ }, \
+ }
+#endif /* PWM_TMR4_2_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_2 */
+
+#ifdef BSP_USING_PWM_TMR4_3
+#ifndef PWM_TMR4_3_CONFIG
+#define PWM_TMR4_3_CONFIG \
+ { \
+ .name = "pwm_t43", \
+ .instance = CM_TMR4_3, \
+ .channel = 0, \
+ .stcTmr4Init = \
+ { \
+ .u16ClockDiv = TMR4_CLK_DIV1, \
+ .u16PeriodValue = 0xFFFFU, \
+ .u16CountMode = TMR4_MD_SAWTOOTH, \
+ .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\
+ }, \
+ .stcTmr4OcInit = \
+ { \
+ .u16CompareValue = 0x0000, \
+ .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \
+ .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\
+ .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \
+ .u16BufLinkTransObject = 0U, \
+ }, \
+ .stcTmr4PwmInit = \
+ { \
+ .u16Mode = TMR4_PWM_MD_THROUGH, \
+ .u16ClockDiv = TMR4_PWM_CLK_DIV1, \
+ .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+ }, \
+ }
+#endif /* PWM_TMR4_3_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_3 */
+
+#endif /* BSP_USING_PWM_TMR4 */
+
+#ifdef BSP_USING_PWM_TMR6
+
+#ifdef BSP_USING_PWM_TMR6_1
+#ifndef PWM_TMR6_1_CONFIG
+#define PWM_TMR6_1_CONFIG \
+ { \
+ .name = "pwm_t61", \
+ .instance = CM_TMR6_1, \
+ .channel = 0, \
+ .stcTmr6Init = \
+ { \
+ .u8CountSrc = TMR6_CNT_SRC_SW, \
+ .sw_count = \
+ { \
+ .u32ClockDiv = TMR6_CLK_DIV1, \
+ .u32CountMode = TMR6_MD_SAWTOOTH, \
+ .u32CountDir = TMR6_CNT_DOWN, \
+ }, \
+ .u32PeriodValue = 0xFFFF, \
+ .u32CountReload = TMR6_CNT_RELOAD_ON, \
+ }, \
+ .stcPwmInit = \
+ { \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ }, \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ } \
+ }, \
+ }
+#endif /* PWM_TMR6_1_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_1 */
+#ifdef BSP_USING_PWM_TMR6_2
+#ifndef PWM_TMR6_2_CONFIG
+#define PWM_TMR6_2_CONFIG \
+ { \
+ .name = "pwm_t61", \
+ .instance = CM_TMR6_2, \
+ .channel = 0, \
+ .stcTmr6Init = \
+ { \
+ .u8CountSrc = TMR6_CNT_SRC_SW, \
+ .sw_count = \
+ { \
+ .u32ClockDiv = TMR6_CLK_DIV1, \
+ .u32CountMode = TMR6_MD_SAWTOOTH, \
+ .u32CountDir = TMR6_CNT_DOWN, \
+ }, \
+ .u32PeriodValue = 0xFFFF, \
+ .u32CountReload = TMR6_CNT_RELOAD_ON, \
+ }, \
+ .stcPwmInit = \
+ { \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ }, \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ } \
+ }, \
+ }
+#endif /* PWM_TMR6_2_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_2 */
+#ifdef BSP_USING_PWM_TMR6_3
+#ifndef PWM_TMR6_3_CONFIG
+#define PWM_TMR6_3_CONFIG \
+ { \
+ .name = "pwm_t61", \
+ .instance = CM_TMR6_3, \
+ .channel = 0, \
+ .stcTmr6Init = \
+ { \
+ .u8CountSrc = TMR6_CNT_SRC_SW, \
+ .sw_count = \
+ { \
+ .u32ClockDiv = TMR6_CLK_DIV1, \
+ .u32CountMode = TMR6_MD_SAWTOOTH, \
+ .u32CountDir = TMR6_CNT_DOWN, \
+ }, \
+ .u32PeriodValue = 0xFFFF, \
+ .u32CountReload = TMR6_CNT_RELOAD_ON, \
+ }, \
+ .stcPwmInit = \
+ { \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ }, \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ } \
+ }, \
+ }
+#endif /* PWM_TMR6_3_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_3 */
+#ifdef BSP_USING_PWM_TMR6_4
+#ifndef PWM_TMR6_4_CONFIG
+#define PWM_TMR6_4_CONFIG \
+ { \
+ .name = "pwm_t61", \
+ .instance = CM_TMR6_4, \
+ .channel = 0, \
+ .stcTmr6Init = \
+ { \
+ .u8CountSrc = TMR6_CNT_SRC_SW, \
+ .sw_count = \
+ { \
+ .u32ClockDiv = TMR6_CLK_DIV1, \
+ .u32CountMode = TMR6_MD_SAWTOOTH, \
+ .u32CountDir = TMR6_CNT_DOWN, \
+ }, \
+ .u32PeriodValue = 0xFFFF, \
+ .u32CountReload = TMR6_CNT_RELOAD_ON, \
+ }, \
+ .stcPwmInit = \
+ { \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ }, \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ } \
+ }, \
+ }
+#endif /* PWM_TMR6_4_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_4 */
+#ifdef BSP_USING_PWM_TMR6_5
+#ifndef PWM_TMR6_5_CONFIG
+#define PWM_TMR6_5_CONFIG \
+ { \
+ .name = "pwm_t61", \
+ .instance = CM_TMR6_5, \
+ .channel = 0, \
+ .stcTmr6Init = \
+ { \
+ .u8CountSrc = TMR6_CNT_SRC_SW, \
+ .sw_count = \
+ { \
+ .u32ClockDiv = TMR6_CLK_DIV1, \
+ .u32CountMode = TMR6_MD_SAWTOOTH, \
+ .u32CountDir = TMR6_CNT_DOWN, \
+ }, \
+ .u32PeriodValue = 0xFFFF, \
+ .u32CountReload = TMR6_CNT_RELOAD_ON, \
+ }, \
+ .stcPwmInit = \
+ { \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ }, \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ } \
+ }, \
+ }
+#endif /* PWM_TMR6_5_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_5 */
+#ifdef BSP_USING_PWM_TMR6_6
+#ifndef PWM_TMR6_6_CONFIG
+#define PWM_TMR6_6_CONFIG \
+ { \
+ .name = "pwm_t61", \
+ .instance = CM_TMR6_6, \
+ .channel = 0, \
+ .stcTmr6Init = \
+ { \
+ .u8CountSrc = TMR6_CNT_SRC_SW, \
+ .sw_count = \
+ { \
+ .u32ClockDiv = TMR6_CLK_DIV1, \
+ .u32CountMode = TMR6_MD_SAWTOOTH, \
+ .u32CountDir = TMR6_CNT_DOWN, \
+ }, \
+ .u32PeriodValue = 0xFFFF, \
+ .u32CountReload = TMR6_CNT_RELOAD_ON, \
+ }, \
+ .stcPwmInit = \
+ { \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ }, \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ } \
+ }, \
+ }
+#endif /* PWM_TMR6_6_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_6 */
+#ifdef BSP_USING_PWM_TMR6_7
+#ifndef PWM_TMR6_7_CONFIG
+#define PWM_TMR6_7_CONFIG \
+ { \
+ .name = "pwm_t61", \
+ .instance = CM_TMR6_7, \
+ .channel = 0, \
+ .stcTmr6Init = \
+ { \
+ .u8CountSrc = TMR6_CNT_SRC_SW, \
+ .sw_count = \
+ { \
+ .u32ClockDiv = TMR6_CLK_DIV1, \
+ .u32CountMode = TMR6_MD_SAWTOOTH, \
+ .u32CountDir = TMR6_CNT_DOWN, \
+ }, \
+ .u32PeriodValue = 0xFFFF, \
+ .u32CountReload = TMR6_CNT_RELOAD_ON, \
+ }, \
+ .stcPwmInit = \
+ { \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ }, \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ } \
+ }, \
+ }
+#endif /* PWM_TMR6_7_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_7 */
+#ifdef BSP_USING_PWM_TMR6_8
+#ifndef PWM_TMR6_8_CONFIG
+#define PWM_TMR6_8_CONFIG \
+ { \
+ .name = "pwm_t61", \
+ .instance = CM_TMR6_8, \
+ .channel = 0, \
+ .stcTmr6Init = \
+ { \
+ .u8CountSrc = TMR6_CNT_SRC_SW, \
+ .sw_count = \
+ { \
+ .u32ClockDiv = TMR6_CLK_DIV1, \
+ .u32CountMode = TMR6_MD_SAWTOOTH, \
+ .u32CountDir = TMR6_CNT_DOWN, \
+ }, \
+ .u32PeriodValue = 0xFFFF, \
+ .u32CountReload = TMR6_CNT_RELOAD_ON, \
+ }, \
+ .stcPwmInit = \
+ { \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ }, \
+ { \
+ .u32CompareValue = 0x0000, \
+ .u32StartPolarity = TMR6_PWM_LOW, \
+ .u32StopPolarity = TMR6_PWM_LOW, \
+ .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \
+ .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \
+ .u32UdfPolarity = TMR6_PWM_LOW, \
+ .u32OvfPolarity = TMR6_PWM_LOW, \
+ } \
+ }, \
+ }
+#endif /* PWM_TMR6_8_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_8 */
+
+#endif /* BSP_USING_PWM_TMR6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_TMRA_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h
new file mode 100644
index 0000000000..71199a0c7c
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-04-18 CDT first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG \
+ { \
+ .Instance = CM_QSPI, \
+ .clock = FCG1_PERIPH_QSPI, \
+ .timeout = 5000UL, \
+ .err_irq.irq_config = \
+ { \
+ .irq_num = BSP_QSPI_ERR_IRQ_NUM, \
+ .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
+ .int_src = INT_SRC_QSPI_INTR, \
+ }, \
+ }
+#endif /* QSPI_BUS_CONFIG */
+
+#ifndef QSPI_INIT_PARAMS
+#define QSPI_INIT_PARAMS \
+ { \
+ .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
+ .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
+ .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
+ .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
+ }
+#endif /* QSPI_INIT_PARAMS */
+
+#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG \
+ { \
+ .Instance = QSPI_DMA_INSTANCE, \
+ .channel = QSPI_DMA_CHANNEL, \
+ .clock = QSPI_DMA_CLOCK, \
+ .trigger_select = QSPI_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_AOS_STRG, \
+ .flag = QSPI_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = QSPI_DMA_IRQn, \
+ .irq_prio = QSPI_DMA_INT_PRIO, \
+ .int_src = QSPI_DMA_INT_SRC, \
+ } \
+ }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+#endif /* BSP_USING_QSPI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__QSPI_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h
new file mode 100644
index 0000000000..3495e6ec34
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG \
+ { \
+ .Instance = CM_SPI1, \
+ .bus_name = "spi1", \
+ .clock = FCG1_PERIPH_SPI1, \
+ .timeout = 5000UL, \
+ .err_irq.irq_config = \
+ { \
+ .irq_num = BSP_SPI1_ERR_IRQ_NUM, \
+ .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
+ .int_src = INT_SRC_SPI1_SPEI, \
+ }, \
+ }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG \
+ { \
+ .Instance = SPI1_TX_DMA_INSTANCE, \
+ .channel = SPI1_TX_DMA_CHANNEL, \
+ .clock = SPI1_TX_DMA_CLOCK, \
+ .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI1_SPTI, \
+ .flag = SPI1_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI1_TX_DMA_IRQn, \
+ .irq_prio = SPI1_TX_DMA_INT_PRIO, \
+ .int_src = SPI1_TX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG \
+ { \
+ .Instance = SPI1_RX_DMA_INSTANCE, \
+ .channel = SPI1_RX_DMA_CHANNEL, \
+ .clock = SPI1_RX_DMA_CLOCK, \
+ .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI1_SPRI, \
+ .flag = SPI1_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI1_RX_DMA_IRQn, \
+ .irq_prio = SPI1_RX_DMA_INT_PRIO, \
+ .int_src = SPI1_RX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG \
+ { \
+ .Instance = CM_SPI2, \
+ .bus_name = "spi2", \
+ .clock = FCG1_PERIPH_SPI2, \
+ .timeout = 5000UL, \
+ .err_irq.irq_config = \
+ { \
+ .irq_num = BSP_SPI2_ERR_IRQ_NUM, \
+ .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \
+ .int_src = INT_SRC_SPI2_SPEI, \
+ }, \
+ }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG \
+ { \
+ .Instance = SPI2_TX_DMA_INSTANCE, \
+ .channel = SPI2_TX_DMA_CHANNEL, \
+ .clock = SPI2_TX_DMA_CLOCK, \
+ .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI2_SPTI, \
+ .flag = SPI2_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI2_TX_DMA_IRQn, \
+ .irq_prio = SPI2_TX_DMA_INT_PRIO, \
+ .int_src = SPI2_TX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG \
+ { \
+ .Instance = SPI2_RX_DMA_INSTANCE, \
+ .channel = SPI2_RX_DMA_CHANNEL, \
+ .clock = SPI2_RX_DMA_CLOCK, \
+ .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI2_SPRI, \
+ .flag = SPI2_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI2_RX_DMA_IRQn, \
+ .irq_prio = SPI2_RX_DMA_INT_PRIO, \
+ .int_src = SPI2_RX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG \
+ { \
+ .Instance = CM_SPI3, \
+ .bus_name = "spi3", \
+ .clock = FCG1_PERIPH_SPI3, \
+ .timeout = 5000UL, \
+ .err_irq.irq_config = \
+ { \
+ .irq_num = BSP_SPI3_ERR_IRQ_NUM, \
+ .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \
+ .int_src = INT_SRC_SPI3_SPEI, \
+ }, \
+ }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG \
+ { \
+ .Instance = SPI3_TX_DMA_INSTANCE, \
+ .channel = SPI3_TX_DMA_CHANNEL, \
+ .clock = SPI3_TX_DMA_CLOCK, \
+ .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI3_SPTI, \
+ .flag = SPI3_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI3_TX_DMA_IRQn, \
+ .irq_prio = SPI3_TX_DMA_INT_PRIO, \
+ .int_src = SPI3_TX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG \
+ { \
+ .Instance = SPI3_RX_DMA_INSTANCE, \
+ .channel = SPI3_RX_DMA_CHANNEL, \
+ .clock = SPI3_RX_DMA_CLOCK, \
+ .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI3_SPRI, \
+ .flag = SPI3_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI3_RX_DMA_IRQn, \
+ .irq_prio = SPI3_RX_DMA_INT_PRIO, \
+ .int_src = SPI3_RX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG \
+ { \
+ .Instance = CM_SPI4, \
+ .bus_name = "spi4", \
+ .clock = FCG1_PERIPH_SPI4, \
+ .timeout = 5000UL, \
+ .err_irq.irq_config = \
+ { \
+ .irq_num = BSP_SPI4_ERR_IRQ_NUM, \
+ .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \
+ .int_src = INT_SRC_SPI4_SPEI, \
+ }, \
+ }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG \
+ { \
+ .Instance = SPI4_TX_DMA_INSTANCE, \
+ .channel = SPI4_TX_DMA_CHANNEL, \
+ .clock = SPI4_TX_DMA_CLOCK, \
+ .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI4_SPTI, \
+ .flag = SPI4_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI4_TX_DMA_IRQn, \
+ .irq_prio = SPI4_TX_DMA_INT_PRIO, \
+ .int_src = SPI4_TX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG \
+ { \
+ .Instance = SPI4_RX_DMA_INSTANCE, \
+ .channel = SPI4_RX_DMA_CHANNEL, \
+ .clock = SPI4_RX_DMA_CLOCK, \
+ .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI4_SPRI, \
+ .flag = SPI4_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI4_RX_DMA_IRQn, \
+ .irq_prio = SPI4_RX_DMA_INT_PRIO, \
+ .int_src = SPI4_RX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG \
+ { \
+ .Instance = CM_SPI5, \
+ .bus_name = "spi5", \
+ .clock = FCG1_PERIPH_SPI5, \
+ .timeout = 5000UL, \
+ .err_irq.irq_config = \
+ { \
+ .irq_num = BSP_SPI5_ERR_IRQ_NUM, \
+ .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \
+ .int_src = INT_SRC_SPI5_SPEI, \
+ }, \
+ }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG \
+ { \
+ .Instance = SPI5_TX_DMA_INSTANCE, \
+ .channel = SPI5_TX_DMA_CHANNEL, \
+ .clock = SPI5_TX_DMA_CLOCK, \
+ .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI5_SPTI, \
+ .flag = SPI5_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI5_TX_DMA_IRQn, \
+ .irq_prio = SPI5_TX_DMA_INT_PRIO, \
+ .int_src = SPI5_TX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG \
+ { \
+ .Instance = SPI5_RX_DMA_INSTANCE, \
+ .channel = SPI5_RX_DMA_CHANNEL, \
+ .clock = SPI5_RX_DMA_CLOCK, \
+ .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI5_SPRI, \
+ .flag = SPI5_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI5_RX_DMA_IRQn, \
+ .irq_prio = SPI5_RX_DMA_INT_PRIO, \
+ .int_src = SPI5_RX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI6
+#ifndef SPI6_BUS_CONFIG
+#define SPI6_BUS_CONFIG \
+ { \
+ .Instance = CM_SPI6, \
+ .bus_name = "spi6", \
+ .clock = FCG1_PERIPH_SPI6, \
+ .timeout = 5000UL, \
+ .err_irq.irq_config = \
+ { \
+ .irq_num = BSP_SPI6_ERR_IRQ_NUM, \
+ .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \
+ .int_src = INT_SRC_SPI6_SPEI, \
+ }, \
+ }
+#endif /* SPI6_BUS_CONFIG */
+#endif /* BSP_USING_SPI6 */
+
+#ifdef BSP_SPI6_TX_USING_DMA
+#ifndef SPI6_TX_DMA_CONFIG
+#define SPI6_TX_DMA_CONFIG \
+ { \
+ .Instance = SPI6_TX_DMA_INSTANCE, \
+ .channel = SPI6_TX_DMA_CHANNEL, \
+ .clock = SPI6_TX_DMA_CLOCK, \
+ .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI6_SPTI, \
+ .flag = SPI6_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI6_TX_DMA_IRQn, \
+ .irq_prio = SPI6_TX_DMA_INT_PRIO, \
+ .int_src = SPI6_TX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI6_TX_DMA_CONFIG */
+#endif /* BSP_SPI6_TX_USING_DMA */
+
+#ifdef BSP_SPI6_RX_USING_DMA
+#ifndef SPI6_RX_DMA_CONFIG
+#define SPI6_RX_DMA_CONFIG \
+ { \
+ .Instance = SPI6_RX_DMA_INSTANCE, \
+ .channel = SPI6_RX_DMA_CHANNEL, \
+ .clock = SPI6_RX_DMA_CLOCK, \
+ .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_SPI6_SPRI, \
+ .flag = SPI6_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = SPI6_RX_DMA_IRQn, \
+ .irq_prio = SPI6_RX_DMA_INT_PRIO, \
+ .int_src = SPI6_RX_DMA_INT_SRC, \
+ } \
+ }
+#endif /* SPI6_RX_DMA_CONFIG */
+#endif /* BSP_SPI6_RX_USING_DMA */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h
new file mode 100644
index 0000000000..6ac1e5a681
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __TMR_CONFIG_H__
+#define __TMR_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_TMRA_1
+#ifndef TMRA_1_CONFIG
+#define TMRA_1_CONFIG \
+ { \
+ .tmr_handle = CM_TMRA_1, \
+ .clock_source = CLK_BUS_PCLK0, \
+ .clock = FCG2_PERIPH_TMRA_1, \
+ .flag = TMRA_FLAG_OVF, \
+ .isr = \
+ { \
+ .enIntSrc = INT_SRC_TMRA_1_OVF, \
+ .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
+ .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
+ }, \
+ .name = "tmra_1" \
+ }
+#endif /* TMRA_1_CONFIG */
+#endif /* BSP_USING_TMRA_1 */
+
+#ifdef BSP_USING_TMRA_2
+#ifndef TMRA_2_CONFIG
+#define TMRA_2_CONFIG \
+ { \
+ .tmr_handle = CM_TMRA_2, \
+ .clock_source = CLK_BUS_PCLK0, \
+ .clock = FCG2_PERIPH_TMRA_2, \
+ .flag = TMRA_FLAG_OVF, \
+ .isr = \
+ { \
+ .enIntSrc = INT_SRC_TMRA_2_OVF, \
+ .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
+ .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
+ }, \
+ .name = "tmra_2" \
+ }
+#endif /* TMRA_2_CONFIG */
+#endif /* BSP_USING_TMRA_2 */
+
+#ifdef BSP_USING_TMRA_3
+#ifndef TMRA_3_CONFIG
+#define TMRA_3_CONFIG \
+ { \
+ .tmr_handle = CM_TMRA_3, \
+ .clock_source = CLK_BUS_PCLK0, \
+ .clock = FCG2_PERIPH_TMRA_3, \
+ .flag = TMRA_FLAG_OVF, \
+ .isr = \
+ { \
+ .enIntSrc = INT_SRC_TMRA_3_OVF, \
+ .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
+ .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
+ }, \
+ .name = "tmra_3" \
+ }
+#endif /* TMRA_3_CONFIG */
+#endif /* BSP_USING_TMRA_3 */
+
+#ifdef BSP_USING_TMRA_4
+#ifndef TMRA_4_CONFIG
+#define TMRA_4_CONFIG \
+ { \
+ .tmr_handle = CM_TMRA_4, \
+ .clock_source = CLK_BUS_PCLK0, \
+ .clock = FCG2_PERIPH_TMRA_4, \
+ .flag = TMRA_FLAG_OVF, \
+ .isr = \
+ { \
+ .enIntSrc = INT_SRC_TMRA_4_OVF, \
+ .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
+ .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
+ }, \
+ .name = "tmra_4" \
+ }
+#endif /* TMRA_4_CONFIG */
+#endif /* BSP_USING_TMRA_4 */
+
+#ifdef BSP_USING_TMRA_5
+#ifndef TMRA_5_CONFIG
+#define TMRA_5_CONFIG \
+ { \
+ .tmr_handle = CM_TMRA_5, \
+ .clock_source = CLK_BUS_PCLK1, \
+ .clock = FCG2_PERIPH_TMRA_5, \
+ .flag = TMRA_FLAG_OVF, \
+ .isr = \
+ { \
+ .enIntSrc = INT_SRC_TMRA_5_OVF, \
+ .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
+ .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
+ }, \
+ .name = "tmra_5" \
+ }
+#endif /* TMRA_5_CONFIG */
+#endif /* BSP_USING_TMRA_5 */
+#endif /* __TMR_CONFIG_H__ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h
new file mode 100644
index 0000000000..c1ac81ae9e
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h
@@ -0,0 +1,449 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG \
+ { \
+ .name = "uart1", \
+ .Instance = CM_USART1, \
+ .clock = FCG3_PERIPH_USART1, \
+ .irq_num = BSP_UART1_IRQ_NUM, \
+ .rxerr_int_src = INT_SRC_USART1_EI, \
+ .rx_int_src = INT_SRC_USART1_RI, \
+ .tx_int_src = INT_SRC_USART1_TI, \
+ }
+#endif /* UART1_CONFIG */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG \
+ { \
+ .Instance = UART1_RX_DMA_INSTANCE, \
+ .channel = UART1_RX_DMA_CHANNEL, \
+ .clock = UART1_RX_DMA_CLOCK, \
+ .trigger_select = UART1_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_USART1_RI, \
+ .flag = UART1_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = UART1_RX_DMA_IRQn, \
+ .irq_prio = UART1_RX_DMA_INT_PRIO, \
+ .int_src = UART1_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* UART1_DMA_RX_CONFIG */
+
+#ifndef UART1_RXTO_CONFIG
+#define UART1_RXTO_CONFIG \
+ { \
+ .TMR0_Instance = CM_TMR0_1, \
+ .channel = TMR0_CH_A, \
+ .clock = FCG2_PERIPH_TMR0_1, \
+ .timeout_bits = 20UL, \
+ }
+#endif /* UART1_RXTO_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_TX_CPLT_CONFIG
+#define UART1_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART1_TCI, \
+ }, \
+ }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART1_TX_CPLT_CONFIG
+#define UART1_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART1_TCI, \
+ }, \
+ }
+#endif
+#endif /* UART1_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG \
+ { \
+ .Instance = UART1_TX_DMA_INSTANCE, \
+ .channel = UART1_TX_DMA_CHANNEL, \
+ .clock = UART1_TX_DMA_CLOCK, \
+ .trigger_select = UART1_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_USART1_TI, \
+ .flag = UART1_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = UART1_TX_DMA_IRQn, \
+ .irq_prio = UART1_TX_DMA_INT_PRIO, \
+ .int_src = UART1_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG \
+ { \
+ .name = "uart2", \
+ .Instance = CM_USART2, \
+ .clock = FCG3_PERIPH_USART2, \
+ .irq_num = BSP_UART2_IRQ_NUM, \
+ .rxerr_int_src = INT_SRC_USART2_EI, \
+ .rx_int_src = INT_SRC_USART2_RI, \
+ .tx_int_src = INT_SRC_USART2_TI, \
+ }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG \
+ { \
+ .Instance = UART2_RX_DMA_INSTANCE, \
+ .channel = UART2_RX_DMA_CHANNEL, \
+ .clock = UART2_RX_DMA_CLOCK, \
+ .trigger_select = UART2_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_USART2_RI, \
+ .flag = UART2_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = UART2_RX_DMA_IRQn, \
+ .irq_prio = UART2_RX_DMA_INT_PRIO, \
+ .int_src = UART2_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* UART2_DMA_RX_CONFIG */
+
+#ifndef UART2_RXTO_CONFIG
+#define UART2_RXTO_CONFIG \
+ { \
+ .TMR0_Instance = CM_TMR0_1, \
+ .channel = TMR0_CH_B, \
+ .clock = FCG2_PERIPH_TMR0_1, \
+ .timeout_bits = 20UL, \
+ }
+#endif /* UART2_RXTO_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_TX_CPLT_CONFIG
+#define UART2_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART2_TCI, \
+ }, \
+ }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART2_TX_CPLT_CONFIG
+#define UART2_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART2_TCI, \
+ }, \
+ }
+#endif
+#endif /* UART2_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG \
+ { \
+ .Instance = UART2_TX_DMA_INSTANCE, \
+ .channel = UART2_TX_DMA_CHANNEL, \
+ .clock = UART2_TX_DMA_CLOCK, \
+ .trigger_select = UART2_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_USART2_TI, \
+ .flag = UART2_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = UART2_TX_DMA_IRQn, \
+ .irq_prio = UART2_TX_DMA_INT_PRIO, \
+ .int_src = UART2_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG \
+ { \
+ .name = "uart3", \
+ .Instance = CM_USART3, \
+ .clock = FCG3_PERIPH_USART3, \
+ .irq_num = BSP_UART3_IRQ_NUM, \
+ .rxerr_int_src = INT_SRC_USART3_EI, \
+ .rx_int_src = INT_SRC_USART3_RI, \
+ .tx_int_src = INT_SRC_USART3_TI, \
+ }
+#endif /* UART3_CONFIG */
+
+#if defined(RT_USING_SERIAL_V2)
+#ifndef UART3_TX_CPLT_CONFIG
+#define UART3_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART3_TCI, \
+ }, \
+ }
+#endif
+#endif /* UART3_TX_CPLT_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG \
+ { \
+ .name = "uart4", \
+ .Instance = CM_USART4, \
+ .clock = FCG3_PERIPH_USART4, \
+ .irq_num = BSP_UART4_IRQ_NUM, \
+ .rxerr_int_src = INT_SRC_USART4_EI, \
+ .rx_int_src = INT_SRC_USART4_RI, \
+ .tx_int_src = INT_SRC_USART4_TI, \
+ }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG \
+ { \
+ .Instance = UART4_RX_DMA_INSTANCE, \
+ .channel = UART4_RX_DMA_CHANNEL, \
+ .clock = UART4_RX_DMA_CLOCK, \
+ .trigger_select = UART4_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_USART4_RI, \
+ .flag = UART4_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = UART4_RX_DMA_IRQn, \
+ .irq_prio = UART4_RX_DMA_INT_PRIO, \
+ .int_src = UART4_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* UART4_DMA_RX_CONFIG */
+
+#ifndef UART4_RXTO_CONFIG
+#define UART4_RXTO_CONFIG \
+ { \
+ .TMR0_Instance = CM_TMR0_2, \
+ .channel = TMR0_CH_A, \
+ .clock = FCG2_PERIPH_TMR0_2, \
+ .timeout_bits = 20UL, \
+ }
+#endif /* UART4_RXTO_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_TX_CPLT_CONFIG
+#define UART4_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART4_TCI, \
+ }, \
+ }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART4_TX_CPLT_CONFIG
+#define UART4_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART4_TCI, \
+ }, \
+ }
+#endif
+#endif /* UART4_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG \
+ { \
+ .Instance = UART4_TX_DMA_INSTANCE, \
+ .channel = UART4_TX_DMA_CHANNEL, \
+ .clock = UART4_TX_DMA_CLOCK, \
+ .trigger_select = UART4_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_USART4_TI, \
+ .flag = UART4_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = UART4_TX_DMA_IRQn, \
+ .irq_prio = UART4_TX_DMA_INT_PRIO, \
+ .int_src = UART4_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG \
+ { \
+ .name = "uart5", \
+ .Instance = CM_USART5, \
+ .clock = FCG3_PERIPH_USART5, \
+ .irq_num = BSP_UART5_IRQ_NUM, \
+ .rxerr_int_src = INT_SRC_USART5_EI, \
+ .rx_int_src = INT_SRC_USART5_RI, \
+ .tx_int_src = INT_SRC_USART5_TI, \
+ }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG \
+ { \
+ .Instance = UART5_RX_DMA_INSTANCE, \
+ .channel = UART5_RX_DMA_CHANNEL, \
+ .clock = UART5_RX_DMA_CLOCK, \
+ .trigger_select = UART5_RX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_USART5_RI, \
+ .flag = UART5_RX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = UART5_RX_DMA_IRQn, \
+ .irq_prio = UART5_RX_DMA_INT_PRIO, \
+ .int_src = UART5_RX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* UART5_DMA_RX_CONFIG */
+
+#ifndef UART5_RXTO_CONFIG
+#define UART5_RXTO_CONFIG \
+ { \
+ .TMR0_Instance = CM_TMR0_2, \
+ .channel = TMR0_CH_B, \
+ .clock = FCG2_PERIPH_TMR0_2, \
+ .timeout_bits = 20UL, \
+ }
+#endif /* UART5_RXTO_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_TX_CPLT_CONFIG
+#define UART5_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART5_TCI, \
+ }, \
+ }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART5_TX_CPLT_CONFIG
+#define UART5_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART5_TCI, \
+ }, \
+ }
+#endif
+#endif /* UART5_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG \
+ { \
+ .Instance = UART5_TX_DMA_INSTANCE, \
+ .channel = UART5_TX_DMA_CHANNEL, \
+ .clock = UART5_TX_DMA_CLOCK, \
+ .trigger_select = UART5_TX_DMA_TRIG_SELECT, \
+ .trigger_event = EVT_SRC_USART5_TI, \
+ .flag = UART5_TX_DMA_TRANS_FLAG, \
+ .irq_config = \
+ { \
+ .irq_num = UART5_TX_DMA_IRQn, \
+ .irq_prio = UART5_TX_DMA_INT_PRIO, \
+ .int_src = UART5_TX_DMA_INT_SRC, \
+ }, \
+ }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG \
+ { \
+ .name = "uart6", \
+ .Instance = CM_USART6, \
+ .clock = FCG3_PERIPH_USART6, \
+ .irq_num = BSP_UART6_IRQ_NUM, \
+ .rxerr_int_src = INT_SRC_USART6_EI, \
+ .rx_int_src = INT_SRC_USART6_RI, \
+ .tx_int_src = INT_SRC_USART6_TI, \
+ }
+#endif /* UART6_CONFIG */
+
+#if defined(RT_USING_SERIAL_V2)
+#ifndef UART6_TX_CPLT_CONFIG
+#define UART6_TX_CPLT_CONFIG \
+ { \
+ .irq_config = \
+ { \
+ .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \
+ .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \
+ .int_src = INT_SRC_USART6_TCI, \
+ }, \
+ }
+#endif
+#endif /* UART6_TX_CPLT_CONFIG */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h
new file mode 100644
index 0000000000..64b5b592da
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dma_config.h"
+#include "uart_config.h"
+#include "spi_config.h"
+#include "adc_config.h"
+#include "dac_config.h"
+#include "gpio_config.h"
+#include "can_config.h"
+#include "pm_config.h"
+#include "i2c_config.h"
+#include "qspi_config.h"
+#include "pulse_encoder_config.h"
+#include "timer_config.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h
new file mode 100644
index 0000000000..c8f47fe163
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h
@@ -0,0 +1,136 @@
+/**
+ *******************************************************************************
+ * @file template/source/hc32f4xx_conf.h
+ * @brief This file contains HC32 Series Device Driver Library usage management.
+ @verbatim
+ Change Logs:
+ Date Author Notes
+ 2023-05-31 CDT First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32F4XX_CONF_H__
+#define __HC32F4XX_CONF_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @brief This is the list of modules to be used in the Device Driver Library.
+ * Select the modules you need to use to DDL_ON.
+ * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
+ * properly.
+ * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
+ * Library.
+ * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
+ */
+#define LL_ICG_ENABLE (DDL_ON)
+#define LL_UTILITY_ENABLE (DDL_ON)
+#define LL_PRINT_ENABLE (DDL_OFF)
+
+#define LL_ADC_ENABLE (DDL_ON)
+#define LL_AES_ENABLE (DDL_ON)
+#define LL_AOS_ENABLE (DDL_ON)
+#define LL_CLK_ENABLE (DDL_ON)
+#define LL_CMP_ENABLE (DDL_ON)
+#define LL_CRC_ENABLE (DDL_ON)
+#define LL_CTC_ENABLE (DDL_ON)
+#define LL_DAC_ENABLE (DDL_ON)
+#define LL_DBGC_ENABLE (DDL_OFF)
+#define LL_DCU_ENABLE (DDL_ON)
+#define LL_DMA_ENABLE (DDL_ON)
+#define LL_EFM_ENABLE (DDL_ON)
+#define LL_EMB_ENABLE (DDL_ON)
+#define LL_EVENT_PORT_ENABLE (DDL_OFF)
+#define LL_FCG_ENABLE (DDL_ON)
+#define LL_FCM_ENABLE (DDL_ON)
+#define LL_GPIO_ENABLE (DDL_ON)
+#define LL_HASH_ENABLE (DDL_ON)
+#define LL_I2C_ENABLE (DDL_ON)
+#define LL_INTERRUPTS_ENABLE (DDL_ON)
+#define LL_KEYSCAN_ENABLE (DDL_ON)
+#define LL_MCAN_ENABLE (DDL_ON)
+#define LL_MPU_ENABLE (DDL_ON)
+#define LL_PWC_ENABLE (DDL_ON)
+#define LL_QSPI_ENABLE (DDL_ON)
+#define LL_RMU_ENABLE (DDL_ON)
+#define LL_RTC_ENABLE (DDL_ON)
+#define LL_SMC_ENABLE (DDL_ON)
+#define LL_SPI_ENABLE (DDL_ON)
+#define LL_SRAM_ENABLE (DDL_ON)
+#define LL_SWDT_ENABLE (DDL_ON)
+#define LL_TMR0_ENABLE (DDL_ON)
+#define LL_TMR4_ENABLE (DDL_ON)
+#define LL_TMR6_ENABLE (DDL_ON)
+#define LL_TMRA_ENABLE (DDL_ON)
+#define LL_TRNG_ENABLE (DDL_ON)
+#define LL_USART_ENABLE (DDL_ON)
+#define LL_WDT_ENABLE (DDL_ON)
+
+/**
+ * @brief The following is a list of currently supported BSP boards.
+ */
+#define BSP_EV_HC32F472_LQFP80 (9U)
+
+/**
+ * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
+ * in use.
+ * The value should be set to one of the list of currently supported BSP boards.
+ * @note If there is no supported BSP board or the BSP function is not used,
+ * the value needs to be set to 0U.
+ */
+#define BSP_EV_HC32F4XX (0U)
+
+/**
+ * @brief This is the list of BSP components to be used.
+ * Select the components you need to use to DDL_ON.
+ */
+#define BSP_24CXX_ENABLE (DDL_OFF)
+#define BSP_GT9XX_ENABLE (DDL_OFF)
+#define BSP_IS61LV6416_ENABLE (DDL_OFF)
+#define BSP_NT35510_ENABLE (DDL_OFF)
+#define BSP_TCA9539_ENABLE (DDL_OFF)
+#define BSP_W25QXX_ENABLE (DDL_OFF)
+#define BSP_INT_KEY_ENABLE (DDL_OFF)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32F4XX_CONF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf
new file mode 100644
index 0000000000..1e01b623b0
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf
@@ -0,0 +1,116 @@
+/***************************************************************************//**
+ * \file HC32F472.icf
+ * \version 1.0
+ *
+ * \brief Linker file for the IAR compiler.
+ *
+********************************************************************************
+* \copyright
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+*******************************************************************************/
+/*###ICF### Section handled by ICF editor, don't touch! *****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+
+// Check that necessary symbols have been passed to linker via command line interface
+if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
+ error "Link location not defined or not supported!";
+}
+if((!isdefinedsymbol(_HC32F472_512K_)) && (!isdefinedsymbol(_HC32F472_256K_SINGLE_)) && (!isdefinedsymbol(_HC32F472_256K_DUAL_))) {
+ error "Mcu type or size not defined or not supported!";
+}
+
+
+/*******************************************************************************
+ * Memory address and size definitions
+ ******************************************************************************/
+define symbol ram1_base_address = 0x1FFF8000;
+define symbol ram1_end_address = 0x20007FFF;
+
+if(isdefinedsymbol(_LINK_RAM_)) {
+ define symbol ram_start_reserve = 0x8000;
+ define symbol rom1_base_address = ram1_base_address;
+ define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
+ define symbol rom2_base_address = 0x0;
+ define symbol rom2_end_address = 0x0;
+ define symbol rom3_base_address = 0x0;
+ define symbol rom3_end_address = 0x0;
+} else {
+ define symbol ram_start_reserve = 0x0;
+ define symbol rom1_base_address = 0x0;
+ define symbol rom3_base_address = 0x03000000;
+ define symbol rom3_end_address = 0x030017FF;
+ if(isdefinedsymbol(_HC32F472_512K_)) {
+ define symbol rom1_end_address = 0x0007FFFF;
+ define symbol rom2_base_address = 0x0;
+ define symbol rom2_end_address = 0x0;
+ } else if (isdefinedsymbol(_HC32F472_256K_SINGLE_)) {
+ define symbol rom1_end_address = 0x0003FFFF;
+ define symbol rom2_base_address = 0x0;
+ define symbol rom2_end_address = 0x0;
+ } else if (isdefinedsymbol(_HC32F472_256K_DUAL_)) {
+ define symbol rom1_end_address = 0x0001FFFF;
+ define symbol rom2_base_address = 0x00040000;
+ define symbol rom2_end_address = 0x0005FFFF;
+ }
+}
+
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
+define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
+define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
+define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
+define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
+define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
+define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0xC00;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+/*******************************************************************************
+ * Memory definitions
+ ******************************************************************************/
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in OTP_region { readonly section .otp_data };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld
new file mode 100644
index 0000000000..d52f564cb4
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld
@@ -0,0 +1,276 @@
+/******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ */
+/*****************************************************************************/
+/* File HC32F472xE.ld */
+/* Abstract Linker script for HC32F472 Device with */
+/* 512KByte FLASH, 68KByte RAM */
+/* Version V1.0 */
+/* Date 2022-06-30 */
+/*****************************************************************************/
+
+/* Custom defines, according to section 7.7 of the user manual.
+ Take OTP sector 16 for example. */
+__OTP_DATA_START = 0x03000000;
+__OTP_DATA_SIZE = 2048;
+__OTP_LOCK_START = 0x03001800;
+__OTP_LOCK_SIZE = 728;
+
+/* Use contiguous memory regions for simple. */
+MEMORY
+{
+ FLASH (rx): ORIGIN = 0x00000000, LENGTH = 512K
+ OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
+ OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
+ RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 64K
+ RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
+ QSPI_ROM (rx): ORIGIN = 0x98000000, LENGTH = 8M
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .vectors :
+ {
+ . = ALIGN(4);
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ } >FLASH
+
+ .icg_sec 0x00000400 :
+ {
+ KEEP(*(.icg_sec))
+ } >FLASH
+
+ .ex_rom :
+ {
+ . = ALIGN(4);
+ KEEP(*(.ex_rom))
+ . = ALIGN(4);
+ } >QSPI_ROM
+
+ .text :
+ {
+ . = ALIGN(4);
+ _stext = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ *(.text) /* remaining code */
+ *(.text.*) /* remaining code */
+ *(.rodata) /* read-only data (constants) */
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.gnu.linkonce.t*)
+
+ /* section information for finsh shell */
+ . = ALIGN(4);
+ __fsymtab_start = .;
+ KEEP(*(FSymTab))
+ __fsymtab_end = .;
+ . = ALIGN(4);
+ __vsymtab_start = .;
+ KEEP(*(VSymTab))
+ __vsymtab_end = .;
+ . = ALIGN(4);
+
+ /* section information for initial. */
+ . = ALIGN(4);
+ __rt_init_start = .;
+ KEEP(*(SORT(.rti_fn*)))
+ __rt_init_end = .;
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ _etext = .;
+ } >FLASH
+
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } >FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >FLASH
+ __exidx_end = .;
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ __etext = ALIGN(4);
+
+ .otp_data_sec :
+ {
+ KEEP(*(.otp_data_sec))
+ } >OTP_DATA
+
+ .otp_lock_sec :
+ {
+ KEEP(*(.otp_lock_sec))
+ } >OTP_LOCK
+
+ .data : AT (__etext)
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data*)
+ *(.gnu.linkonce.d*)
+ . = ALIGN(4);
+ *(.ramfunc)
+ *(.ramfunc*)
+ . = ALIGN(4);
+ __data_end__ = .;
+ } >RAM
+
+ __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
+ .ramb_data : AT (__etext_ramb)
+ {
+ . = ALIGN(4);
+ __data_start_ramb__ = .;
+ *(.ramb_data)
+ *(.ramb_data*)
+ . = ALIGN(4);
+ __data_end_ramb__ = .;
+ } >RAMB
+
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ _sbss = .;
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ __bss_end__ = _ebss;
+ . = ALIGN(4);
+ *(.noinit*)
+ . = ALIGN(4);
+ } >RAM
+
+ .ramb_bss :
+ {
+ . = ALIGN(4);
+ __bss_start_ramb__ = .;
+ *(.ramb_bss)
+ *(.ramb_bss*)
+ . = ALIGN(4);
+ __bss_end_ramb__ = .;
+ } >RAMB
+
+ .heap_stack (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ PROVIDE(_end = .);
+ *(.heap*)
+ . = ALIGN(8);
+ __HeapLimit = .;
+
+ __StackLimit = .;
+ *(.stack*)
+ . = ALIGN(8);
+ __StackTop = .;
+ } >RAM
+
+ /DISCARD/ :
+ {
+ libc.a (*)
+ libm.a (*)
+ libgcc.a (*)
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ PROVIDE(_stack = __StackTop);
+ PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
+ PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
+
+ __RamEnd = ORIGIN(RAM) + LENGTH(RAM);
+ ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+}
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..b183673e76
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.sct
@@ -0,0 +1,22 @@
+; ****************************************************************
+; Scatter-Loading Description File
+; ****************************************************************
+LR_IROM1 0x00000000 0x00080000 { ; load region size_region
+ ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+ RW_IRAM1 0x1FFF8000 UNINIT 0x00000008 { ; RW data
+ *(.bss.noinit)
+ }
+ RW_IRAM2 0x1FFF8008 0x0000FFF8 { ; RW data
+ .ANY (+RW +ZI)
+ .ANY (RAMCODE)
+ }
+ RW_IRAMB 0x200F0000 0x00001000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h
new file mode 100644
index 0000000000..1f8fb29c76
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-02-20 CDT first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include
+#include
+
+/* enable hc32f4 onchip flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_HC32F4
+/* enable SFUD flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_SFUD
+
+extern const struct fal_flash_dev hc32_onchip_flash;
+extern struct fal_flash_dev ext_nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE \
+{ \
+ &hc32_onchip_flash, \
+ &ext_nor_flash0, \
+}
+
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE \
+{ \
+ {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 256 * 1024, 0}, \
+ {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h
new file mode 100644
index 0000000000..1548ec16d7
--- /dev/null
+++ b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-04-28 CDT first version
+ */
+
+#ifndef __TCA9539_PORT_H__
+#define __TCA9539_PORT_H__
+
+#include "tca9539.h"
+
+/**
+ * @defgroup HC32F472_EV_IO_Function_Sel Expand IO function definition
+ * @{
+ */
+#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */
+#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */
+#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */
+#define EIO_RTCS_CTRST (TCA9539_IO_PIN5) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */
+#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */
+#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */
+
+#define EIO_LIN2_SLEEP (TCA9539_IO_PIN0) /* LIN1 PHY sleep, output */
+#define EIO_LIN1_SLEEP (TCA9539_IO_PIN1) /* LIN2 PHY sleep, output */
+#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */
+#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */
+#define EIO_CAN3_STB (TCA9539_IO_PIN4) /* CAN3 PHY standby, output */
+#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
+#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
+#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
+ * @{
+ */
+#define LED_RED_PORT (TCA9539_IO_PORT1)
+#define LED_RED_PIN (EIO_LED_RED)
+#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
+#define LED_YELLOW_PIN (EIO_LED_YELLOW)
+#define LED_BLUE_PORT (TCA9539_IO_PORT1)
+#define LED_BLUE_PIN (EIO_LED_BLUE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup BSP_CAN_PortPin_Sel BSP CAN PHY STB port/pin definition
+ * @{
+ */
+#define CAN1_STB_PORT (TCA9539_IO_PORT1)
+#define CAN1_STB_PIN (EIO_CAN1_STB)
+#define CAN2_STB_PORT (TCA9539_IO_PORT1)
+#define CAN2_STB_PIN (EIO_CAN2_STB)
+#define CAN3_STB_PORT (TCA9539_IO_PORT1)
+#define CAN3_STB_PIN (EIO_CAN3_STB)
+/**
+ * @}
+ */
+
+#endif
diff --git a/bsp/hc32/ev_hc32f472_lqfp100/figures/board.png b/bsp/hc32/ev_hc32f472_lqfp100/figures/board.png
new file mode 100644
index 0000000000000000000000000000000000000000..82ef204bc49a3222b74cc4f68451e2ce7174d30e
GIT binary patch
literal 9670538
zcmcG!RZv__^zJf000bmIVp7j0IdW7Ku$(M`nU2s5Bcfe
zfa)Zt;|c(vJyyGEewWYS7~j
z3R8mDdtDZyapZYwsP0%fWzo>gi(2m9NUtkjvD%V7kN@uq)N*nR`OmL!A?7Bo&iqGR
z2^He13km*51u(ct*vkG#ja-DO$ekViN8RU6qgImtSM}fuQbUXXqxL){7)m_c{-d5%
zj>6{ud$3Xee++iXCc^(SAU)_5R-sw&2q@TLD40P22pJ|2p!zHto9R>R?)Lo2_`M2d
z@5Ts27UuK7=
zkKr~9R6q!DbP?sNmX^Z&}69^G5@YUDWJs@PqR
zvf?oL?ouZ+S0@iY-sws73n#OmUC_2k=t;m}OL&`kO8S}-K|GGDID)v2vi|9mNJi$F>H9xf#)p^xj-KX=g3qR$
zLyLr;RMW*qw)&QggAd|7%Ev;4qo>U+Z3#T5g0a4B?Gh1L+5xEO4lR7O2}1~W6uI;A
zN_5O=+d#sS&E1YN(3#%zTx#^CHmCX1m`t-?-3UKe5)1ZTkj#QanO)9%WbdnQ)6bo}
z&LonhgMFEtKYs%jUGW5xAa*+d=_H}VlvUpa!B6)3ESzC`Ub>NFd-{!w$
z(Jv3CUCYtlBV5M9LWVEhgm1!s*hdr_))hSH26f%(LMa3y0X2?q2Zu{b(7lVr3-k6D
zUqQpSs+k|d^+yWI-yB|f<-Ts7XFJi=cQ2A5i?CuMU-|oeFEQJCTJcF(@@!FK38g}7
zKQGW`Q!F5rxKtSa!~6QXH%fnm?}10a?diq&`MV@cFaL|PC=JbS_Qi+I8--!}y*WqJ
z6w;Bo77@?ZzpC)Rs6Ni_5ZbMMwi6W?WLhlzy&OH=^5R5WSo;HS>rf?9vX#Ty-)>1;
zXQu=0^tCe}1Hog~{pr2!z9o&|ZI}D&`qK{~!($1S`40!5bUS8EzGq*oufRvAM{8X-
zIPM7^IBy+TArA-p=9K+QDwO{_sjjr6-Y!J%=h#sCfxQ?DWGDEg%)=>=SokPniP)Z7
z-=3qm#hIC_k8y8vf!BfWv=aovaC0zh(W)_fokZe@MoiEbGli7QRCKFM^9ZeZQq;E%
z#Zsu1j7>r1aC=T69cD~iX{BOc2bO!CGKgb@h>&=Zpi^*Sm57$BQRbjX(@G?F;E${7cUVKK-eUpNO~5Cco$4{jl%<`O?go2Qq|Ik6?Jqq7`m;7
z_|2^~0c2aHNHzF3zksdc5pa&1T{}7FSI5WjdHI{P)O{IaGHHfFr(AJLI)rjK_fGR)K!HzN
z&mDiZo_qsC0#6-Zl!e!G0ZmjL2FM-38!q4JiLEiVxh_I*SiF-A={5uCRs-%E*$O?s
zal_ZsBej@|A*}fmHeOcmXY*A?4Q$nk_Nb6R1H#p7S~oeA!X>SP0woixhr}Ip35fe*QF{U
z6d9;p)+b9!K&v)-``iOn1%f^b$UfG-{dKj#pUdWeL`51
z8K~Fu`oyPtzEAVbqL4u*$Pp-k8?4cFM9lkh1Hy&&c~InRKB^qY;sw*E^p8
zdfPA!p9d1h!x*!k<;MdPVM?e5-!D~BX2))c_Aa0N)1CDePiH!FoZ783ccap-kLSTb
zXX|fS_s3U;4$%|*lh^?_A6WjbUG3(sn*64e?;Qd3Kd#*B-U*O4RgM9@QWH(v`qOc+IExQ1w?7r>_rC0RX!B=p6hQ
zSz2uy@pd=bJF~a419BCoAO^l&yixiTzbMAP
zU5eftsp=5S7a7CZ3Nkio%3AaigBz(}7{J1?6eI|jZB1OlaD^p+6vnJ!ciH|$(;WTp
zP(h0hEh`5Cf;`A-*sm?94~!jz+e83{-}4%FA`w5BP7NymdGPd&AFdz5rEZ{_4n&qr
z1^}8E4_x~AV*x~(gme(bLm41w){G5(K2)h|94%HLG!hPB8f)tnDFt_)`9xiez`pnd
zQf+JrVuA;R5rb`NzA#D`RsrCv@Rf)UJGjCSCB!py^YWc_LhdsnV^cnkCW|SJdI!N*
zH1`r3SE4JhWw1|G2-1EvrZij#zDj*R3lBkdk|AfS
zv+%}?MoY31oj|j}>q~|}6&nIike4#?H-XWG(QO2zFr45Na*#%mZ7Pw(07SJWJWV}U
zEC*-KiG*oP%o{I6XhOH(t9oXBp?Dx&I%Jy$Eu_3299*12fuzY$gLowi^0a>&0^DDhOqdGuosK%ix5Eq`uVs-IPYARI6Gfa(!V>n1bA~C1(ELLZ(WXU8@
z|JqcM2tnT-&iE;zOQ@k8v@Ia*aOx%~^yB_!u9!idH#Ri03i~U%l{5jZxJ5=*ySF$!
zFMbl*Py7NjFZVLwu0pKfXlss3El?epjSlNA6M0gXIEis}p$*Y22=EyW$E6ryICAL=
ze9V6%yno4mqd}=esK1C-FaLlVkR7|ce&5ZGyCj#%rw-^?^gWN&sG`)*BkC-
z7iNg=kyFvZU&z(nYJ(0!V%QE*))c24HZvkTd+lDPvfHqz*Je;+G
zi46~JS$27=CZhhBGXiYrwrdqbz=B2JmKS>3WoJfGOBY%H<3l~BKZE*q>)W3JhlJY?
z^D@(`s8oOYuWzT%Nv#qbZ=0*#*$jFb2y>+EV$8B@*bH>gd)jlm)IzuJM))*!_}2K0
z#-i&Om#(10E8Qz!N}ASuKcAJh+|dNx*OpmF-Wr6%Dwqy=Xsj67YK@=-?lort_3WGT
z7ntTyGvD)jjil0pmT)(|
z3uL}Cl5!^`BdC!5VQHLHd-IA(PK^Pvk}^Fcs@)Eo0248IglqY=@90~H#L-XR0(ct-
zyJA{_m|FDv`v|dSU5ShFm{vhY@-@@IDYtzwinqP0V%+C()L=}1Z{HiKdJh=`{Ld{n
zdkWjObe1BpE>i5D%{rIi(hr7U;zP>Foo%1)ZzVf*Du>O<+-skId9^(i&+Y^~8$ZNl
z=eLYKd)T8aNQ%O^*m?N0)h&Vc%-^(`8|>P9Na|+wOO=avw?J9zA*=)R-Q;at%Ci8`uBVgBqN?4`@x_*G^V
zGDLs-k9rPm&~kV_okKYmIRbC!;&Uy1244LCUfiaW81=ioY}jF+Kh`d~f6)vn?fPuO
zQj{jyH@q5YzhBN3mDK*OG(DSnO;wg!$8l?VCj9g$#JOWft%@CBa^Hm}pk*eQ`gbHumUxyPf!a}#8
ziVE(eNEK0zs4YomUP}U1QW70ARu#%+3ILkGe-qPGYYL$T$5WNsQcFR!
zs44=f0FBJH2F6uuu8Smrv@~)8Gl>yt-yq512M`
z0E7knn?E4e5lE~PMo3|%Ssnul2O9Fjl^YHil^I|XBKMrlb#ZM92t&}tSJc_vAcE|}
z(fN+PQ+$_vuV2H(W>JV@8uqy6B_f$2{}p??q}CW-jkX~g{42+X=zQBD<1o63mQ@6a5Fn0itpsP03gj3g)u3^K6~ER+
zA;>qDnuLW&mLG_lYS07B*{(A`g~)8t$^+r8b>3NPx_sgnJ5Z@bqbbtGKUY9dRUiga
z^Mx+9ml6(}0FuB~(SzyCnIx6ky^3Lpa*4BIOyw1(ixLaD>#^UpN=yKfqe}8&_ipVB
zp(aeJc_N+24Ah$R)dbRS$-S&8xWRO^hX^z}ah(Nd2qrjAb%tLB#5V*qh&~w7sN?i{
zfBHd6H{(RoyWi9*t{BeGk;1`-3#XD76`l!;@+%ES#THgvkcdVYurW>>6f0CmOSPb8
z%#d2vls}bF%*-4rGMEL2$t0l=p&2hqSm*{DM1ffmLd58}-*KCx&y40mv@>Y>=P(Jz
z+1kv_&pUA*#0EjA*W?@=s4%pc_wNU{>4I==HKQQs=SU^ogXiiP2l!NylPmHFwH%R^
z;SJ?-x}V%2HBM}*@M?-Z8KnBTWHM4>$x7fL1M573tTc3Ig;vrjDxfW*T$st`Xfcwu
zad3Yj5mRV*ufP+em-KCc*ntiKOq#P@CIVVvLOs#fr)z5ypXfb@XgcoeM1jC2kkGIa
zL|?>&d=UwADuM_xV@N&Ru^)1;^Efe+6`!Zl)W`e#`yF(a
zU2uDU%*xH5FzS3ro(vs!0xy@UDr5(s$ps`s4awoEVxbWAALQ1Ie_vQKMfSZo+8C~2)BR%600t>JPPir@
zH3bxlMr)yhrm_%}#jFiLM8!8&jxgQsFP?WMBH-1aR32IC*ZRDC$2?V@;&EK0~4+wsn>A4df+C;E`6|C`rte+i8!fJzLYd{*p#yt;VK20#6U5N_}}I2Gb!
zT;Z@KVMpQg63=4s)dRzk4#{XOU7+@`RlRAYwh;%_Ve=;V>Bs5oZ#4B*b)-HFtU;sK
z@)q-4N)(nPc%8FdEv+*dL&V9pwc(eW{_ovZmq!Jc?jJsU*|SOchmoxhAseY>Z<)9d
zFAMur+5VX9I^pP-EEYBRWzDZaEWaAop5PobM=PAk{AruW57jo4
zyPBB5_Le`=$7Khdd-11$C_p1`jjfP%}$jcYC3|c3Ab{2*2Zcsd@0VDu#ZeiSn|zzwC+PbtK^Jabga=fh8b2
z@7L+Y`b&%7)`F>1##%th3-2$@E&FM4FAJDqwc2j@2fpSj740qOMu$z83Y&|8x=Pw^
zqJ-B5ajeOmI?t5U-@oe`TOCs=H;kHC9wu6Q6a2TT{Y`rMii^&xpJJ-{J}!;$Z}|$(
zo!YxwfAlE~@nSR=p6t>-8R&)nz27PQZhpNNVBWP@Tif|f><1J1+=8F=c^&Gzi>=eT
zxZqQF!&qe>F=Qzih-jZPu>A{)|5+*rjSeCbgYq
zt=;e8zOv-^REi2SK5lOAo#HH1*B+vekZ%|KKIIQHHT*K;U?#^d@}_qHqa?ixczJ0`
zJ~xW}sjXoZZAhTG{kd*ObhEauYi-Z)&BKtcXu`lU?v1}zvp!)BHW2Z|kL=Jg^m)Vi
z*;dqx{Hsp(4@4us4>gIneU;%A@dmxR*&?9I5pzMoS38;ibA|ED5+nUGwDSZlIEX1^
z&=7nT*bclFeZi8i4#5=%Yc(n|G5!rXejuI`9#FnIc*S%SeIr`{m9om^h$r)*<5dH&
zQ11@0L*R5--Wk*@5yGZ$6*%^Vfl9{mtvx-FSvzxkvb`YBL*IQ4c))`0fJjL2;B5SJ
zHPjNZz~pO5A-L6t9-m9Dagux(H+L8WA2Mjd7HC6|+I0Y_GgbgFqcC+_P+jr|3C!p-
zz|x76)ho_91~NGOpTjCss2+aB3cvIFJ4ARt;TX`XUUr{X1%dn`+vBAcS8pP8PCQu#
z+lIAEZEt|!iHsv`rPIQ=%Y{LT`IRL)7FPfAl82>j+9z9<0&
zmcmk!r#Ch}49`W6TNKs1TB13qm>XqeekV!eoYA*Tv9XM#{S|w293OENPZXpp%|uwG
z%P~7@rVyk7E1edeNC`VWKL=S#@cc^Qlp!{T;MJI0=D4o+WQuF9uttTVtXXk#F^7-E
zGX0Pa+#5A)V^+vSWu;5*HLg;=S0s|7t1uj`p-G6Qprk|vY~)fTA{AN+Dg&%_&=e{M
zL7c7?i#+C3fZ*^X*LQGpop`3yv3t?{R!uuWw$XrMYAl2xTb;yfF-w^oqP>mGlbeu{
zax4V8_6|`sQ}Hf52p2t0Rq6B>T%6ErucE;M8^eMM{-4pCon7U&GUr>I5OgvtIqe
zA2Z5i&9PN2E3}q$P(kL{e6Dykll`MiLd2ojB|yax&~CIk`T<7;)A2ib4l5nRmbXew
z>zay*fZUb(ReM)cWR58M1F_tlA%F)M6$eX&wr11X_#GtF)*WDuDXT*OyFq}op_q{k
z5rZ0=7}UjsSgMHEw*|`CG-{p9xwCIo#Y%OVscFx{0Xqn>p!Wd8assmPbjvb1rqJF4
z4sjuIf1<|2IpgTY%*u2N4pW&*^r|Wbocy1$#}5LFaF8%W?@{hD>>L`~fWS8~$#L!l
z1?b6R=^(6$RVJT8H0ei@m|XR>4W3{EL(CZatht3DBoBF)4#Z+_Z|XF@4U>b7GI{GT
z=dlx7A!V%C@mO>7_BwHK6Z+gB^k$eWnEu@%T7zmamnQ41^mmbb(GCeNL|r&}6v`S$
z{K@@b0~-}6o(KLtVPfd?_xgJCfSEi9C#i#GYXHE@KOD+0Cx)^TMc}I3-4Wf$L1ffu
zYtW-ee|*B}&+AIoMbyzt$wW2w;;2%!t}zGDm&jDSOU~&9q^cKKmXO%-i-G0A9DIn^
zOw>Qx;8b}M0&oUBxNdH|-Qdjvy6?UCcDeJ&K~6P6uBY&Y!epjBAW8Z<6)`tKwjYx?
z8P}s3c~-IIu8KJDcZXb5u{L?fPg{PWkx!A$hNS!>g2J&g1b8=JTbxgxgrYg@p~F>K
zNDwjI?2u;CWV)bWU1q?guz~U9s5c$Y0SAUL($pMK5@Sa}rNkC&`f&gN?>mlA;ah53
zwQ$NQG~an->MbXjCj-CCT1Cz3tRAWf&rQt~q`tyTx-=*WrwXW)VEo<9s48#mEQx)9
z2&*!dH29Lm{;F^JiHq{)D4FO+Sg3J(E>gDh;WyXg#q-tHt((Z+#j{W#;oD2k&B*=r
z*@v)9*vmWWL%!hG^rXPDy{Tito$F$GyRC&EM}NbP?1JwM`oefQkihyG(Y47Z%4dTf
zZ&GDliPJA5jVW%a>>`X!>y`q3_PHOb-`4sA`EI@N^8cvvqf65neQG_gW2oHGn|0Q#
zLveoRljP=XHzw=ATinfTzTV11k;9Qto9rQ%b5G52{4{4I;PlAxLo%{wCE2d7V(nbF
z{M_y3JV(n{!)FG+#a#9i`IQX6JKEvA@c~lsvZFkfb|xuu!?w|Bf&D_)&kOUyY^miW
zzXNu8X@0+E@jUGVB$s%i&E9*Nxfuv^xqlmo3h^C`)a=J?de_
zr1U*zA=g3E_sN}=+*ddo1xj!6Ip(|9JNsh?2XfP$_sYmuYvxSShLuwTRoeqb6mj3GKH~5u_+x`&kI&ZqW
zjaBNc*O%0)6_&REHsZjaHJ_tvwJ&bU^hQVmrK^`~EzYH+IuzCx4+4~jg$Vsba_&Sx(&p`2MEnP
z$b~#5Da5njPYy%|kfIJab_a5qb}@Ae;4mDgJv%pg>O^OCeylZrZJ;_zCEqS13sim<
znw73ySTv;l_GLBXoIT~$DZ|JpTkObEsrIJPC}}=HN;fcE(5uEPQn~T9-C&~bY1p}E
ze>wG#tnQnJVQ02vxykzX^j^hZJY>U5ry9cT4l6I{wWCXX?nc@Mm;AK>VJLozBAcU4
zd}vWEQ^C9re4NueNlrwEb@|G*hr@d>)77rM)jZzp!}~uzc1!H~{iuI339x8?clc;`
z)BLuKCl`4Yt=EFuS(NXErzQfEx6eOXx>@=w%9ZzZ+w{*WvjyM
z+t(lVVU*ujoqaC_s-!p1HylKy-1PUzZTYnJ>}$U%L%%tAjrsQNt7!SkH?MaeLI|GO
z1&oYpe6>%_!XAm;x;}P^EY6+jZ?l)!*DbZuUS$|Qzj~ytZV6B>#5pTx6f2|iu8uvI
zX*E`(j8!W}IDwI=AeS
z@00G|^zM4ys;m90jZfKci`kdZ134HdQ3uyL{+Av&#>D)R7
zK5;AObt0UXdYh*S=Q9EOv5hKh?5E)`s$w#AA}lYXYsGrNvmgA2Wh8gfKL#d^w@gi1
zhDhSm5rKR>Y^Q0DXDR&uSY`f)=rn)HiBt_hSUG;I-w)8#J4eY*ooIlo`<%fKk!!(tF7MND
z`j7fE)PbE32wqO#|C-cWt5?dyk1hsBN)9s6B1=!4a_m<#>{R!#9sLg>k|r#
zip(CL=UpfEd0VS|mVt@!Oz(|g8Ox^#aPpNBSXXk#GK@Nr(HPU
zI~7!_0~UcbuE6H}TW1DSB`8aL$4#Sg7#cphuj`IfxoR_LHdiY}*VwYD%3RZ^9v03?!Zk6I4!DJ?knt`k_PbA~I
zoQ?~xh>;9gPP7>GB7svtDfUF_m1BZKdb?e7yu7@H>+kj4>W(z;Co~F(dunlnh>GmI
zJY4{Q-Osy+&g2P`sGHK>~b#*sG5KS`b1Nu34bAn*s?m^7&Z>nyf$QfpP5
zLLl1pVo@+dJ<4~y3IusIx}9vto}rBwgTz_53Z#|yKgaEGHCS4OKhn|Q*~S6oLvFl)
zsN#pa--rh>?AOH^#k>BQ4@}?14iJk;YeuG_5tMaY#hRiYl=fEb`FTbP$5L@scsJ%^
zk!)ljurhHbeSugu>+Vbl2EgF?hn_x{jVZJ6x7^Jox1C_>RdInhL73DaVXE?Pp%b4>
zLEd4RCRtX?!)eGWdngBRKRbJE`}7G@+IDv~4&^|Pmshy@pL?Ul{5T`^j1UQR83~H{oLW}oD
zuOXRF`NxnzHZKnfyJk|(VqCIjmJAU#JbL2@^Sc8X{$xmX3*S@5sJ{qstP>?CV=xuJ
zKS_TerlP{Ip?_-Bi+viDkff++pD90NFjW~eZbsV;Mv-e`EhN)Z*g3u)9F+0&yvylj
zv}G0OYjUYX=g2spg1=^x7=Q^JFlyEwr^|S-k0)oINd>f
zNQeg`a1S-}Pz5jmLEgH?=&F4s?P7MpHb=6dL1~7>@x$t>`kiis7z}6g%4MV7cJO^lc(Qjry}GFM*nPl`&DJ
zriQgEn!0{OUn3nMgWP!Q
zJfi5s*wp3LV^>eSr|1hX@cQC8`=0VSHxOOa`w6Lm^TshsEdb)ahOhdZXkJn+_5LMI
z3J?(X*;xr;^Bqn+2lRuuVqK!kt$FuGV)zkse^1foA01SwyEshLfBf-$Q5N7@dMzbd
zbp*xH^q`+P<%Qre%qpaQ0|H8*Dd#q_Xl1Vk>vPki@
z@%PYI?e_k?OwYXK;b?(QK+iXmww(CyX6#k&Ekyo|LtXvLc=F#!Dn0y-TUcmD*|3C?
zVX_@!qG0$a!>l8Up)U>%<95KGm>>H-AHQ{+omqZ}N{@b5WT0~?$gU`w6|^Tw^E@(J
z8*r)@y=Cg{t!j2fdu8U2+39sjm<(YbhQ*b@jK)cY*H3G%t9s=6yJ6ecCV9)O(T;L<
z>_^}~vx2y?(u{Yc^oOSD5Da@|vRYUaM#28`;Y5XP|;dBHB14KXUodJ@nfs
zx~O6wRhC@WlWVcu3iUFn1L;rwq?!BTBo>pzj@W0HpUi!lj)uOve|2bw*_9-bhF2Oy
zf$AEAn?sVa(Ki#1d7;-^GAQ+Ww@p3U(iC_MMl%{E=_hu6RL;u@zd0RXU$E$obH$35
z7p61gZFBij(0Z6+b(UOwW;hIQ*R*d1BikGry_zR{9)I!2`$v9*@P&MO?ph6g?@qNs
z9_?$V^vHifu8H_dCihmM3$sJ8PQadS%x>*ehSMN5pzgz|4GZSAKf~BrTg?P2|Mwbg
zG~cER(#6998P)3nkvPL+hLP1usC_1iEfTyT2=4wTbl&lna%)Fg5FlGyv6g)XQSqUmBUuuWF^pw1A4uD=a9=Iv<42?32{`U4Z>;(9j0!G(p_e1+Ma|4^
zcDtm>uGV_a?XX9;pFult!q;0$D2)h0VTk_G({*#1c$J&geKFw?>H^OBLc4h#x9jd#
z!pm8f*^+@m10!kS_%#rYf2)3myS
z*7+D|ci&<6i%%1KPfPwBAYu@>aF|SGhOceN$85-js~5|RG>F@M(LJxPy_Rwp@wmce
z7I|4tg}ViZzlST$x`a77x^5W)tXNF`SWfjTX-jM1(f4T|CRXF5XyK`?`3mOg
zz$Bq*+2c2A$9G-_7ENtzrXhe}oU7Zs#axYOg;mB`-F%FzFN?Pbpv21l>OQ3_ClV(<
znb)t@?lsQpu9tPWcMX@{>
zmZ}k3UW#fTxec#PFlc&rbJsurLO_G*A?i_ND?1XXSrVvb^vn>5^Xa3>_8ao{#S3Zg
z+pjm2QQ~{#H!5Biqkx@JTF9oXyMcQ+cM@tw@F&)ygQdQp;y;Zv8ZcgquLIOMhUh>F
zT%^dV#kGRz>R04tw$=EK2$ru{>$;nrQ8k9h>PPLf+g>m3W{o0mB*xr#mcQDNZEI`S
zJd9UI;TjNoYR@cCL~%+xbSWG|dzT8UDDj0n^_i@D2%ayqgBZGS_}7{X`GOm(&zKC@
zmq$o1wQC3sKdR20y_Kf-{i4bvXEAbK;4{)_-;qvTa4$$OMCILM?^!b2pM23GczqYu
zN}2CDm60wz#cuEC5aREKa-^^Ayr=m$oYJ>eJM@q8>MjI
zJkUh$ippumpvDeZ=d|(v$ahQX)|uX;!FTIp*v?EoA&;pT?MnK$Gf!t{R4N6Ia)+Df
zi^g1VG%}zq15-jc*0cO-&L!#jK&AV2Woqw>w`ncDej4Ieg5+C+pXP(1)7;8#J*$&#FQfb2y~w&C1xvfY*QKOpZ{3(
z6eLiJG*Nvs5vDKV8dw;eaB36o1Er`l#xK&_>kPGNFyA07pcB;a=c>4QdPdUq3KOPW
z$8yL9naoHCl-IL5ev@rC2Q#!vPnVB^G>1#|A(#?aca8wS)JHBli<~LX4EJDLM1E*V
zaUl$UF4^y+G_L{(er}FIzYKjihnirdUm3qf1Li*508_RAzfa!z4Z%?OhqKMJiM9)Q
zE2@l5a#TDs#zF1_HYmO~JAT7hTV1lBL}PjMi3KCOoY>Gsgg@-kwJ}j+sMcg0Sbf%6
z=SGoHa!v@Liv2;XN{%m{BaTiXoElR4Uaavw9}%lc$mj8pUFeE|l^2uO-H=eM>#PWKiq1ms$a;jgXoAAGj$W^ndJLz_(ziR
z;W(m$8k&+udmmgV!)7ThON5Igjyot{X}(vD;2s>J=9eX?R)0=IG~RyoOZb*Y-OuRS
zXVD%6$f2Ncx^qGv4sl`9_#JZii#UV0+@=564axY={U5l%*J>;MlkgChy*Ld%F&s(E
zC$iA6kX_jHU3=y2<_BRh!d`9^OUTgPFW>@|3L2_BGf^ZOafU(-V_Do!O=`1<#Ta!A
zc_iVft((XMO383nvfh5i((UVGRHSWlhW+maO-S(=(Ofw+)<~S@W82h-7WnvLG@b?X
zXujR5zmqU-$Y^DT;gbIuEKqOAe1CUDPMJWmm;u^H+|)NggRztpqT8HCRG@th>3rjU
z>D08JVK$jgo^RU&{LO9D{p8ZbIi}GKK-QmO>iF$2swAql@?b9_YHt*tDO0bfTee;a
zm?Xl(s(WReQ7`0x>w|FT(9JK@IoIf`v`{6OvGFL8QugW(IOzeG^^{r0QBGdH!7#cA
zI;n$LQ>0zE@<>+{0+;9SFhr<^LNX)P-RJ;nG8a*VcOHkq`+rV5lxw?8mJ^g%vk>ng
zP6K1Z(E}7PpL$od79SB6lUzFbw#`*3YwZCh*M5o_ron;Np_4U+&?Q}%ceDVnBCtI6
zMqPe~(KS)tsyvO38;qU|s1GYb)MQy7Z~kM$R8cy}x~g$8Jm>u@E+mtxe^{8?lug(A
zYm%!2*QKQhR!d0L#C!6feYlg<8j{wP?g3O?@=~P|wyQxJDpbfUt{Po=#7?0O;zs|gE=4|hM&NcBCS)<9GY0-2reCV6C=g|YI%n*N~Ey6scNuu
zW~%9)w0UX0Jka$(of&RYNos!()5$x>nu%*coiQ$RAr?Ui)_a$JL9AOZ{ITRD4=xcU
zW60E=!`fb)A5Ln}g+g*nlQs-Bnl>^GnDGtBSc@lata_A+ZpYoNT2DOIN9RH#h?df?
zM$(sEDduuZ_uE|u!X{dfhBzojfs&BmbVpo@M>xr!Kzlwcw9iotoYn>KFiZbnMbu3p
z3pxQNDY=nAM3wccfe7ORK`oA3(>9&7X|QmNS}JzL1GJh{J2e{X#FQ1V0A8qbcs<;t
zm*4ZzVNQXo^PFuzCsi5oG@s_?CT9tq08+
zN-oK|QQhb)l882TXTleg_hxi3)JQMY)xl%z_XAo-JnU8}YQjqIfd&1_ktWlk_m4ei
z<#V|cb6;|hg$>@nXLZt~gUi4vQ>WIv%ErpSB>x0U|JJG|c%Rwmh%Q;d+76iOt|aGvGBZ
z&Y`^!L>bU4`)k(2pfQ)IE1unV$g2Jv#O*^|*dDh$t0v|7iN>eU;}5Mk+ra7fNjuHC
z4%l3$f=!dYJPT}Ys37MQFblPv1~a0RC*M3jo;`c@sp2rF`}_F0v&HKwUXO~
zR<~_tx$J(wh|LOqE_6iu78z~RNLBhGkWeV^nLu|ZsIziDv{z4<)pnCiv76ic{KFm|?V1OX_jm{Lk=dH$;(GN03-
z&_wC35BX0rp!#7kjC9aiXfukuL*wFh$qg@sdvJFCyg`sg*BEVBtsRW
zakZJU((<#d{ZwyF#ZTS0n9niI91J+AEYiiI`@F%aG6y=oQgGsIE{1pIvENWM@V}m#
zEFFq7A|&>L<1c1pN_4*NEEWZ54w&1)9R<4~OZ5?t5M|mn`2)?sMOts+zv|^y6+8<4
z{WNRT_O=e>cx}(H?c9o>U-J6S<3@?CwubO@F^0t@8mq)3)XPtT)DmS!5cI2PlV}xX
zVq|17tnhpBr=Wko-oB<+wZga#bdz)vlc}&xV5sGDm73jP99agT@-RgX4NWCmuPn<9
zp-iEJ_6`9QSysnNe6z_*j8GM61RX~N0d0j$A2eJK
zL47cxn?L_*uH_DlEmkwMghLS#>#EW!8h3wk9y>J*2blTy-I{*7Xq!{`lRT-6r6-`Dy#DI<2Hb)fQ`U~%n0#<_J;Zp
zykUeK^Pmz&jZRjs&vY?Ggwkr^&fw2nTrpa$x?m{*-qv-w?gI*c5N6uZTp1b>Ef#Q$
zXXG{CWU?^q6$4W2^{P@cLyjkWsC#i
z5~)+BHyLz=qqrDRm+`BRaKw^(t6P9N;Z;EI+$ZvruwaCoy?~4X>e1D_6^)(W1s>L)
zb-(bV0|-)93fg-G4vGd*%T0o8UFAdJbF7IFl3kmwiax)`oyW5g=IPhRNNzC4qY=aJ
z4+`aLC_s@k30joFM_fm*F@NTz@2?)})W+9kj&I-)U`W*R(hMR_xskE{+9_whM{mhXp_EmybTS8u4Do;#pnk^&;mo7h~q&8+3Ef-%CT|ek)4wV)4B&HoE
zm#nHVbaTV?ehv{9OC3ifLp?@p3Hl4n*l}wg5wL<;GX4bGIlFVoYQl^635W3qf8Q5~
zs484UjK?|mV4^MurNP~h72)hXC^5!Rigbn^InC5mZ*fwO=5}Kz!B63
zLX)v*@KrdL0~+WtOHq7;p&dmjA-c>}EGS`9TLBUIZ@(4&yaOZES-O4w`Xg;5Y+t-;
zQ}fu-VLZ1vtj6$V7JWCru-&zy%u8~pbP}Zi*g+o-4#1>+jKo9CmNjc_l^R10tRKn8qN_9?-%`o
zpAe$7ljk*4I;2!Y|E{j0Vp^I>Q9{R5MdvQM46VLb*JMl#m1#ys%ZRTSX&5ZXS#h9I
zU7S^Pzj<&c$1ka>#Gy(5ZaBLGce?hFXI!=jm?58$q$^}ZAh~eg{p3RDeZ
ziPt%FN+U&HXNWM!JH95|+S_{33&aS#<_m}q+{5bbw;6T%`peCIcz?j8@&~Q3=@-(Q
z{^PPdhYum=Y9Nw!nTUIz~w}t@u%3$
zJ=Q5jdO^m0N9QuC%i5CV>c$#)eyek-#rQz`D|UTqDDXZ3@LUJ?3|zvmb2R{HLUMN`
z5!@Dk8DsFbpA{RtF!o$55pdgYqqm5?Xu)}H+wT~Adq{6~suSvW4H}{fLwgZw?J>2k
zSAI%dpV}JrQ%}$GhqU~daKHU4=`@R#nOdCkO5(AX&f2Z1*G>Q9_?^w3p8jthhn0kO
z+8SAV$Fw}Qqx&rS@uV&f`o|0Qy;!}{VG0^&L5(a29gO=z`=jveF_wMxb|_CP_3Mms
z!Tq?rWdfX0xbX3?&;Dp}>B3b3`Oz^IV|~`XzN38q=IqwR+!z*W*ud*=Is5}?
zq8Xu8XH}_H0+~{EZ<`D3bAEJ-0(HAf#}4h*Lc-mNoym7D@`%3R>Yqy%4^LKW%C-3n
zz|o>=7vGW2Rg&HIf_$telJ=ck%8Rq36A#tsLN<0!Dx6Q%i>0S+t_dD31>DC;QR~km
zUWzBu^oO+yCwQba+HCLEH*%NaK7K{w;~~1D$Ra4E1sGgm>L{f`Qo{ZH
z1Kz%Ui~EPS7@Jz6nL&mi)tXhf0o9CSR1EC
z+6v`OPK=?E8Fj9h=Lw%ae4tVmr8>o`=U
zX_~-8h71G1z!zV9f$@Bghr4@l9%!0pl&PX1uuNfFyv!4oQa~K)lH)jH9PgTfT#ahkA%|`P1JhLT{kPxX
z@$q9M>fCXeCYUPnX=nlDidq)H4MY*R8-}p)1`;S|5>BYKV45b(^8!=DDV;E!?s2|*
zz{A742=+A@216xXDvXU%8X(kkAQ?z35r9YuRtwxJP4hGU{7?TJpFVxUIF2}wazHIfQd2W0Sd!1UGVASCm5K{
zr#k>q`R`hwYDkhipU=n=>W)bmmuaG581V4s4esvV;{M$`Ff*Q>FQlFjYO|@$-v+ZK
zc&Tl!N(uD#e8ST*;hSIm3XdN?keaoCWGEU4Gh~P$r308ApHNhxrqE@9yCaVyiAan&
zHKfyk^Dv++jxs4N^#TUr{>=lv{K?Pp`R88(OqeeP&+`-Myr32(N`OcNFij149FT_*
z(2ARUIiO5HZ{%xxgeat*EMSRg}{1
zJ0;vdyv5z!J-vDJ4sYJRffdHnJi$!cBA0L|4u+NrwHd+@G_SSb@$nHqeE;31vXXN~
z&dG_`i3tq$oCi3Eib}j=he%UrP;UtVhRE2G4I0F6Nq~S{o!-9r45x<^PQ#f?F_coE
zTDL&EVSVNVVYXHQ?FRQ{n)Gsc_G!8}T#d}!S)BmW68ar#>P^YRRtxmV;tIHB@WY;7
z7>1b7;8d$dwu%!{KJlA(@96E@FL)S720+U^vzf6Zp;`+UEf67EN)h2qZ{NJbcs`K<
zr22uT$B+2+pZ^NeOoH*daxYNctquvJ6O_p~QB7&#AcGdw*#A?1wIFkmT@KRtcK
z$HyQ1a{1(57Z4kq)d52SxzN!a}QE*5gz~OG~+z}ccrWFPz7NKb>G))sEC7ezt
ze)sw3`1+?`)0bcWoJwVSe0oNiN{~(ghDN~%WhRCIIqsP_`s{R>@!hw-GOr5&^?I58
z!w(8HxEc@Kq-pn=VzE!+}*tar$nEB@fCjh
zvtQ7guRg=`hnb$AFOV##bHUT{g!|Jye)9R(nCBTkeE5!-f&2S67*7M9pB`c55l>G)
z;M;G$#fJ|cU|Rj*&0Ehoqt=RLS==2iOjwo)wN|7gV9AkKzBzv@oNB44RWZ#oS9835
z`x*W9Kl8-MeU{U=|3r8%8#UKG#sBh1;C`GRVO;e5hpU;YB)yLXsz!PkHId-$LI`~Mz(
z@x_;TE;Z&X;q`PIY9WM;h;US=IBIlOb27J$@D++CamdWfn<9$4Q5Fg14|go8sOliz
z&n)VZ_*xI1t5Zd&LH9BV=KO
z*$L!oMh+Oa_fuQLhkB4ZZ$vzAN*?T?thJJ89S8T?Roc*r;E4%D>{G37?#>Q!b8~_v
zVrPOAkqMJEQwUQxQ-{T(1g|hJ?%+*ZO^_r-vMwix14}D}+rx#7kr_s-GLK_X+el-a
zfMk)h+%qc3Z2l2>O)i~aXNR9&;vHd>g1KQ4;L?Opg
z)KT4$7zhP*!XVq=j(7@lI8n5yQjpFJsSyOFkr-FCqiVXTIB6pQrh{Tz6QFxly}=B~
zZR}UmtvzN{R1e31_1RoL87a*
zZu6UfK*FJHWzkQ_35^yOmZ?qM%r)k5HHYMgG+K>drZVtm$ap)9AOfaZF)d1$S~vT3
z=&lf{k!geppz4@Cl-Z>9^~Dt{7h$0aIN_dx1O^7o30VMcvOQ{!xoWI4=1AB{NJDIZ
zn~(&!J;+DA~_*95^PGb)SkzD{_O@-Ji#1pkrABcB6M+&U#!+KX
zopPKTs)AraC`ck;2c9j6OIZ>IMpNmE8FMa*T2~5`Zpr*ak@Gm`0i0T{MGdn7Q#I(K
zm~{d*Wj+X_R?t*tygQ$e5&;#Mmx|d9Vk=3xV%7yo6Ncdg5TG@_nWRO`G{!Yk6f?6#
zJV8-mOF^lGoE(-J*%Dad+N!n|MH5Q`P*IkO;)pqb7)3qktWA|qi-J>(hsI8gg;EJi
ziMWhvRgz~T!Td$PXR)#zm2pHpV4$?=CS-UJ1b&2?jA;y#zC9evFL6?X*
z$OxR$0LnRz2+gpeUSe=WF=GJqlB>d<=Rx?`)RaZYAnOeq5Fsu;&JYMlW!3@L*kn3rkGjfpTg
zCk#mdPtaw;qDp9F=5YG3Py$`*A@8cVJB<+oYy_hgp90meJvxsg=6Q)e)XrXGlExxt
zh@g
z9MmxkBPxLD@d5`ho&{MlbSaqX9OTa7j5H(!OK?>}br1HWQ2uiK=JY8VbaT*iGVcgk7upqOxrCm4$$-FLL
z0OvGDJRHFD6ygLdK%!8}GXUPm+gSt1gw}X&K&~zN&%ot>dhzPGNC2KL~
zHl2W=PzWSQ`=x+}0n%bf!;m9JwT>o_@GgO&OUy~9oUoLNWi5&-in1smjew0%FJ&W;
zFi95FvTWo-YQ!=#Y9u;O847YS9sRbgv-PS>hEAmi8Ilr-1o2q_kVn5VXmh|~P$twxQHq1x8Yx4Dv%qv|{Yc=&P;>#*
zk%s|8mR+(FF$P%}gdt`%Rn(TD1;7~ZqBy%uGg+;1
z#x@|`4X`;x4~RodWNhQFUP?ICiGWikpa7INh3TkxXzHeI4zNhPL~HXQTGmM5O&=rH
z0f~~*EZhk6(#{K!g@Z{roRrKeu&SX(BaluC!njY(EZ~75B9u6ROU3d$!7E{W
zcLIh?%Ur@$aGE2&ngnh_S{yLJ>3oKqN5C^+0}KKdCSpgn_>QR*ln)EWOh_nLK3<5I
z84p9jAN}G>{Ez?cAK~x)@h@5=mYhNsMSa|
zN1LOHDjjM<+i=|os3AV>%0xy)N)(z3v~wI*ib1=kZ>p`d6;rOHjP|pg&*F|fmV`rr
z@Tw4t8=|elan4;~wc}quq<_&jKmh)20FSzFDjkGR6TqhdBgZsSt0FPrh)p0j#YBUH
zeCK;cRb_R522E4
z#RE4#5(J}6j}KK2ErH@|MYQlwn*=>IC4buN()?Pj^`P3h_PtFZGpsANYG+!5ucd7;
z!M?F+SIK;9N)NF~byCMh9N+D>qI%cc!F(knuZ+**wqXsXYO^kA1X;4x{I9Xx6T>M6
zYPfSJKsZ8CZiGpzPg>W03Sl6DJSx!5iy4H(naHA8D&~r{U#q!m^h0Y7N^v6Mw#hO}
zia0C+;HC(g;WRz@QBfutE5Ye)$($Wv8mffj=>+R;q0r{|ujh^)>Fs6P}(Pu`DHmYALsp!BFKy0wiTJW0dKFQWhi{U~c&KH{W70*&ck~~I0T8+HT_lqu#05%}!jAa7;;1A#6-RD20=jRK&E)*IQjKnGKFLp&B1IFP5
z9QDpc>0KspB{0!Eco#0375;qP{;!zr9_DZ?m&U=WD5_q)ZsK@7)KB>QX@ot
zeE$*8&rc+YXgr@W<}=QB4|x3ejB|d#&wla;^#0=`E>Djr^QL+WrV%11FptCxaHLBGAqWIScqSpm4?G`}dfiFIX^^Z5+8g&L^pZg)ew
zat>HXI6+H^#Kops-N*=yK%Y~Bu;AhCJ9_iwj4!@Q$Zy^@g`!o7AR^h4Gs^q~GhjU5
zBd$Ngu;9B-&!~0AcfWa$_uqX>m*;0_txiOtvKex0kt~x40+w2X$R8Fp&15BIRjnC1^~2#^O5B4L|zhPA5v2r?ytB#aVm^4QXS7p;}j5D^cB97An3Ijb7L`TRid-hP2Mf9rGn?5BSX
zPfr&-fBS2&0g@A#k`uTQk18-2OtZ5%%quRB7dRg2{N@cFKYql=k3XQ+>LBu!LA
zVZkyNeEHSS=;y!qIi8-L>FMc-m&+349f{`I;1;Uqk`f-?ym0_n%Hl;sVVD4$o}cjD
zZ+=B(nJA^?DJRdFK@Kk^f|^^=BWNpRAr8|xUoGp_-9HhPvd}P&(1!=gd8G7vC*+iI
znP!f02!@Oh7!@l}HzcI6uFnaQ8CHODsi@QJS`~lsXMcuI-+k*ES$c0=t5_`CW-wd;
z*T_MuVRPGvaUXv80AfK|W|UF@2kzcH^8Ni=ynXjMefjk-kjFC~-~R=Trx8^vrezM*
z3Ko>P?4s-lb*%Ax2F&sJ=@UME_=w+p^DVyr?mIYuZ-4!*6H8N}pil@!C^@X=o~)~!(5XYBuvwAqQ|ETpYsW)(@3B66H-pZ6QH${am*c;%Y<5HPgxwso+MdR
z5VE@&rpshMy#GPVJgK><5F0zIyQv`tm18Yn<4VknnN>F{;ehE2oEDHR04?M)gLoOo
zQ+@mHb9=adXJA${c9y};BXB;S{fCdA@K~O3et3g?x_2Pddd9oA_~ke6>3{d1{O9Xb`OiA!~{u}v>>
zEmOmA$^a*5sfaEYmZQu-vD%Wmg1UraSCA=)gr%K72rz@LI=Tl959RtZegK|#mQBH91H2?Qc))ZpBRz|Cos}E
z!7UgpWuDt}t>m&c|FQtALEJ#vp4m8v#$nYKMg%T`FivECLw>X&{IU@hn9#
zPZRXAK#K$UK*DY@3u+RXwJ5BVXcOkJebrE}Pv;Tic?1j_DaTCX%zsW`&fy@DLaj|4
zSe6R40*A&LrV1m4un_S8q^5S<2*GX^eXkXJ7#wMoE#AS*EjGB4zS`egoM*iem?;r}
z+{j@Bx90w4fZ7t}^&uq%PC}HVDed|0g256g=yp$Qus=v?2C#uRHAVXZG7iqkN;ot}
zxlAAfq}>m36fmFe?;%2X{J2mpPw@If5CKw(0?{#}%+FCEtwDCG7loV&JPa+y1Yl9f
zsTG5^$wX^A>sEy(BTkGY2|14#67X>b=2C*RGbwBcm9ilXk>0C7ofXw9hzuzP6O@%A
zL>q?mJhc2p0?JzDAyG`rt5cvR011~YAy1$!`C^PT3=j#T>3K{TMPiTH2v5?8_90XP
zVm7-&2BHhQ5+cLsz@m{J@@F-Y7w(A
z0Zt+~=P`;ttwhm6*e6H4w$b7SiFjL`3lzXG4qIXp0E#Nk@)^c)#HqfS(Y8Y@v
zsui3P&ZjZR!CE1$7<5%LRx@N4OkN?vxC2m+v0|c7kaWV+r>7|1W?)DOInHhy^-NCKw&rqB{s7KKo&*zWi7tMTxJw4$cZp!0jODjSEo`eLOw(rIW%#o
z2xb{j;V54fBodfw5IX^2sQ@v?At9#}>XI4+=7U=e@j;=;Kuy846$7`t%Bq&_Ybd2v
z)2O#Xv*t_S?y${2C1jH1?jZ^fByD?lvjaD;_2o#}8^nwZz{0@Lu5~({4$3(RlES9G
zEEVboBOo(VPJ&T@w-g1-QDEbnihni5kk*PoqHX`ya=E$f{a78d6_}x2b3myTla;3U
z%4_1D)_7#K0`)bbL^uIBZ<$GK%Ctwv%W7*~+}aMd6)wfRa){Bi``;ZhXj4rMaRLSd
zRMk*aW4-mpzN!Wh!b8qcz!-UsAjdU9)LM5d?I1md`Xsl!W}+y-TQp+At6C#JI7k?7
zXa(fH?SqRt*qzYo8yvvtK<1Q0p;X=qF-#3};egfmC+Cpl~8`At_U_ilPNVj4XolXTVR~qkvoXO6GYfczn7<
z{=fkNShl|iWqq7Q#r+$pKC=iBjJ`OZ!s%jMo!JILxJKUI-x~LYm9AeM2j>;
z44j2R4Z8(x`+NrUPU1NO7p0^GymR6<2
z1iXc`LX1t}K3wdy#lKsY*){T%kw-8J)njSGGaUIFmQ{_ON{xbhHlRc_6ep3e{c3%i
zSg!{sIYS)Fq+JfF#C{1v#8Y=uQ>OPZsFqg5~2gzWDNU{Olz7lb_t<
z-~W?8z%SmNkR+n5vKEi}q4xS+phQ#~DYd#ogW3&aUL9h$LS)-1q|uMagOR%4#OlIfE%d#{6DXLo
z+w<;fs`1lHF(P-IhE7cF=!De2G6;bGxdDIiUmBkN8esJi!`(f`6TsEroL~%y@n*LZ
zl7fvW7TIAk3nFEtk%<6jT~`$%7C~}%F?S&#C+0+i0iZj;?}%{EL??&e5z#=Pfe2%i
z-FXI4B0o6Cyr>!94Nkn>YO^fa<|k~T4`dN7^XfYjKNPsplt-cjq&iST$#A#KZbB7J
zbkSGiatb1Yy}^5`tbtMF?P_
z%mNKdICpC^bCAqPh;hz>(iCSeb48^%SYDQjPqSKD72GL4S9YmZXI2Q$D5!viJ@{hg
z=H^MrD$LE`%xptq&tTO!TUmDVOLePoGj@B(ga7RA-WF)Y!%TfH)vHB9A+s2Re6EH{
zidxMRvva5|c=f2NUBWKN*ZWNf;#oBdLy=X_du77KViOyyBuEepiI7s1Q?7*4#gwXp
z2Lh5X51eRZ;cCuBD=(@@BAl3csm4nc6ctR1^0FwY2{U9>>?H?eF(oV72rELahFS{L
zE$DPYNEF41X&{V}a7xVQAt6N}6Fn{!@1G|+ZoK2yO0ZX;D#LaqP|T?kr3RVf1F(rUY!HHBCBB5}yuHnBKx
z#hWSxgRCl5^EmsDp*QcF10?-)yxVq3V|~Lg_$a+p^zj4*i0uU3-UNIdm2yig=Il=y|JEokUJjJN$022^23MopmP4~-NWfVkK
zAMyPUA3*MSe!4U(c?Xe@T7|U=k*Fl3RZVy!F70Zy(Q%0c<9LGK1)U`2ij+?n(mO1s
zxEN5KQH(Ki5bH`^AW3*kC!{=t-9!qdgnT;V?b|O<=6{4AzJDKtOMoJ275C(8AjNhy
zE8=(u9t|4A_O=(Xs&ID6TYMItz1Ck`0m1dhPTWhwUGleP!%%j3zn5~;4_~8ef9^T>YyRR_}cQ6>{X`*=v#oizeCgfAtnkyU&
zM<1VO#WK%WmKl$a7n&}SxcKp~Bc~5PyvH}c`empK
zdQ$*qM)NQX%cOC5^Si5e
zH$@`K0}aE7A!pPw!E033uZhmncp^y&&rgq0h1`mI#~g&ZR@4tGhFG^L`tId90>uD^
zadaj|DT}LWD8ohId@cNNb=@kcBH<@wwiRel&KcwB46W4x;Jy_dT%Iaef!Qspr35YD
zY@wnA12G3B*BB%TdAx%bMb+X@pB{tANbNw@$Rul6Ws3+k<*`k%uc^dtwb3n!o%4wI
zKYWKYWP0=F9q!L(h-ApXl+;L>SG7!A+c{2E1`%;e>}=*7n@9_y_@r=$*2PTKOcmA|
zi&>0`d>v1|D+!S`qBjtMe0PUxC1znsnTUy!FzY(}YD^MZm61|Y4hPT6Lis$BmW6UY
zaV-;-c>*z0#z?3}rWNPYoqzYuHy%N315?`Vh-fu{AYa$;7UuWGr?##iO9eqBLgqv{
zkNE8KpWyAgFB!;KmW9TACM`gzMq}ni^fszm4@r8sYK2I`X*lDTpZ>9Z_~AX(T2Yr7
zWqP)#y@@@1h+$hBN4tV!Y`}P(yPEnPh&e&s$kYfLP++JR#-mk?<|y{>$v3=#kM6-H(PIt$1oLIb+76~Y;(`*$=w
zMN!T;o}x%-?e}JGY@Ty+5;n!XfBuuNy_7{Smrpv+lS9?qP@$v*H7Bl2WN=h>FYZ`dYLfXpOMG&s*u!*k2$vKjYum@;GCi$Zoc^P>Cy-lMgsV7
ze~;6{TcS+9stf^5sWuDD7*>jNivBh~O>WVT-3`thV+*JTFnm$3%VbE&U@$F;&^PoFM13
zTLtPo!VzJF3)CDHD}i?
zbydxvtRhfJS$P7OzhqFr)|A!gzani=|fhQc=nRzf57{cpjoQ8||!2
z-ii)@Ixj&4Wr1Wu9!3o3ILCQ4SgEnEXAma|m9iS7WNza`jG)yatUwY_5|k-2+~X;O
zh>^z>dq-oa0zAz@N^F+SF|HW8RLH;>PK_XWDWR_Co01!?_R~41aJ5=xCecW8NuaZZ
z5}_#)r%=3EEBqr)1IZFe-MN)_kmWS$^x59;$oWKJiQ-U_GlL)|8oA*jfs3w6g3W5?3
z46WfF5_=;Cn*k`$8sio#L9;d!9Mf>%0D%+ZH0EZttH7dg4#lYyUhAmE*S%nnc-&D-
z3xv)UoD(re0+b}w_Xq+m9^`tQLMd=ulj31>RI0+IC4-spsDMAOTZbTuzE
z^R%F`pa5drw*s$qPkSq|(FB*UvmQfnF>xrL88nLOg-{HeQDifbYQJMhW{6W*ldHn2
z!HZ#N#gVJpFN@%`%4jr2)Ok@PA;=hnj-e&ROS6eBOWmBr(9|GV74xE)+Pp2N1c2yH
z5^`otwE}K1D3)mk1UTQFFeV8V)MDVoFc@?Rwm=lR1vxF0;3^clpSgDl2$(rC67rDZ
z99li(hB%f*_jsSNUI-16A{XJ&uLTTVNzfkV?XtUEwej7EI}!<+aQq4DWmiQW7$QV-
zoi`igaI}$a+h|qS7mT8zUQcd#IKRc|bV8Qck6Eq3Pba~p&PXC48Zo96XDF(fMSq61K*Pvl
z(+!0~B|}({2a2NK#$hSiETcEO;)rJ#b#P)VU`)$`;r@)NhV8GW3}pZnq=XbF
zi8;q-t-X8lb*jC)qqmG?Qk`B$-&CRH)CbK
z6sHOU8DVKlf2Mg&>Ir{Yjx}Fa(YzW`Vj?HhC208T&*^7OT5I2^9ix{ymI29(+%;+i
z7EDW}^P+fhcYw2XLMp?WLnOq*2E%?=Xad9Lg_ctVhJF2COH8HA`3KMFWWlB^eVd4
zdjLu(ETj{VIHA#hP`JYd{wO^6tvG5WSbFi<8!LW$XM`^lFWhY!)p9V&JA4GXH(
z*mP3bsEl2^vW8eQI(4$w(bPqme4(Jagg7%26g(o73mki5?3n04z#fD>g9e15s|2GO
zWhKvFRiV`FRNLxw0Y=b;irBHtQI+`Gh}6vn10=X>_z|ebV7nkfY$Zgh-aO8BVZ7;N
zPSEut6|;v(2LrpisF{G`JmL;@P+*3i?8I5fBuEM@>_nOTUHkS;_EN?
zX;C5rHO@q(K!yS}kTb!IINVJJ1E`%9%dw%{hC6YYLQoL^Dd`R58IU-1_mNkx
z9py^^lUwWUo~GVxaU`}>*vD}+%HpK1EaDKTKnzS~>IM;mX`}#IHC1=3Rkf*`HV4CO
zQRgBqlD$@iaL`|@moUCmIKxYlaQO!p6m_1V=P4pl_6N^7ySCb6P1%VA?iKA+;}(cK
zAhfmsDUqas+yHBp0FbaSrxYAr6M}&q#@?LKj2uP=W#K_G-@)brJsURzxe1dcfSD|^
z1L2F4H)Se`Qpw=#K@8V$D6)9S`_#ym#`UzI)dsg3rF1D|77Z6qLNJg>hNm+d9spk8
zW?^7wBcQ^J2%IRD5u68b$sEmYgbNFqFyFGZ0oIf#B~VFh4Md0`0&)dZ$r?yaFKUkt
zJzW7W)MKZ6?}EZP-@ta}X`ZM}XGr4iyqh6~kp?14Gf~=()Io}{iC~7Do`LK(;s&Br
zWkB3b!Z~YzwFRb5oCRERl(i{_ick<`a<5Kqae6d3BxSfMS~F5JIPb!TvnbpMDGjJ^
zj#T*z=bAtgs2jM*eFo=Q<3#3&{6)*`tZY~Z9mz+BmA7&HwzilZG3l*xm
zEK8l|YE!FVRN`dbnra|4&CR@>tNXD!F~Ea>B}88#JV7UAaBuo0q?;W)fG<>bJLFu@
ztYSV-@M;)u_MoBQ`1FKUXXN`A5XyL}6WV!(w*>Fevnz^r6-}Cj@QlEO(qm*h$;)>I
zjWfpk4`Eq?+&9gzGD1>D-VGh1t?-73=&=~Y0U%ox>N945cF$f0EakYc+aklwA-P#<
zk4q-_E=$?-AbZ#4pk@b?yg%IE?moS{8Qa6teqZNN{_N+&{F5J-vQ)XfyBC{{kMG_x
zYQyekPgM;f1@|vLB6p%`I>nr*JJty+O@$$xVkhj4)787McI4OiB$Ob7rW9+-QX6h0
z;dnY>vL36K3aTx5I#1!297eDKb6sF&IMoHye8!@RA_-}?!`+Jy@b2*)=BKBX6docp
z3CAHP=^J*Bb_-Jph`7fv+V+fMRpfZ59QRne(B>o<6wSI$ERs?{Fw9kn)sYILS=187
zjKkp;!oWNoQA&wt*CQ6%YNgA8&^NyKR(Pmh#Izn%M-l1rplC7>3z2iUjv;_ESQ%&t
z@ku)=-P(dvdrXoO%5+b`*EV16VbyB-F{HSYtxW@`wJ*aVJkf+#Cog^3tW|$BW|fFV7`i%7+M$PpH?$iL
zSmfkX0F$)QwB!F$7sOgT%PbL()1&TLxUV-|PL~pdnaa3BDFccWWGN^-AW;IaAeli=
z3r(2dFyfp^tA*HMNRXV-xt%?dR=4>{DHEoQ^O6Sw=83HEj+JVWzRI0^m;Lu-FqN;p^iG
zb#{1L;5|;&+?~m;GIfHK%Kceik529m$r;Q+aR^GZlbS*)C~M6cQO?NwJ$OvORDsNZ
zM!Qy03bCFsR2NihFeEp)fng@*CWgGrK8~ZEr*nu<2?i!}qi!TKIFV5hCS$eEIik5t
zVJ&)5ksT33AxW82$&|}LW!%v?3{-{z3pGBU&$KKvcY+~h54OwsbSCOL5y>NUkdQR1
zp34sV!*e1s9Hxfz|GoHQpz|Y4=umBSS)|!zM%-Tjf&Uxs2
zWi*Dpi~G3?QZK4n5J)0cltCf`0Zb_k$ioQhf>lQ5*!$u*Uxr~7Pm+1-dt=lIA_C7l
z-`9$p-45;k-ly|~^XX^=pyUDOVJKV)iQz>j=auS(pmH$_N-3yyfp8&ahU9`W3@GD(
zp$wRp1#CLxHT%CL)T&%m?&J%(Mzbe;e>?)G;82Vv^v{m1n5@DAf}1?J`{CFeD&jbgn^?%UumkiRixmXyIH5wzh#4Tj_SiI70&(;2LZScHfH
z_SA(PjGU8GcLFlAu;%74M&ZG01*Y>OrfCA+
zJt5!RQr%@tXc(To#K%8)f%8uA28KGHp^%8L%mpbGBuNypz#*zDWhAEPON0Zla}7m0
z1tL7cq7IT6zIbyoZ9Ut?oS|UJNTq;@k=d)$joQv5_LC5`O^@p2
zOkj0H!h)`>1f-IJ0N0FaJx9dNIG_xrizYm1ce-?0wNpf$c2af;N|mZ2mC|c!C3w)J
zgc-{;6Q_hd6RaAfq#$kfNLaoe*!5%+)1X^2he5%$p{aT*0$PmRj9k^736udB_c~2*
z2hwiDIPBay9fd`3)9>-t%%|fCB#b=nESCgfa$TBLYv#4jb~AfU$rxl+tIzZ7uFWV8
z3#R6}8wVf9(MiPWJo~a#bC3V$XA8>5=FH+O;;CdWrFh~L;BD$nH{FPr?&=|eg*!CN
zAF+;@S8ZssxePlmyTL`+Sp>oy(S%}>oRwN6RuLw6?cl{tkdk$~1bHZWooCTiwbXbp6Znyj@*IbjZg6C2*6R>gfo
zXy&jM_dw!^iRXU4>nA?q?$BR6BIkJ}jYQ`SaA23-t2F@!X1m0f$8`u{YwCZ#^`T`V
z2FPK3zSvZ;w4j2G62!))LAeS8;7UFU+5ZOG!_D%cuqMna-dj({^o?-
zeG%1s%aIZg3Ww%g-RP_#%U&~`Qa8jUj`!Q#F?A77(1WPQ?)F&p9uaO7@$KtSx@pjh
zdLB}M0%B9fC_&O3dT)Mm$5dO8j72C3hrmD`hs2m+SWMA0-fRlhUbnl3t1=6X&4u(N)ab
zs?BW8FspB(5h0-T*Yc=_Sq-Vj1V0-y4n;7j;kYzZRirNP9I{~GxPGb*S#co!Cl!hN
zPi+f+?=#}~nVWEYZS#Pz@8|{X|6Sd?peckcrk86~m^a^JVMgxfjm1OU$bR`A>orK-
zAgLaaa`9M%IIKjP*p`}wZuV(#6zb3MhGB|lHxZ%Qnl5@-r_vhP=Fvk+y@y2o{rB%f
z0H{D$zqVqZx-r|jh={LZ=R#Pto}~N&M_7eM9G{*h|mA@)w`ZFgP;c|L9-Awf>!F9kvriy8;<7_)D-jFFysNcPnebp
zZ55>pf2&@S7sJRYSn32-pp?r~%~x%WHOozvu`CUedg_-dHT6v}UQsW5Y{#6%njPoo
z+7zlryaW-{Lgh+}J46koB$QGjK`aDOonT14chW^+J!`C~qPFN|iU^KqeXZ>urt}TX
z6RA2hMeV44A85@XY#_=|BhnV4p*m|Pk#B}&YO}3(=tdcmZr|6*+$=s5rcT-?kcbci
zt}WmZq4kPntJy1=TEtPN>>%%=m>^WF-EO9|QFqs2vh|oq2T-<1^oTjvrkG}>F*8OI
zJWdUDR%FSTe1Ufn<@r1VAlmIRlnm2S(OR5wOOE#;LNW7P94bx<2YF9<0x&H#sJj%V
z0#jh=UBsa3r0_IT7`Lr2n%d&^iiDwaZkMD+uaOuR!j=%ptFA^`0$Go{r-;&41(YMY
z9yQGG+~si04C}xOTUDygTX3g#MG#4Xgt@LK6k-!7ahSFP45;>=sL$3sicY*4)W@?>9@};ca>fBCErL|T?3(`J>u+H_mlqnWE>86<_1br-g
zy+)F#qoBYj_R8&j8llZwKWz&FU#-e84=Q!1qDI23!QH4Ka97l?yAvU&*r&_^tGF)O
z2^{3ya6`$qdJ8Co))v~~=-Xe!ecBT(Qwq{}U4n*;e&4RTG6rGR*h^E2y1cSNs|7`K
zD~I|_n7PN-$7gI7jRxy!1c3FBg$#4UpT3)L$OW@Getw+r(>EuaXS+yG*R#i#&KWc@
zb)%J%ZPw}Dbdi5tEZ}q{6a}ez7w>Ci%*jf2#+K=6u(bpVF>i-;_!LGZ$pYtYe7S_Q
zQozFEu9N74cAi4iu~B4Xue4_X=fkTrNtYxG%MnR&(_6V($<_?(f0efYxci9s*!_PxUP^e6>}m
zPY@=OUNvaz5C!Yh<({6_01$gWpI)WccE%<#VA{pt9DUWgR6qftOsGm361||-&wv(Z
z?e�D1dn&5_8mMU+nUFojdI7|#v(J^p;c5Mx
zV{$^!*!R4O3l$)2xPZ$bdNp;(*{Z!#*bv7?XF?n?;|A
zopE|Qk=EGLo;@Ei2xC51I-eSnFiK`%0AAh*{jFd50Ds}5J3Jp!cZ&;B`BvW1n0GL9|F@J=<9wN)%29*4XA3kx)Q;iGn^LC
z{u@&2H(%cfQvdCKIe@R+@i5K!E*(H5Aa)d`Kzw@-qvc^pdm-QW2w`Oz2OO8@Z3ulNsN8U5L-cWft!D5xCvRG#l~
zHt^HCMuu?AC?j08y&&ZsAiEG0DuA?07@m!EIAo-VO9SWCfZVVwiW=B(w@i>y{g7{w
zli_%t+zc)`V!xf-E2}Nbgr;V0++;VHs=7gxGg)Raa#L4W5jGaqr^iP>Jsu4LySck@
zYt83nF>UJV=8-Wy+At2DNC4Gqk0mEsKK%<4~N#Rcl&<6p~W78Eu)d
zw8gC-6o-B~U`}936p^_L5ricPoz5q&r-_9!Qz9aUFtIQb@>qyzkfbB?#AuW8JULCX
zfhZBPuv(nLIVEy)rVwS4o*U9mc-SQ%F?><5J2M$fm4?;U$u4G&<-AZmD`Y5SCa8}K
z^X*8(z2SKJoZ9J$Za=u8ayJHnv`t*Sfy=I;@Niw
zIz1e5emr6S!5$a^Un-r>M_4_B*id$bBs1+_9N<1fO2K}74m%b)*BNbAW-g8kz3VMY@d5Qvk(9P=_M+#sd+d_39w_-Nqd#AIb0t;k?v
zZVjsQ@oXey!~S4Iq#|N~n@CcC%v9C9X)1$3UFYR&M6BaDG)}n@QFFHnP$Qy>m_1Z8
zTQqXAs+rb0tC==Kf{F}oO>J4u-ez@XM%fL4=)Ia7kO0($R78R#OwPTjp>c>$Lg0hJ
z)k46-OymB>U4sS^_f0|B0cj{;7C4lwMliNWCWFCUV_$)+Su!xM1nrfs#!#9_kVhat
zTZhO1k&yR8($=Lj6`gXwk+hsK0=LD65}9K)kIPxKR;x4?8&e7KI@R0msVR|PA9JOSuz*NITJK+v5BI&8^%MyNV_C4BS7zr|CT5bbN%lVqXqG
zMn4z_mC8EqKvgje0|pVC&qtU?^sq3r|;GCarO}z6}gn1i6f;ONE;v
z=ZxKM1dBxM31p>Z^^!3h{^xlDv0%3w(WaT08EP$PD-jM9beJwelCtlFsSwEs^Y(f;
z;>)9XMbS_TB)^ljhDC!$6JQ+2{;
z@30#WTl)uWAr!QrFL@4n$+PG801Qu$N7TCD?)gg`pB_-_5}yYHW!QnV#?S9G$hC)_
zAux649#Fqa0+V4xZC6Q{+?KvIK>(t>um!^rYx93Lb}R$@acIBTa1#&wGc3;ZKMx&0>ynhjC)F{K-J02Xgbe0pUzB3Bn)VsNfC5z
z84Hpmpe|0#o|!SvCm75>`RH3{(-E)UI7&&F&y#yIR}Hd4oJG0E*6~Jy>n>4RX=08L
zt*L8>+$AIB93*GT+*&_3fzd)YNQM?!3lU{XOlcEiGJ?8STSKig=H-NCYA%$JQt~9J
z$D65phzG3$A7Eye%#u!dh`~w>rX55i63s>lI-F@ltDhdv#J3CXVyWu$5i=ktkni+BXCx+WkH2_d6EsZ-p|0db_1K@!pDrmYX-1we8kAPs#j
z@8q;R79?MXE73F85IhsJAjx2oyDgc>dFTc#)ond?BPbfV2t-n+AxThgEXW-}&^^%F
z(^qQ{H7FQq$lw%bQozyL!t-n(A?!$?4w}^=0LqZixRC|r#wm~FwR!VS%LuC?i3prS
zJQ3U!1F?W8!L^g^VXjU{B}2eSLjvt?(9}(a5~4nhoT8?Vrp>*!Snm!85R)q>Q)38=
zrLicxx@C6}QZ=>X(wqzqur_2@ka13yQ!>|PXEi;as*yA=IeEGnT@9{HEyFF91R?Pj
zvD3alY^fbsAzh+l$%O@AxVoD6;i77_MVoVG&*R`?3KR1N^48q3G>2P6$Z;4Sk|YD5
zb()<7n#QbrGwSGvYU<6+ss~WC9hYh@gQf%dq}3T_rjFCYJ0G;-#b$cwi;_ifBbpq#}HX{A}sYciOPk{VV
z(_chZn*dBe8!RL-u0t}B`Xpxk+3P7Q5*U3Gs;r_P>0+?OE{3o$xW6A)#hp^gtCMi0
zjb8meTazSwLuGHQEWNxY%DtxPQjH+B_UTySm27o&J#dM_O;`U6fa+>m?ALZBSAjwV
z#@qYupQ&F&Tf7+~FGJM}XC_1tSBbqLM$?t)@7;_>muVOQD;%h~UqK}4Jt2C$mi`)6
zI8Z+|N{{SPH&nAOJmVf;7(-b>G}{{-nd1IDtC9BWu)gj!c76p=UCGkAxUCboh)`lF
zj~-0_NY{I<;UcUPz6d$`5c?{{^J0nYgs|;8yqDlcvl{kU-_p`nS
zz5;KU_wpi!PXM?c=x|*n_{@OL}J(5n{(O<~CTt%LKHKUI%jj47Q0e{JraUtr9^O@AGz##^-Do
zQr`B1x}crt{fIqUL7LXrzRp(bBJL}IT3-u8SL!`>_(~w@-6!q6+prDEx6hcbS{vJS
zb9V^Gt5SE8Q0DZ3mtVcp{{DLXc`b5|Iz6JDXVZ=H=c};x{iS~sthVmkkS@PF+
zf5U=ZVtnUjfF#B+B>c-S-_qN6M+}D%yBwmJr722E7>0tmi`f&EFeNoZs{||{Nd>kL
zbW+sC!8-~XYKt@%>3bP9Lh&68POKbaUUO{7#BNqt&$zGz(dZwjTUa$$Rk8b(n5)y4
znYVh6TyT}i(aEX_tOiSfs6d(^vj;iOiFBJUU<yvkRCa
z!3b&XzqA^Y=Cr2V$+*%q1)MkYiZU1E)=cd?>nBOP70>97r7%+RQd$=Gs5AX0*m{GeCNk
z(x}&Ug@vG4`+mM{q)I)lDQY4$thuUjHTxV3@D(SCK-T#6ZXTaQr`nr>M4~HN`-bRD
zn?YnX#;kk416%&9n!zj*575@WB|(+o8v8{vCS{Nt_xhZ>cE0!DWnFKBitZZGEOaHv
z4U()wGNIOnKl<@&{NW$J@>GO4o(IZ3mL33D>HUyf2}&lzVH(IW=?Q7Hm5;vFF~FtR
zU;-#P4qSr#d#Q=Kgf+g2^qM?!aTqxImR!wxC*K0?MVjro|!lz
zKNBl0^kUHJJsd
zS^|jR%|KyLrGSA5xb?N4Qmk9rUF1vcW&y@hBl;^zqD&6;hPD{8D3k@dD4>qTD`7g}
z`yV9yPk;S8^cOyUhMN$|(z+L~4dDMbanm;a
zg1G5=X(HGNj8C2vYy;e7$;I@$4?+6LEaJI{*wU
zwF1q+xkM;6MZrT?%`y*A#ad}|gxp1Nsc`IxYmG@^=}BGUmWYrERESWRX(Z4pM!g~U
z9Y6;McI3zoj06mD6adNH<*K)E=`~OLx3_mJC6Su(JWZTZqMO4(>fES3Iw^x_9C*yc#udz&gcBJvR|Dl;<~8ov
ztMOt$ZAx}-Bqaw~kBrO-+K6*ujANpk+Y!rB@$l}F6khESZ!
z2hS;u1QI7nwhU+V2NCKhC@y&+ulDoQZY}
zs|syPxIQaDJH_rWQe7&RqhkNzjzkQ@uE3TFG%NB>=m)>?5e`Y|I8XTctA^M01W~7N
zee{C9_}Oc`c=;R^2e?%#Hw9W3f;Y6*@a%&Z7;?ecnAsc&vX=&Tk(|Y!(D!#;?i(^d%0Ox>Sef9*FfUH}Fq8K5}Z&GYA0&oic{
zN%?s(%i_6=jmN#uPbX7^UDiPA>dvs<8;1d+2*`&j#F@Dn<;Id*)z;dq&CDAF)!b@3
z&x=*BGNvV^w3woqL5Y&Ni$Rk?2BT73s714Z6V%Yz$OKLasRWmxwgzj8WeyReYeSnB
zfC>4q14mE@>Qyr|Z_U8@5<9w**Q-CaP#q
z17%@w=Bx8%_bBBAx}x~9NRMX$DI$74?e<_9nOImbW>*td6)8Cprwp~7SKT|>o{R6P
z>Z*!x
zp~ukLYQr?2SA#?+NcKS@2eEUF$96No!$mRdb`VK$?VW9e$l`cBZDP@RK4O}VDB}pE
z?ijQN;e^I|X%?Dd7)R{OK>BsW!?jxDbpkM21+)t4&gWIU7nDbII$U=xO9FEOaY9N1
zO4>oem{sE-of6E9xHos|Tw!cD+}|grLgQNW~yIVzLd01jJpsjepMmXH({F}h97ilc2IFO(qe0<8$kiVEvo-ge
zkVF8obqdt+8$nNOs-QdoBIL}Nmj#s#yXW^9wW76#)A@vHd4wsD(}39))VAPk6-YpW
zfOCcn24lv&Odtk!yB+E>cTr|AT$$FGc3(ZJAx`e`^4^7^5noy2*&+oAL1X~)xQVT|
zwz+8t>X?yJfwl%WB{N_sJ8(;=bq>-cCopUDtj)ok@Z!aXczn#5r|Eq{YagjHUEG-A
zRHY=VUj`;ASPmz*g
znQ92xl7z6)3^|t&bpd#Kd;k%n)`sca;I7nK2s#gkXHctne0+knGg3;O-rQDJKDL%q
ze}=4!beV;?N4dpX1(0Nv@ql4>15O21Bc4st2(`x;kga_f^ANA@b`at|pzcpU3(O>P
z`#QuXNv5Ifd@_gD>On-Ii+TVQK`~t{%_Od@(RhmP2bo)MCPm1DPBWYZr>8T<-BVwu
zZHw&Y)zE-z8U)8VOa#?>1W^uZ?EdB!=I+{>D_Rhh!`