RISC-V/SiFive: Added SiFive custom cache control instructions.

According to the chapter 10 of the following U74-MC manual,
https://sifive.cdn.prismic.io/sifive/6d9a2510-2632-44f3-adb9-d0430f139372_sifive_coreip_U74MC_AXI4_rtl_v19_08p2p0_release_manual.pdf

and the implementations of freedom-metal,
https://github.com/sifive/freedom-metal/blob/v201908-branch/src/cache.c

* Encodings,
31-25   24-20 19-15 14-12  11-7  6-0
FUNCT7  RS2   RS1   FUNCT3 RD    OPCODE
1111110 00000 xxxxx 000    00000 1110011 CFLUSH.D.L1
1111110 00010 xxxxx 000    00000 1110011 CDISCARD.D.L1
1111110 00001 00000 000    00000 1110011 CFLUSH.I.L1

* Extension names,
xsfcflushdlone:   CFLUSH.D.L1.
xsfcdiscarddlone: CDISCARD.D.L1.
xsfcflushilone:   CFLUSH.I.L1.

* Vendor target triples,
For assembler, the target vendor is defined as TARGET_VENDOR in the
gas/config.h, but I don't see any related settings in bfd/config.h
and opcode/config.  Since we may have vendor relocations in the future,
and these relocation numbers may repeat, I add a new RISCV_TARGET_VENDOR
in the bfd/config.h for riscv.  The vendor name will be stored in the
bfd/cpu-riscv.c, so that all tools (gas, bfd, opcode, ...) can get
the vendor name from the configure setting.

If the --with-arch configure option, -march gas option and elf architecture
attributes are not set, then we will generate the default ISA string
according to the chosen target vendor.  For example, if you build the
binutils with the configure option, --target=riscv64-sifive-elf, then
the assembler will find the whole supported extension tables in the
bfd/elfxx-riscv.c, and generate the suitable ISA string.

bfd/
	* configure.ac (RISCV_TARGET_VENDOR): Defined to store target_vendor,
	only when the target is riscv*.
	* config.in: Regenerated.
	* configure: Regenerated.
	* cpu-riscv.c (riscv_vendor_name): Defined to RISCV_TARGET_VENDOR.
	* cpu-riscv.h (enum riscv_spec_class): Added VENDOR_SPEC_CLASS_SIFIVE.
	* elfxx-riscv. (EXT_SIFIVE): Defined to choose the default extensions
	for sifive.
	(riscv_supported_vendor_sifive_ext): Added extensions for sifive cache
	control instructions.
	(riscv_supported_std_ext, riscv_all_supported_ext): Updated.
	(riscv_get_default_ext_version): Updated.
	(riscv_set_default_arch): Updated.
gas/
	* config/tc-riscv.c (VENDOR_SIFIVE_EXT): Added.
	(riscv_extended_subset_supports): Handle INSN_CLASS_XSF*.
	(op_vendor_sifive_hash): Added to store sifive opcodes.
	(md_begin): Init the op_vendor_sifive_hash.
	(riscv_find_extended_opcode_hash): Find the opcodes from
	op_vendor_sifive_hash.
	* testsuite/gas/riscv/extended/sifive-insns.d: New testcase.
	* testsuite/gas/riscv/extended/sifive-insns.s: Likewise.
include/
	* opcode/riscv-opc-extended.h: Added opcodes for sifive cache
	instructions.
	* opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS_XSF*.
opcodes/
	* riscv-opc.c (riscv_vendor_sifive_opcodes): Added.
	(riscv_extended_opcodes): Updated.

bfd/config.in

@@ -257,6 +257,9 @@
 /* Define to the version of this package. */
 #undef PACKAGE_VERSION
 
+/* RISCV target vendor. */
+#undef RISCV_TARGET_VENDOR
+
 /* The size of `int', as computed by sizeof. */
 #undef SIZEOF_INT
 

bfd/configure

@@ -13658,6 +13658,16 @@ test -n "${selarchs}" && tdefaults="${tdefaults} -DSELECT_ARCHITECTURES='${selar
 
 
 
+case "${target_cpu}" in
+  riscv*)
+
+cat >>confdefs.h <<_ACEOF
+#define RISCV_TARGET_VENDOR "${target_vendor}"
+_ACEOF
+
+    ;;
+esac
+
 # If we are configured native, pick a core file support file.
 COREFILE=
 COREFLAG=

bfd/configure.ac

@@ -822,6 +822,12 @@ AC_SUBST(bfd_default_target_size)
 AC_SUBST(tdefaults)
 AC_SUBST(havevecs)
 
+case "${target_cpu}" in
+  riscv*)
+    AC_DEFINE_UNQUOTED(RISCV_TARGET_VENDOR, "${target_vendor}", [RISCV target vendor.])
+    ;;
+esac
+
 # If we are configured native, pick a core file support file.
 COREFILE=
 COREFLAG=

bfd/cpu-riscv.c

@@ -25,6 +25,8 @@
 #include "libbfd.h"
 #include "cpu-riscv.h"
 
+const char *riscv_vendor_name = RISCV_TARGET_VENDOR;
+
 static const bfd_arch_info_type *
 riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
 {

bfd/cpu-riscv.h

@@ -18,6 +18,8 @@
    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
+extern const char *riscv_vendor_name;
+
 enum riscv_spec_class
 {
   /* ISA spec.  */
@@ -33,6 +35,12 @@ enum riscv_spec_class
   PRIV_SPEC_CLASS_1P10,
   PRIV_SPEC_CLASS_1P11,
   PRIV_SPEC_CLASS_DRAFT,
+
+  /* Vendor spec for T_HEAD XuanTie.  */
+  VENDOR_SPEC_CLASS_THEAD,
+
+  /* Vendor spec for SiFive.  */
+  VENDOR_SPEC_CLASS_SIFIVE,
 };
 
 struct riscv_spec

bfd/elfxx-riscv.c

@@ -1073,15 +1073,44 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"g", "zicsr",	check_implicit_always},
   {"g", "zifencei",	check_implicit_always},
   {"q", "d",		check_implicit_always},
+  {"v", "d",		check_implicit_always},
+  {"v", "zve64d",	check_implicit_always},
+  {"v", "zvl128b",	check_implicit_always},
+  {"zvamo", "a",	check_implicit_always},
+  {"zve64d", "d",	check_implicit_always},
+  {"zve64d", "zve64f",	check_implicit_always},
+  {"zve64f", "zve32f",	check_implicit_always},
+  {"zve64f", "zve64x",	check_implicit_always},
+  {"zve64f", "zvl64b",	check_implicit_always},
+  {"zve32f", "f",	check_implicit_always},
+  {"zve32f", "zvl32b",	check_implicit_always},
+  {"zve32f", "zve32x",	check_implicit_always},
+  {"zve64x", "zve32x",	check_implicit_always},
+  {"zve64x", "zvl64b",	check_implicit_always},
+  {"zve32x", "zvl32b",	check_implicit_always},
+  {"zvl65536b", "zvl32768b",	check_implicit_always},
+  {"zvl32768b", "zvl16384b",	check_implicit_always},
+  {"zvl16384b", "zvl8192b",	check_implicit_always},
+  {"zvl8192b", "zvl4096b",	check_implicit_always},
+  {"zvl4096b", "zvl2048b",	check_implicit_always},
+  {"zvl2048b", "zvl1024b",	check_implicit_always},
+  {"zvl1024b", "zvl512b",	check_implicit_always},
+  {"zvl512b", "zvl256b",	check_implicit_always},
+  {"zvl256b", "zvl128b",	check_implicit_always},
+  {"zvl128b", "zvl64b",		check_implicit_always},
+  {"zvl64b", "zvl32b",		check_implicit_always},
   {"d", "f",		check_implicit_always},
   {"f", "zicsr",	check_implicit_always},
+  {"zfh", "f",		check_implicit_always},
+  {"zfh", "zicsr",	check_implicit_always},
   {NULL, NULL, NULL}
 };
 
 /* For default_enable field, decide if the extension should
    be enbaled by default.  */
 
-#define EXT_DEFAULT   0x1
+#define EXT_DEFAULT	0x1
+#define EXT_SIFIVE	(0x1 << 2)
 
 /* List all extensions that binutils should know about.  */
 
@@ -1106,7 +1135,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
   {"i",		ISA_SPEC_CLASS_2P2,		2, 0, 0 },
   /* The g is a special case which we don't want to output it,
      but still need it when adding implicit extensions.  */
-  {"g",		ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, EXT_DEFAULT },
+  {"g",		ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, EXT_DEFAULT|EXT_SIFIVE },
   {"m",		ISA_SPEC_CLASS_20191213,	2, 0, 0 },
   {"m",		ISA_SPEC_CLASS_20190608,	2, 0, 0 },
   {"m",		ISA_SPEC_CLASS_2P2,		2, 0, 0 },
@@ -1130,7 +1159,7 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
   {"j",		ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
   {"t",		ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
   {"p",		ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
-  {"v",		ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
+  {"v",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"n",		ISA_SPEC_CLASS_NONE, RISCV_UNKNOWN_VERSION, RISCV_UNKNOWN_VERSION, 0 },
   {NULL, 0, 0, 0, 0}
 };
@@ -1146,11 +1175,32 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zba",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zbs",               ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zve32x",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zve32f",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zve32d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zve64x",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zve64f",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl256b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl512b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl1024b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl2048b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl4096b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl8192b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl16384b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl32768b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvl65536b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvamo",		ISA_SPEC_CLASS_DRAFT,		0, 10, 0 },	/* draft.  */
+  {"zfh",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },	/* draft.  */
   {NULL, 0, 0, 0, 0}
 };
 
 static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
+  {"svinval",		ISA_SPEC_CLASS_DRAFT,	0, 1, 0 },		/* draft.  */
   {NULL, 0, 0, 0, 0}
 };
 
@@ -1164,6 +1214,24 @@ static struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
   {NULL, 0, 0, 0, 0}
 };
 
+/* T-HEAD extentions for Xuantie C9xx.  The version 2.0 just keeps
+   compatible.  */
+static struct riscv_supported_ext riscv_supported_vendor_thead_ext[] =
+{
+  {"xtheadc",		VENDOR_SPEC_CLASS_THEAD,	2, 0, 0 },
+  {"xtheade",		VENDOR_SPEC_CLASS_THEAD,	2, 0, 0 },
+  {"xtheadse",		VENDOR_SPEC_CLASS_THEAD,	2, 0, 0 },
+  {NULL, 0, 0, 0, 0}
+};
+
+static struct riscv_supported_ext riscv_supported_vendor_sifive_ext[] =
+{
+  {"xsfcdiscarddlone",	VENDOR_SPEC_CLASS_SIFIVE,	0, 1, EXT_SIFIVE},
+  {"xsfcflushdlone",	VENDOR_SPEC_CLASS_SIFIVE,	0, 1, EXT_SIFIVE},
+  {"xsfcflushilone",	VENDOR_SPEC_CLASS_SIFIVE,	0, 1, EXT_SIFIVE},
+  {NULL, 0, 0, 0, 0}
+};
+
 const struct riscv_supported_ext *riscv_all_supported_ext[] =
 {
   riscv_supported_std_ext,
@@ -1171,6 +1239,8 @@ const struct riscv_supported_ext *riscv_all_supported_ext[] =
   riscv_supported_std_s_ext,
   riscv_supported_std_h_ext,
   riscv_supported_std_zxm_ext,
+  riscv_supported_vendor_thead_ext,
+  riscv_supported_vendor_sifive_ext,
   NULL
 };
 
@@ -1435,6 +1505,10 @@ riscv_get_default_ext_version (enum riscv_spec_class default_isa_spec,
     case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break;
     case RV_ISA_CLASS_H: table = riscv_supported_std_h_ext; break;
     case RV_ISA_CLASS_X:
+      if (strncmp (name, "xsf", 3) == 0)
+	table = riscv_supported_vendor_sifive_ext;
+      else
+	table = riscv_supported_vendor_thead_ext;
       break;
     default:
       table = riscv_supported_std_ext;
@@ -1445,6 +1519,8 @@ riscv_get_default_ext_version (enum riscv_spec_class default_isa_spec,
     {
       if (strcmp (table[i].name, name) == 0
 	  && (table[i].isa_spec_class == ISA_SPEC_CLASS_DRAFT
+	      || table[i].isa_spec_class == VENDOR_SPEC_CLASS_THEAD
+	      || table[i].isa_spec_class == VENDOR_SPEC_CLASS_SIFIVE
 	      || table[i].isa_spec_class == default_isa_spec))
 	{
 	  *major_version = table[i].major_version;
@@ -1824,6 +1900,28 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
         (_("rv32e does not support the `f' extension"));
       no_conflict = false;
     }
+
+  bool support_zve = false;
+  bool support_zvl = false;
+  riscv_subset_t *s = rps->subset_list->head;
+  for (; s != NULL; s = s->next)
+    {
+      if (!support_zve
+	  && strncmp (s->name, "zve", 3) == 0)
+	support_zve = true;
+      if (!support_zvl
+	  && strncmp (s->name, "zvl", 3) == 0)
+	support_zvl = true;
+      if (support_zve && support_zvl)
+	break;
+    }
+  if (support_zvl && !support_zve)
+    {
+      rps->error_handler
+	(_("zvl*b extensions need to enable either `v' or `zve' extension"));
+      no_conflict = false;
+    }
+
   return no_conflict;
 }
 
@@ -1833,8 +1931,14 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
 static void
 riscv_set_default_arch (riscv_parse_subset_t *rps)
 {
-  unsigned long enable = EXT_DEFAULT;
+  unsigned long enable;
   int i, j;
+
+  if (strcmp (riscv_vendor_name, "sifive") == 0)
+    enable = EXT_SIFIVE;
+  else
+    enable = EXT_DEFAULT;
+
   for (i = 0; riscv_all_supported_ext[i] != NULL; i++)
     {
       const struct riscv_supported_ext *table = riscv_all_supported_ext[i];

gas/testsuite/gas/riscv/extended/extended-csr.d

@@ -0,0 +1,16 @@
+#as: -march=rv32iv
+#objdump: -d
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[     	]+[0-9a-f]+:[  	]+00802573[    	]+csrr[     	]+a0,vstart
+[     	]+[0-9a-f]+:[  	]+00902573[    	]+csrr[        	]+a0,vxsat
+[     	]+[0-9a-f]+:[  	]+00a02573[    	]+csrr[       	]+a0,vxrm
+[     	]+[0-9a-f]+:[  	]+00f02573[    	]+csrr[     	]+a0,vcsr
+[     	]+[0-9a-f]+:[  	]+c2002573[    	]+csrr[        	]+a0,vl
+[     	]+[0-9a-f]+:[  	]+c2102573[    	]+csrr[       	]+a0,vtype
+[     	]+[0-9a-f]+:[  	]+c2202573[    	]+csrr[       	]+a0,vlenb

gas/testsuite/gas/riscv/extended/extended-csr.s

@@ -0,0 +1,12 @@
+	.macro csr val
+	csrr a0,\val
+	.endm
+
+	# Vector
+	csr vstart
+	csr vxsat
+	csr vxrm
+	csr vcsr
+	csr vl
+	csr vtype
+	csr vlenb

gas/testsuite/gas/riscv/extended/extended.exp

@@ -0,0 +1,23 @@
+# Expect script for RISC-V assembler tests.
+# Copyright (C) 2021 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if [istarget riscv*-*-*] {
+    run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+}

gas/testsuite/gas/riscv/extended/float16-be.d

@@ -0,0 +1,10 @@
+# source: float16.s
+# objdump: -sj .data
+# as: -mbig-endian
+
+.*:[ 	]+file format .*bigriscv
+
+Contents of section \.data:
+ 0000 4a002fdf 1c197bff 000103ff 04003c00.*
+ 0010 3c017fff 7c00fc00 00008000 bc00bbe7.*
+ 0020 fbff4200 4a00603e 7e007c01.*

gas/testsuite/gas/riscv/extended/float16-le.d

@@ -0,0 +1,10 @@
+# source: float16.s
+# objdump: -sj .data
+# as: -mlittle-endian
+
+.*:[ 	]+file format .*littleriscv
+
+Contents of section \.data:
+ 0000 004adf2f 191cff7b 0100ff03 0004003c.*
+ 0010 013cff7f 007c00fc 00000080 00bce7bb.*
+ 0020 fffb0042 004a3e60 007e017c.*

gas/testsuite/gas/riscv/extended/float16.s

@@ -0,0 +1,21 @@
+.data
+	.float16 12.0
+	.float16 0.123
+	.float16 0.004
+	.float16 65504
+	.float16 5.9605e-8
+	.float16 6.0976e-5
+	.float16 6.1035e-5
+	.float16 1
+	.float16 1.001
+	.float16 NaN
+	.float16 +Inf
+	.float16 -Inf
+	.float16 +0
+	.float16 -0
+	.float16 -1
+	.float16 -0.98765
+	.float16 -65504
+	.float16 3.0, 12.0, 543.123
+	.float16 0h:7e00	# qNaNh
+	.float16 0h:7c01	# sNaNh

gas/testsuite/gas/riscv/extended/fp-zfh-insns.d

@@ -0,0 +1,71 @@
+#as: -march=rv64ifdq_zfh
+#source: fp-zfh-insns.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+00059507[ 	]+flh[ 	]+fa0,0\(a1\)
+[ 	]+[0-9a-f]+:[ 	]+00a59027[ 	]+fsh[ 	]+fa0,0\(a1\)
+[ 	]+[0-9a-f]+:[ 	]+24b58553[ 	]+fmv.h[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+24b59553[ 	]+fneg.h[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+24b5a553[ 	]+fabs.h[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+24c58553[ 	]+fsgnj.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+24c59553[ 	]+fsgnjn.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+24c5a553[ 	]+fsgnjx.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+04c5f553[ 	]+fadd.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+04c58553[ 	]+fadd.h[ 	]+fa0,fa1,fa2,rne
+[ 	]+[0-9a-f]+:[ 	]+0cc5f553[ 	]+fsub.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+0cc58553[ 	]+fsub.h[ 	]+fa0,fa1,fa2,rne
+[ 	]+[0-9a-f]+:[ 	]+14c5f553[ 	]+fmul.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+14c58553[ 	]+fmul.h[ 	]+fa0,fa1,fa2,rne
+[ 	]+[0-9a-f]+:[ 	]+1cc5f553[ 	]+fdiv.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+1cc58553[ 	]+fdiv.h[ 	]+fa0,fa1,fa2,rne
+[ 	]+[0-9a-f]+:[ 	]+5c05f553[ 	]+fsqrt.h[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+5c058553[ 	]+fsqrt.h[ 	]+fa0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+2cc58553[ 	]+fmin.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+2cc59553[ 	]+fmax.h[ 	]+fa0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+6cc5f543[ 	]+fmadd.h[ 	]+fa0,fa1,fa2,fa3
+[ 	]+[0-9a-f]+:[ 	]+6cc58543[ 	]+fmadd.h[ 	]+fa0,fa1,fa2,fa3,rne
+[ 	]+[0-9a-f]+:[ 	]+6cc5f54f[ 	]+fnmadd.h[ 	]+fa0,fa1,fa2,fa3
+[ 	]+[0-9a-f]+:[ 	]+6cc5854f[ 	]+fnmadd.h[ 	]+fa0,fa1,fa2,fa3,rne
+[ 	]+[0-9a-f]+:[ 	]+6cc5f547[ 	]+fmsub.h[ 	]+fa0,fa1,fa2,fa3
+[ 	]+[0-9a-f]+:[ 	]+6cc58547[ 	]+fmsub.h[ 	]+fa0,fa1,fa2,fa3,rne
+[ 	]+[0-9a-f]+:[ 	]+6cc5f54b[ 	]+fnmsub.h[ 	]+fa0,fa1,fa2,fa3
+[ 	]+[0-9a-f]+:[ 	]+6cc5854b[ 	]+fnmsub.h[ 	]+fa0,fa1,fa2,fa3,rne
+[ 	]+[0-9a-f]+:[ 	]+c405f553[ 	]+fcvt.w.h[ 	]+a0,fa1
+[ 	]+[0-9a-f]+:[ 	]+c4058553[ 	]+fcvt.w.h[ 	]+a0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+c415f553[ 	]+fcvt.wu.h[ 	]+a0,fa1
+[ 	]+[0-9a-f]+:[ 	]+c4158553[ 	]+fcvt.wu.h[ 	]+a0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+d405f553[ 	]+fcvt.h.w[ 	]+fa0,a1
+[ 	]+[0-9a-f]+:[ 	]+d4058553[ 	]+fcvt.h.w[ 	]+fa0,a1,rne
+[ 	]+[0-9a-f]+:[ 	]+d415f553[ 	]+fcvt.h.wu[ 	]+fa0,a1
+[ 	]+[0-9a-f]+:[ 	]+d4158553[ 	]+fcvt.h.wu[ 	]+fa0,a1,rne
+[ 	]+[0-9a-f]+:[ 	]+c425f553[ 	]+fcvt.l.h[ 	]+a0,fa1
+[ 	]+[0-9a-f]+:[ 	]+c4258553[ 	]+fcvt.l.h[ 	]+a0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+c435f553[ 	]+fcvt.lu.h[ 	]+a0,fa1
+[ 	]+[0-9a-f]+:[ 	]+c4358553[ 	]+fcvt.lu.h[ 	]+a0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+d425f553[ 	]+fcvt.h.l[ 	]+fa0,a1
+[ 	]+[0-9a-f]+:[ 	]+d4258553[ 	]+fcvt.h.l[ 	]+fa0,a1,rne
+[ 	]+[0-9a-f]+:[ 	]+d435f553[ 	]+fcvt.h.lu[ 	]+fa0,a1
+[ 	]+[0-9a-f]+:[ 	]+d4358553[ 	]+fcvt.h.lu[ 	]+fa0,a1,rne
+[ 	]+[0-9a-f]+:[ 	]+e4058553[ 	]+fmv.x.h[ 	]+a0,fa1
+[ 	]+[0-9a-f]+:[ 	]+f4058553[ 	]+fmv.h.x[ 	]+fa0,a1
+[ 	]+[0-9a-f]+:[ 	]+40258553[ 	]+fcvt.s.h[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+42258553[ 	]+fcvt.d.h[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+46258553[ 	]+fcvt.q.h[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+4405f553[ 	]+fcvt.h.s[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+44058553[ 	]+fcvt.h.s[ 	]+fa0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+4415f553[ 	]+fcvt.h.d[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+44158553[ 	]+fcvt.h.d[ 	]+fa0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+4435f553[ 	]+fcvt.h.q[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+44358553[ 	]+fcvt.h.q[ 	]+fa0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+e4059553[ 	]+fclass.h[ 	]+a0,fa1
+[ 	]+[0-9a-f]+:[ 	]+a4c5a553[ 	]+feq.h[ 	]+a0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+a4c59553[ 	]+flt.h[ 	]+a0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+a4c58553[ 	]+fle.h[ 	]+a0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+a4c59553[ 	]+flt.h[ 	]+a0,fa1,fa2
+[ 	]+[0-9a-f]+:[ 	]+a4c58553[ 	]+fle.h[ 	]+a0,fa1,fa2

gas/testsuite/gas/riscv/extended/fp-zfh-insns.s

@@ -0,0 +1,68 @@
+	flh		fa0, 0(a1)
+	fsh		fa0, 0(a1)
+
+	fmv.h		fa0, fa1
+	fneg.h		fa0, fa1
+	fabs.h		fa0, fa1
+	fsgnj.h		fa0, fa1, fa2
+	fsgnjn.h	fa0, fa1, fa2
+	fsgnjx.h	fa0, fa1, fa2
+
+	fadd.h		fa0, fa1, fa2
+	fadd.h		fa0, fa1, fa2, rne
+	fsub.h		fa0, fa1, fa2
+	fsub.h		fa0, fa1, fa2, rne
+	fmul.h		fa0, fa1, fa2
+	fmul.h		fa0, fa1, fa2, rne
+	fdiv.h		fa0, fa1, fa2
+	fdiv.h		fa0, fa1, fa2, rne
+	fsqrt.h		fa0, fa1
+	fsqrt.h		fa0, fa1, rne
+	fmin.h		fa0, fa1, fa2
+	fmax.h		fa0, fa1, fa2
+
+	fmadd.h		fa0, fa1, fa2, fa3
+	fmadd.h		fa0, fa1, fa2, fa3, rne
+	fnmadd.h	fa0, fa1, fa2, fa3
+	fnmadd.h	fa0, fa1, fa2, fa3, rne
+	fmsub.h		fa0, fa1, fa2, fa3
+	fmsub.h		fa0, fa1, fa2, fa3, rne
+	fnmsub.h	fa0, fa1, fa2, fa3
+	fnmsub.h	fa0, fa1, fa2, fa3, rne
+
+	fcvt.w.h	a0, fa1
+	fcvt.w.h	a0, fa1, rne
+	fcvt.wu.h	a0, fa1
+	fcvt.wu.h	a0, fa1, rne
+	fcvt.h.w	fa0, a1
+	fcvt.h.w	fa0, a1, rne
+	fcvt.h.wu	fa0, a1
+	fcvt.h.wu	fa0, a1, rne
+	fcvt.l.h	a0, fa1
+	fcvt.l.h	a0, fa1, rne
+	fcvt.lu.h	a0, fa1
+	fcvt.lu.h	a0, fa1, rne
+	fcvt.h.l	fa0, a1
+	fcvt.h.l	fa0, a1, rne
+	fcvt.h.lu	fa0, a1
+	fcvt.h.lu	fa0, a1, rne
+
+	fmv.x.h		a0, fa1
+	fmv.h.x		fa0, a1
+
+	fcvt.s.h	fa0, fa1
+	fcvt.d.h	fa0, fa1
+	fcvt.q.h	fa0, fa1
+	fcvt.h.s	fa0, fa1
+	fcvt.h.s	fa0, fa1, rne
+	fcvt.h.d	fa0, fa1
+	fcvt.h.d	fa0, fa1, rne
+	fcvt.h.q	fa0, fa1
+	fcvt.h.q	fa0, fa1, rne
+	fclass.h	a0, fa1
+
+	feq.h		a0, fa1, fa2
+	flt.h		a0, fa1, fa2
+	fle.h		a0, fa1, fa2
+	fgt.h		a0, fa2, fa1
+	fge.h		a0, fa2, fa1

gas/testsuite/gas/riscv/extended/march-imply-v.d

@@ -0,0 +1,6 @@
+#as: -march=rv32iv -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zve32f.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32f -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zve32x.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl32b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zve64d.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64d -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zve64f.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64f -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zve64x.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64x -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl1024b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl1024b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl128b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl128b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl16384b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl16384b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl2048b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl2048b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl256b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl256b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl32768b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl32768b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl4096b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl4096b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl512b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl512b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl64b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl64b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl32b1p0_zvl64b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl65536b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl65536b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0"

gas/testsuite/gas/riscv/extended/march-imply-zvl8192b.d

@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl8192b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"

gas/testsuite/gas/riscv/extended/sifive-insns.d

@@ -0,0 +1,12 @@
+#as: -march=rv32i_xsfcdiscarddlone_xsfcflushdlone_xsfcflushilone
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+fc050073[ 	]+cflush.d.l1[ 	]+a0
+[ 	]+4:[ 	]+fc250073[ 	]+cdiscard.d.l1[ 	]+a0
+[ 	]+8:[ 	]+fc100073[ 	]+cflush.i.l1

gas/testsuite/gas/riscv/extended/sifive-insns.s

@@ -0,0 +1,4 @@
+target:
+	cflush.d.l1	x10
+	cdiscard.d.l1	x10
+	cflush.i.l1

gas/testsuite/gas/riscv/extended/svinval.d

@@ -0,0 +1,15 @@
+#as: -march=rv32i_svinval
+#source: svinval.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+0:[ 	]+16b50073[ 	]+sinval.vma[ 	]+a0,a1
+[ 	]+4:[ 	]+18000073[ 	]+sfence.w.inval
+[ 	]+8:[ 	]+18100073[ 	]+sfence.inval.ir
+[ 	]+c:[ 	]+36b50073[ 	]+hinval.vvma[ 	]+a0,a1
+[ 	]+10:[ 	]+76b50073[ 	]+hinval.gvma[ 	]+a0,a1

gas/testsuite/gas/riscv/extended/svinval.s

@@ -0,0 +1,5 @@
+	sinval.vma	a0, a1
+	sfence.w.inval
+	sfence.inval.ir
+	hinval.vvma	a0, a1
+	hinval.gvma	a0, a1

gas/testsuite/gas/riscv/extended/thead-csr-list.d

@@ -0,0 +1,107 @@
+#as: -march=rv64gcxtheadc
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0000000000000000 <.text>:
+   0:	7c002573          	csrr	a0,mxstatus
+   4:	7c102573          	csrr	a0,mhcr
+   8:	7c202573          	csrr	a0,mcor
+   c:	7c302573          	csrr	a0,mccr2
+  10:	7c402573          	csrr	a0,mcer2
+  14:	7c502573          	csrr	a0,mhint
+  18:	7c602573          	csrr	a0,mrmr
+  1c:	7c702573          	csrr	a0,mrvbr
+  20:	7c802573          	csrr	a0,mcer
+  24:	7c902573          	csrr	a0,mcounterwen
+  28:	7ca02573          	csrr	a0,mcounterinten
+  2c:	7cb02573          	csrr	a0,mcounterof
+  30:	7cc02573          	csrr	a0,mhint2
+  34:	7cd02573          	csrr	a0,mhint3
+  38:	7e002573          	csrr	a0,mraddr
+  3c:	7e102573          	csrr	a0,mexstatus
+  40:	7e202573          	csrr	a0,mnmicause
+  44:	7e302573          	csrr	a0,mnmipc
+  48:	7f002573          	csrr	a0,mhpmcr
+  4c:	7f102573          	csrr	a0,mhpmsr
+  50:	7f202573          	csrr	a0,mhpmer
+  54:	7f302573          	csrr	a0,msmpr
+  58:	7f402573          	csrr	a0,mteecfg
+  5c:	7d102573          	csrr	a0,usp
+  60:	7d202573          	csrr	a0,mcins
+  64:	7d302573          	csrr	a0,mcindex
+  68:	7d402573          	csrr	a0,mcdata0
+  6c:	7d502573          	csrr	a0,mcdata1
+  70:	7d602573          	csrr	a0,meicr
+  74:	7d702573          	csrr	a0,meicr2
+  78:	be002573          	csrr	a0,mebr
+  7c:	be102573          	csrr	a0,nt_mstatus
+  80:	be302573          	csrr	a0,nt_mtvec
+  84:	be202573          	csrr	a0,nt_mie
+  88:	be402573          	csrr	a0,nt_mtvt
+  8c:	be502573          	csrr	a0,nt_mepc
+  90:	be602573          	csrr	a0,nt_mcause
+  94:	be702573          	csrr	a0,nt_mip
+  98:	be802573          	csrr	a0,nt_mintstate
+  9c:	be902573          	csrr	a0,nt_mxstatus
+  a0:	bea02573          	csrr	a0,nt_mebr
+  a4:	beb02573          	csrr	a0,nt_msp
+  a8:	bec02573          	csrr	a0,t_usp
+  ac:	bed02573          	csrr	a0,t_mdcr
+  b0:	bee02573          	csrr	a0,t_mpcr
+  b4:	bef02573          	csrr	a0,pmpteecfg
+  b8:	fc002573          	csrr	a0,mcpuid
+  bc:	fc102573          	csrr	a0,mapbaddr
+  c0:	fc202573          	csrr	a0,mwmsr
+  c4:	80002573          	csrr	a0,fxcr
+  c8:	9c002573          	csrr	a0,smir
+  cc:	9c102573          	csrr	a0,smel
+  d0:	9c202573          	csrr	a0,smeh
+  d4:	9c302573          	csrr	a0,smcir
+  d8:	5c002573          	csrr	a0,sxstatus
+  dc:	5c102573          	csrr	a0,shcr
+  e0:	5c202573          	csrr	a0,scer2
+  e4:	5c302573          	csrr	a0,scer
+  e8:	5c402573          	csrr	a0,scounterinten
+  ec:	5c502573          	csrr	a0,scounterof
+  f0:	5c602573          	csrr	a0,shint
+  f4:	5c702573          	csrr	a0,shint2
+  f8:	5c802573          	csrr	a0,shpminhibit
+  fc:	5c902573          	csrr	a0,shpmcr
+ 100:	5ca02573          	csrr	a0,shpmsr
+ 104:	5cb02573          	csrr	a0,shpmer
+ 108:	5e002573          	csrr	a0,scycle
+ 10c:	5e102573          	csrr	a0,shpmcounter1
+ 110:	5e202573          	csrr	a0,shpmcounter2
+ 114:	5e302573          	csrr	a0,shpmcounter3
+ 118:	5e402573          	csrr	a0,shpmcounter4
+ 11c:	5e502573          	csrr	a0,shpmcounter5
+ 120:	5e602573          	csrr	a0,shpmcounter6
+ 124:	5e702573          	csrr	a0,shpmcounter7
+ 128:	5e802573          	csrr	a0,shpmcounter8
+ 12c:	5e902573          	csrr	a0,shpmcounter9
+ 130:	5ea02573          	csrr	a0,shpmcounter10
+ 134:	5eb02573          	csrr	a0,shpmcounter11
+ 138:	5ec02573          	csrr	a0,shpmcounter12
+ 13c:	5ed02573          	csrr	a0,shpmcounter13
+ 140:	5ee02573          	csrr	a0,shpmcounter14
+ 144:	5ef02573          	csrr	a0,shpmcounter15
+ 148:	5f002573          	csrr	a0,shpmcounter16
+ 14c:	5f102573          	csrr	a0,shpmcounter17
+ 150:	5f202573          	csrr	a0,shpmcounter18
+ 154:	5f302573          	csrr	a0,shpmcounter19
+ 158:	5f402573          	csrr	a0,shpmcounter20
+ 15c:	5f502573          	csrr	a0,shpmcounter21
+ 160:	5f602573          	csrr	a0,shpmcounter22
+ 164:	5f702573          	csrr	a0,shpmcounter23
+ 168:	5f802573          	csrr	a0,shpmcounter24
+ 16c:	5f902573          	csrr	a0,shpmcounter25
+ 170:	5fa02573          	csrr	a0,shpmcounter26
+ 174:	5fb02573          	csrr	a0,shpmcounter27
+ 178:	5fc02573          	csrr	a0,shpmcounter28
+ 17c:	5fd02573          	csrr	a0,shpmcounter29
+ 180:	5fe02573          	csrr	a0,shpmcounter30
+ 184:	5ff02573          	csrr	a0,shpmcounter31

gas/testsuite/gas/riscv/extended/thead-csr-list.s

@@ -0,0 +1,98 @@
+csrr a0, mxstatus
+csrr a0, mhcr
+csrr a0, mcor
+csrr a0, mccr2
+csrr a0, mcer2
+csrr a0, mhint
+csrr a0, mrmr
+csrr a0, mrvbr
+csrr a0, mcer
+csrr a0, mcounterwen
+csrr a0, mcounterinten
+csrr a0, mcounterof
+csrr a0, mhint2
+csrr a0, mhint3
+csrr a0, mraddr
+csrr a0, mexstatus
+csrr a0, mnmicause
+csrr a0, mnmipc
+csrr a0, mhpmcr
+csrr a0, mhpmsr
+csrr a0, mhpmer
+csrr a0, msmpr
+csrr a0, mteecfg
+csrr a0, usp
+csrr a0, mcins
+csrr a0, mcindex
+csrr a0, mcdata0
+csrr a0, mcdata1
+csrr a0, meicr
+csrr a0, meicr2
+csrr a0, mebr
+csrr a0, nt_mstatus
+csrr a0, nt_mtvec
+csrr a0, nt_mie
+csrr a0, nt_mtvt
+csrr a0, nt_mepc
+csrr a0, nt_mcause
+csrr a0, nt_mip
+csrr a0, nt_mintstate
+csrr a0, nt_mxstatus
+csrr a0, nt_mebr
+csrr a0, nt_msp
+csrr a0, t_usp
+csrr a0, t_mdcr
+csrr a0, t_mpcr
+csrr a0, pmpteecfg
+csrr a0, mcpuid
+csrr a0, mapbaddr
+csrr a0, mwmsr
+csrr a0, fxcr
+csrr a0, smir
+csrr a0, smel
+csrr a0, smeh
+csrr a0, smcir
+csrr a0, sxstatus
+csrr a0, shcr
+csrr a0, scer2
+csrr a0, scer
+csrr a0, scounterinten
+csrr a0, scounterof
+csrr a0, shint
+csrr a0, shint2
+csrr a0, shpminhibit
+csrr a0, shpmcr
+csrr a0, shpmsr
+csrr a0, shpmer
+csrr a0, scycle
+csrr a0, shpmcounter1
+csrr a0, shpmcounter2
+csrr a0, shpmcounter3
+csrr a0, shpmcounter4
+csrr a0, shpmcounter5
+csrr a0, shpmcounter6
+csrr a0, shpmcounter7
+csrr a0, shpmcounter8
+csrr a0, shpmcounter9
+csrr a0, shpmcounter10
+csrr a0, shpmcounter11
+csrr a0, shpmcounter12
+csrr a0, shpmcounter13
+csrr a0, shpmcounter14
+csrr a0, shpmcounter15
+csrr a0, shpmcounter16
+csrr a0, shpmcounter17
+csrr a0, shpmcounter18
+csrr a0, shpmcounter19
+csrr a0, shpmcounter20
+csrr a0, shpmcounter21
+csrr a0, shpmcounter22
+csrr a0, shpmcounter23
+csrr a0, shpmcounter24
+csrr a0, shpmcounter25
+csrr a0, shpmcounter26
+csrr a0, shpmcounter27
+csrr a0, shpmcounter28
+csrr a0, shpmcounter29
+csrr a0, shpmcounter30
+csrr a0, shpmcounter31

gas/testsuite/gas/riscv/extended/theadc-ext.d

@@ -0,0 +1,112 @@
+#as: -march=rv64gcxtheadc
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0000000000000000 <.text>:
+   0:	cff01073          	csrw	0xcff,zero
+   4:	0010000b          	dcache.call
+   8:	0030000b          	dcache.ciall
+   c:	02b5000b          	dcache.cipa	a0
+  10:	0235000b          	dcache.cisw	a0
+  14:	0275000b          	dcache.civa	a0
+  18:	0295000b          	dcache.cpa	a0
+  1c:	0285000b          	dcache.cpal1	a0
+  20:	0255000b          	dcache.cva	a0
+  24:	0245000b          	dcache.cval1	a0
+  28:	02a5000b          	dcache.ipa	a0
+  2c:	0225000b          	dcache.isw	a0
+  30:	0265000b          	dcache.iva	a0
+  34:	0020000b          	dcache.iall
+  38:	0215000b          	dcache.csw	a0
+  3c:	0100000b          	icache.iall
+  40:	0110000b          	icache.ialls
+  44:	0305000b          	icache.iva	a0
+  48:	0385000b          	icache.ipa	a0
+  4c:	0160000b          	l2cache.iall
+  50:	0150000b          	l2cache.call
+  54:	0170000b          	l2cache.ciall
+  58:	04b5000b          	sfence.vmas	a0,a1
+  5c:	0180000b          	sync
+  60:	01a0000b          	sync.i
+  64:	0190000b          	sync.s
+  68:	01b0000b          	sync.is
+  6c:	02c5950b          	addsl	a0,a1,a2,1
+  70:	20c5950b          	mula	a0,a1,a2
+  74:	22c5950b          	muls	a0,a1,a2
+  78:	24c5950b          	mulaw	a0,a1,a2
+  7c:	26c5950b          	mulsw	a0,a1,a2
+  80:	28c5950b          	mulah	a0,a1,a2
+  84:	2ac5950b          	mulsh	a0,a1,a2
+  88:	1105950b          	srri	a0,a1,16
+  8c:	1505950b          	srriw	a0,a1,16
+  90:	40c5950b          	mveqz	a0,a1,a2
+  94:	42c5950b          	mvnez	a0,a1,a2
+  98:	8905950b          	tst	a0,a1,16
+  9c:	8005950b          	tstnbz	a0,a1
+  a0:	4105a50b          	ext	a0,a1,16,16
+  a4:	4105b50b          	extu	a0,a1,16,16
+  a8:	8605950b          	ff1	a0,a1
+  ac:	8405950b          	ff0	a0,a1
+  b0:	8205950b          	rev	a0,a1
+  b4:	9005950b          	revw	a0,a1
+  b8:	62b5600b          	flrd	ft0,a0,a1,1
+  bc:	42b5600b          	flrw	ft0,a0,a1,1
+  c0:	72b5600b          	flurd	ft0,a0,a1,1
+  c4:	52b5600b          	flurw	ft0,a0,a1,1
+  c8:	02c5c50b          	lrb	a0,a1,a2,1
+  cc:	22c5c50b          	lrh	a0,a1,a2,1
+  d0:	42c5c50b          	lrw	a0,a1,a2,1
+  d4:	62c5c50b          	lrd	a0,a1,a2,1
+  d8:	82c5c50b          	lrbu	a0,a1,a2,1
+  dc:	a2c5c50b          	lrhu	a0,a1,a2,1
+  e0:	c2c5c50b          	lrwu	a0,a1,a2,1
+  e4:	12c5c50b          	lurb	a0,a1,a2,1
+  e8:	32c5c50b          	lurh	a0,a1,a2,1
+  ec:	52c5c50b          	lurw	a0,a1,a2,1
+  f0:	72c5c50b          	lurd	a0,a1,a2,1
+  f4:	92c5c50b          	lurbu	a0,a1,a2,1
+  f8:	b2c5c50b          	lurhu	a0,a1,a2,1
+  fc:	d2c5c50b          	lurwu	a0,a1,a2,1
+ 100:	1af5c50b          	lbia	a0,\(a1\),15,1
+ 104:	0af5c50b          	lbib	a0,\(a1\),15,1
+ 108:	3af5c50b          	lhia	a0,\(a1\),15,1
+ 10c:	2af5c50b          	lhib	a0,\(a1\),15,1
+ 110:	5af5c50b          	lwia	a0,\(a1\),15,1
+ 114:	4af5c50b          	lwib	a0,\(a1\),15,1
+ 118:	7af5c50b          	ldia	a0,\(a1\),15,1
+ 11c:	6af5c50b          	ldib	a0,\(a1\),15,1
+ 120:	9af5c50b          	lbuia	a0,\(a1\),15,1
+ 124:	8af5c50b          	lbuib	a0,\(a1\),15,1
+ 128:	baf5c50b          	lhuia	a0,\(a1\),15,1
+ 12c:	aaf5c50b          	lhuib	a0,\(a1\),15,1
+ 130:	daf5c50b          	lwuia	a0,\(a1\),15,1
+ 134:	caf5c50b          	lwuib	a0,\(a1\),15,1
+ 138:	fab6450b          	ldd	a0,a1,\(a2\),1
+ 13c:	e2b6450b          	lwd	a0,a1,\(a2\),1
+ 140:	f2b6450b          	lwud	a0,a1,\(a2\),1
+ 144:	62b5700b          	fsrd	ft0,a0,a1,1
+ 148:	42b5700b          	fsrw	ft0,a0,a1,1
+ 14c:	72b5700b          	fsurd	ft0,a0,a1,1
+ 150:	52b5700b          	fsurw	ft0,a0,a1,1
+ 154:	02c5d50b          	srb	a0,a1,a2,1
+ 158:	22c5d50b          	srh	a0,a1,a2,1
+ 15c:	42c5d50b          	srw	a0,a1,a2,1
+ 160:	62c5d50b          	srd	a0,a1,a2,1
+ 164:	12c5d50b          	surb	a0,a1,a2,1
+ 168:	32c5d50b          	surh	a0,a1,a2,1
+ 16c:	52c5d50b          	surw	a0,a1,a2,1
+ 170:	72c5d50b          	surd	a0,a1,a2,1
+ 174:	1af5d50b          	sbia	a0,\(a1\),15,1
+ 178:	0af5d50b          	sbib	a0,\(a1\),15,1
+ 17c:	3af5d50b          	shia	a0,\(a1\),15,1
+ 180:	2af5d50b          	shib	a0,\(a1\),15,1
+ 184:	5ac5d50b          	swia	a0,\(a1\),12,1
+ 188:	4af5d50b          	swib	a0,\(a1\),15,1
+ 18c:	7af5d50b          	sdia	a0,\(a1\),15,1
+ 190:	6af5d50b          	sdib	a0,\(a1\),15,1
+ 194:	fab6550b          	sdd	a0,a1,\(a2\),1
+ 198:	e2b6550b          	swd	a0,a1,\(a2\),1

gas/testsuite/gas/riscv/extended/theadc-ext.s

@@ -0,0 +1,115 @@
+.text
+
+wsc
+
+# cache ext
+dcache.call
+dcache.ciall
+dcache.cipa a0
+dcache.cisw a0
+dcache.civa a0
+dcache.cpa a0
+dcache.cpal1 a0
+dcache.cva a0
+dcache.cval1 a0
+dcache.ipa a0
+dcache.isw a0
+dcache.iva a0
+dcache.iall
+dcache.csw a0
+icache.iall
+icache.ialls
+icache.iva a0
+icache.ipa a0
+l2cache.iall
+l2cache.call
+l2cache.ciall
+
+# sync ext
+sfence.vmas       a0, a1
+sync
+sync.i
+sync.s
+sync.is
+
+# calc ext
+addsl             a0, a1, a2, 1
+mula              a0, a1, a2
+muls              a0, a1, a2
+mulaw             a0, a1, a2
+mulsw             a0, a1, a2
+mulah             a0, a1, a2
+mulsh             a0, a1, a2
+srri              a0, a1, 16
+srriw             a0, a1, 16
+mveqz             a0, a1, a2
+mvnez             a0, a1, a2
+
+# bit ext
+tst               a0, a1, 16
+tstnbz            a0, a1
+ext               a0, a1, 16, 16
+extu              a0, a1, 16, 16
+ff1               a0, a1
+ff0               a0, a1
+rev               a0, a1
+revw       a0, a1
+
+# load/store ext
+flrd       f0, a0, a1, 1
+flrw       f0, a0, a1, 1
+flurd      f0, a0, a1, 1
+flurw      f0, a0, a1, 1
+lrb               a0, a1, a2, 1
+lrh               a0, a1, a2, 1
+lrw               a0, a1, a2, 1
+lrd               a0, a1, a2, 1
+lrbu              a0, a1, a2, 1
+lrhu              a0, a1, a2, 1
+lrwu              a0, a1, a2, 1
+lurb              a0, a1, a2, 1
+lurh              a0, a1, a2, 1
+lurw              a0, a1, a2, 1
+lurd              a0, a1, a2, 1
+lurbu             a0, a1, a2, 1
+lurhu             a0, a1, a2, 1
+lurwu             a0, a1, a2, 1
+lbia       a0, (a1), 15, 1
+lbib       a0, (a1), 15, 1
+lhia       a0, (a1), 15, 1
+lhib       a0, (a1), 15, 1
+lwia       a0, (a1), 15, 1
+lwib       a0, (a1), 15, 1
+ldia       a0, (a1), 15, 1
+ldib       a0, (a1), 15, 1
+lbuia      a0, (a1), 15, 1
+lbuib      a0, (a1), 15, 1
+lhuia      a0, (a1), 15, 1
+lhuib      a0, (a1), 15, 1
+lwuia      a0, (a1), 15, 1
+lwuib      a0, (a1), 15, 1
+ldd               a0, a1, (a2), 1
+lwd               a0, a1, (a2), 1
+lwud              a0, a1, (a2), 1
+fsrd       f0, a0, a1, 1
+fsrw       f0, a0, a1, 1
+fsurd      f0, a0, a1, 1
+fsurw      f0, a0, a1, 1
+srb               a0, a1, a2, 1
+srh               a0, a1, a2, 1
+srw               a0, a1, a2, 1
+srd               a0, a1, a2, 1
+surb              a0, a1, a2, 1
+surh              a0, a1, a2, 1
+surw              a0, a1, a2, 1
+surd              a0, a1, a2, 1
+sbia              a0, (a1), 15, 1
+sbib              a0, (a1), 15, 1
+shia              a0, (a1), 15, 1
+shib              a0, (a1), 15, 1
+swia              a0, (a1), 12, 1
+swib              a0, (a1), 15, 1
+sdia              a0, (a1), 15, 1
+sdib              a0, (a1), 15, 1
+sdd               a0, a1, (a2), 1
+swd               a0, a1, (a2), 1

gas/testsuite/gas/riscv/extended/theade-ext.d

@@ -0,0 +1,62 @@
+#as: -march=rv32gcxtheade
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+00000000 <.text>:
+[       ]+[0-9a-f]+:\s+cff01073          	csrw	0xcff,zero
+[       ]+[0-9a-f]+:\s+02a5000b          	dcache.ipa	a0
+[       ]+[0-9a-f]+:\s+0295000b          	dcache.cpa	a0
+[       ]+[0-9a-f]+:\s+02b5000b          	dcache.cipa	a0
+[       ]+[0-9a-f]+:\s+0225000b          	dcache.isw	a0
+[       ]+[0-9a-f]+:\s+0215000b          	dcache.csw	a0
+[       ]+[0-9a-f]+:\s+0235000b          	dcache.cisw	a0
+[       ]+[0-9a-f]+:\s+0020000b          	dcache.iall
+[       ]+[0-9a-f]+:\s+0010000b          	dcache.call
+[       ]+[0-9a-f]+:\s+0030000b          	dcache.ciall
+[       ]+[0-9a-f]+:\s+0100000b          	icache.iall
+[       ]+[0-9a-f]+:\s+0385000b          	icache.ipa	a0
+[       ]+[0-9a-f]+:\s+0180000b          	sync
+[       ]+[0-9a-f]+:\s+01a0000b          	sync.i
+[       ]+[0-9a-f]+:\s+02c5950b          	addsl	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+1105950b          	srri	a0,a1,16
+[       ]+[0-9a-f]+:\s+20c5950b          	mula	a0,a1,a2
+[       ]+[0-9a-f]+:\s+28c5950b          	mulah	a0,a1,a2
+[       ]+[0-9a-f]+:\s+22c5950b          	muls	a0,a1,a2
+[       ]+[0-9a-f]+:\s+2ac5950b          	mulsh	a0,a1,a2
+[       ]+[0-9a-f]+:\s+40c5950b          	mveqz	a0,a1,a2
+[       ]+[0-9a-f]+:\s+42c5950b          	mvnez	a0,a1,a2
+[       ]+[0-9a-f]+:\s+4105a50b          	ext	a0,a1,16,16
+[       ]+[0-9a-f]+:\s+4105b50b          	extu	a0,a1,16,16
+[       ]+[0-9a-f]+:\s+8605950b          	ff1	a0,a1
+[       ]+[0-9a-f]+:\s+8405950b          	ff0	a0,a1
+[       ]+[0-9a-f]+:\s+8205950b          	rev	a0,a1
+[       ]+[0-9a-f]+:\s+8905950b          	tst	a0,a1,16
+[       ]+[0-9a-f]+:\s+8005950b          	tstnbz	a0,a1
+[       ]+[0-9a-f]+:\s+02c5c50b          	lrb	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+22c5c50b          	lrh	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+42c5c50b          	lrw	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+82c5c50b          	lrbu	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+a2c5c50b          	lrhu	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+1af5c50b          	lbia	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+0af5c50b          	lbib	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+3af5c50b          	lhia	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+2af5c50b          	lhib	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+5af5c50b          	lwia	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+4af5c50b          	lwib	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+02c5d50b          	srb	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+22c5d50b          	srh	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+42c5d50b          	srw	a0,a1,a2,1
+[       ]+[0-9a-f]+:\s+1af5d50b          	sbia	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+0af5d50b          	sbib	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+3af5d50b          	shia	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+2af5d50b          	shib	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+5ac5d50b          	swia	a0,\(a1\),12,1
+[       ]+[0-9a-f]+:\s+4af5d50b          	swib	a0,\(a1\),15,1
+[       ]+[0-9a-f]+:\s+c000150b          	fmv.x.hw	a0,ft0
+[       ]+[0-9a-f]+:\s+a005100b          	fmv.hw.x	ft0,a0
+[       ]+[0-9a-f]+:\s+0040000b          	ipush
+[       ]+[0-9a-f]+:\s+0050000b          	ipop

gas/testsuite/gas/riscv/extended/theade-ext.s

@@ -0,0 +1,66 @@
+.text
+
+wsc
+
+# cache ext
+dcache.ipa a0
+dcache.cpa a0
+dcache.cipa a0
+dcache.isw a0
+dcache.csw a0
+dcache.cisw a0
+dcache.iall
+dcache.call
+dcache.ciall
+icache.iall
+icache.ipa a0
+
+# sync ext
+sync
+sync.i
+
+# calc ext
+addsl             a0, a1, a2, 1
+srri              a0, a1, 16
+mula              a0, a1, a2
+mulah             a0, a1, a2
+muls              a0, a1, a2
+mulsh             a0, a1, a2
+mveqz             a0, a1, a2
+mvnez             a0, a1, a2
+
+# bit ext
+ext               a0, a1, 16, 16
+extu              a0, a1, 16, 16
+ff1               a0, a1
+ff0               a0, a1
+rev               a0, a1
+tst               a0, a1, 16
+tstnbz            a0, a1
+
+# load/store ext
+lrb               a0, a1, a2, 1
+lrh               a0, a1, a2, 1
+lrw               a0, a1, a2, 1
+lrbu              a0, a1, a2, 1
+lrhu              a0, a1, a2, 1
+lbia       a0, (a1), 15, 1
+lbib       a0, (a1), 15, 1
+lhia       a0, (a1), 15, 1
+lhib       a0, (a1), 15, 1
+lwia       a0, (a1), 15, 1
+lwib       a0, (a1), 15, 1
+srb               a0, a1, a2, 1
+srh               a0, a1, a2, 1
+srw               a0, a1, a2, 1
+sbia              a0, (a1), 15, 1
+sbib              a0, (a1), 15, 1
+shia              a0, (a1), 15, 1
+shib              a0, (a1), 15, 1
+swia              a0, (a1), 12, 1
+swib              a0, (a1), 15, 1
+
+fmv.x.hw   a0, f0
+fmv.hw.x   f0, a0
+ipush
+ipop

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.d

@@ -0,0 +1,3 @@
+#as: -march=rv32iv -mcheck-constraints
+#source: vector-insns-fail-arith-fixp.s
+#error_output: vector-insns-fail-arith-fixp.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.l

@@ -0,0 +1,27 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vm `vsaddu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsaddu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsaddu.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsadd.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsadd.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssubu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssubu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssub.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vaaddu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vaaddu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vaadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vaadd.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vasubu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vasubu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vasub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vasub.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsmul.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsmul.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssrl.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssrl.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssrl.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssra.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssra.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssra.vi v0,v4,31,v0.t'

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.s

@@ -0,0 +1,81 @@
+# Vector Single-Width Saturating Add and Subtract
+
+	vsaddu.vv v4, v4, v8		# OK
+	vsaddu.vv v8, v4, v8		# OK
+	vsaddu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vsaddu.vx v4, v4, a1		# OK
+	vsaddu.vx v0, v4, a1, v0.t	# vd overlap vm
+	vsaddu.vi v4, v4, 15		# OK
+	vsaddu.vi v0, v4, 15, v0.t	# vd overlap vm
+
+	vsadd.vv v4, v4, v8
+	vsadd.vv v8, v4, v8
+	vsadd.vv v0, v4, v8, v0.t
+	vsadd.vx v4, v4, a1
+	vsadd.vx v0, v4, a1, v0.t
+	vsadd.vi v4, v4, 15
+	vsadd.vi v0, v4, 15, v0.t
+
+	vssubu.vv v4, v4, v8		# OK
+	vssubu.vv v8, v4, v8		# OK
+	vssubu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vssubu.vx v4, v4, a1		# OK
+	vssubu.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vssub.vv v4, v4, v8
+	vssub.vv v8, v4, v8
+	vssub.vv v0, v4, v8, v0.t
+	vssub.vx v4, v4, a1
+	vssub.vx v0, v4, a1, v0.t
+
+# Vector Single-Width Averaging Add and Subtract
+
+	vaaddu.vv v4, v4, v8		# OK
+	vaaddu.vv v8, v4, v8		# OK
+	vaaddu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vaaddu.vx v4, v4, a1		# OK
+	vaaddu.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vaadd.vv v4, v4, v8
+	vaadd.vv v8, v4, v8
+	vaadd.vv v0, v4, v8, v0.t
+	vaadd.vx v4, v4, a1
+	vaadd.vx v0, v4, a1, v0.t
+
+	vasubu.vv v4, v4, v8
+	vasubu.vv v8, v4, v8
+	vasubu.vv v0, v4, v8, v0.t
+	vasubu.vx v4, v4, a1
+	vasubu.vx v0, v4, a1, v0.t
+
+	vasub.vv v4, v4, v8
+	vasub.vv v8, v4, v8
+	vasub.vv v0, v4, v8, v0.t
+	vasub.vx v4, v4, a1
+	vasub.vx v0, v4, a1, v0.t
+
+# Vector Single-Width Fractional Multiply with Rounding and Saturation
+
+	vsmul.vv v4, v4, v8		# OK
+	vsmul.vv v8, v4, v8		# OK
+	vsmul.vv v0, v4, v8, v0.t	# vd overlap vm
+	vsmul.vx v4, v4, a1		# OK
+	vsmul.vx v0, v4, a1, v0.t	# vd overlap vm
+
+# Vector Single-Width Scaling Shift Instructions
+
+	vssrl.vv v4, v4, v8		# OK
+	vssrl.vv v8, v4, v8		# OK
+	vssrl.vv v0, v4, v8, v0.t	# vd overlap vm
+	vssrl.vx v4, v4, a1		# OK
+	vssrl.vx v0, v4, a1, v0.t	# vd overlap vm
+	vssrl.vi v4, v4, 31		# OK
+	vssrl.vi v0, v4, 31, v0.t	# vd overlap vm
+
+	vssra.vv v4, v4, v8
+	vssra.vv v8, v4, v8
+	vssra.vv v0, v4, v8, v0.t
+	vssra.vx v4, v4, a1
+	vssra.vx v0, v4, a1, v0.t
+	vssra.vi v4, v4, 31
+	vssra.vi v0, v4, 31, v0.t

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.d

@@ -0,0 +1,3 @@
+#as: -march=rv32ifv -mcheck-constraints
+#source: vector-insns-fail-arith-floatp.s
+#error_output: vector-insns-fail-arith-floatp.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l

@@ -0,0 +1,49 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vm `vfadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfadd.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsub.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfrsub.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmul.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmul.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfdiv.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfdiv.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfrdiv.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmacc.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmacc.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmacc.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmacc.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmsac.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmsac.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmsac.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmsac.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmadd.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmadd.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmsub.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmsub.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsqrt.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfrece7.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfrsqrte7.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfclass.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmin.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmin.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmax.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmax.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfneg.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfabs.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnj.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnj.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnjn.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnjn.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnjx.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnjx.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.xu.f.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.x.f.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.rtz.xu.f.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.rtz.x.f.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.f.xu.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.f.x.v v0,v4,v0.t'

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s

@@ -0,0 +1,157 @@
+# Vector Single-Width Floating-Point Add/Subtract Instructions
+
+	vfadd.vv v4, v4, v8		# OK
+	vfadd.vv v8, v4, v8		# OK
+	vfadd.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfadd.vf v4, v4, fa1		# OK
+	vfadd.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+	vfsub.vv v4, v4, v8
+	vfsub.vv v8, v4, v8
+	vfsub.vv v0, v4, v8, v0.t
+	vfsub.vf v4, v4, fa1
+	vfsub.vf v0, v4, fa1, v0.t
+
+	vfrsub.vf v4, v4, fa1		# OK
+	vfrsub.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+# Vector Single-Width Floating-Point Multiply/Divide Instructions
+
+	vfmul.vv v4, v4, v8		# OK
+	vfmul.vv v8, v4, v8		# OK
+	vfmul.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfmul.vf v4, v4, fa1		# OK
+	vfmul.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+	vfdiv.vv v4, v4, v8
+	vfdiv.vv v8, v4, v8
+	vfdiv.vv v0, v4, v8, v0.t
+	vfdiv.vf v4, v4, fa1
+	vfdiv.vf v0, v4, fa1, v0.t
+
+	vfrdiv.vf v4, v4, fa1		# OK
+	vfrdiv.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+
+	vfmacc.vv v4, v4, v8		# OK
+	vfmacc.vv v8, v4, v8		# OK
+	vfmacc.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfmacc.vf v4, fa1, v4		# OK
+	vfmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
+
+	vfnmacc.vv v4, v4, v8
+	vfnmacc.vv v8, v4, v8
+	vfnmacc.vv v0, v4, v8, v0.t
+	vfnmacc.vf v4, fa1, v4
+	vfnmacc.vf v0, fa1, v4, v0.t
+
+	vfmsac.vv v4, v4, v8
+	vfmsac.vv v8, v4, v8
+	vfmsac.vv v0, v4, v8, v0.t
+	vfmsac.vf v4, fa1, v4
+	vfmsac.vf v0, fa1, v4, v0.t
+
+	vfnmsac.vv v4, v4, v8
+	vfnmsac.vv v8, v4, v8
+	vfnmsac.vv v0, v4, v8, v0.t
+	vfnmsac.vf v4, fa1, v4
+	vfnmsac.vf v0, fa1, v4, v0.t
+
+	vfmadd.vv v4, v4, v8
+	vfmadd.vv v8, v4, v8
+	vfmadd.vv v0, v4, v8, v0.t
+	vfmadd.vf v4, fa1, v4
+	vfmadd.vf v0, fa1, v4, v0.t
+
+	vfnmadd.vv v4, v4, v8
+	vfnmadd.vv v8, v4, v8
+	vfnmadd.vv v0, v4, v8, v0.t
+	vfnmadd.vf v4, fa1, v4
+	vfnmadd.vf v0, fa1, v4, v0.t
+
+	vfmsub.vv v4, v4, v8
+	vfmsub.vv v8, v4, v8
+	vfmsub.vv v0, v4, v8, v0.t
+	vfmsub.vf v4, fa1, v4
+	vfmsub.vf v0, fa1, v4, v0.t
+
+	vfnmsub.vv v4, v4, v8
+	vfnmsub.vv v8, v4, v8
+	vfnmsub.vv v0, v4, v8, v0.t
+	vfnmsub.vf v4, fa1, v4
+	vfnmsub.vf v0, fa1, v4, v0.t
+
+# Vector Floating-Point Square-Root Instruction
+
+	vfsqrt.v v4, v4			# OK
+	vfsqrt.v v0, v4, v0.t		# vd overlap vm
+
+# Vector Floating-Point Reciprocal Estimate Instruction
+
+	vfrece7.v v4, v4		# OK
+	vfrece7.v v0, v4, v0.t		# vd overlap vm
+
+# Vector Floating-Point Reciprocal Square-Root Estimate Instruction
+
+	vfrsqrte7.v v4, v4		# OK
+	vfrsqrte7.v v0, v4, v0.t	# vd overlap vm
+
+# Vector Floating-Point Classify Instruction
+
+	vfclass.v v4, v4		# OK
+	vfclass.v v0, v4, v0.t		# vd overlap vm
+
+# Vector Floating-Point MIN/MAX Instructions
+
+	vfmin.vv v4, v4, v8		# OK
+	vfmin.vv v8, v4, v8		# OK
+	vfmin.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfmin.vf v4, v4, fa1		# OK
+	vfmin.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+	vfmax.vv v4, v4, v8
+	vfmax.vv v8, v4, v8
+	vfmax.vv v0, v4, v8, v0.t
+	vfmax.vf v4, v4, fa1
+	vfmax.vf v0, v4, fa1, v0.t
+
+# Vector Floating-Point Sign-Injection Instructions
+
+	vfneg.v v4, v4			# OK
+	vfneg.v v0, v4, v0.t		# vd overlap vm
+	vfabs.v v4, v4			# OK
+	vfabs.v v0, v4, v0.t		# vd overlap vm
+
+	vfsgnj.vv v4, v4, v8		# OK
+	vfsgnj.vv v8, v4, v8		# OK
+	vfsgnj.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfsgnj.vf v4, v4, fa1		# OK
+	vfsgnj.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+	vfsgnjn.vv v4, v4, v8
+	vfsgnjn.vv v8, v4, v8
+	vfsgnjn.vv v0, v4, v8, v0.t
+	vfsgnjn.vf v4, v4, fa1
+	vfsgnjn.vf v0, v4, fa1, v0.t
+
+	vfsgnjx.vv v4, v4, v8
+	vfsgnjx.vv v8, v4, v8
+	vfsgnjx.vv v0, v4, v8, v0.t
+	vfsgnjx.vf v4, v4, fa1
+	vfsgnjx.vf v0, v4, fa1, v0.t
+
+# Single-Width Floating-Point/Integer Type-Convert Instructions
+
+	vfcvt.xu.f.v v4, v4		# OK
+	vfcvt.xu.f.v v0, v4, v0.t	# vd overlap vm
+	vfcvt.x.f.v v4, v4
+	vfcvt.x.f.v v0, v4, v0.t
+	vfcvt.rtz.xu.f.v v4, v4
+	vfcvt.rtz.xu.f.v v0, v4, v0.t
+	vfcvt.rtz.x.f.v v4, v4
+	vfcvt.rtz.x.f.v v0, v4, v0.t
+	vfcvt.f.xu.v v4, v4
+	vfcvt.f.xu.v v0, v4, v0.t
+	vfcvt.f.x.v v4, v4
+	vfcvt.f.x.v v0, v4, v0.t

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.d

@@ -0,0 +1,3 @@
+#as: -march=rv32iv -mcheck-constraints
+#source: vector-insns-fail-arith-int.s
+#error_output: vector-insns-fail-arith-int.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.l

@@ -0,0 +1,71 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vm `vneg.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vadd.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vadd.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsub.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vrsub.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vrsub.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vzext.vf2 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsext.vf2 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vzext.vf4 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsext.vf4 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vzext.vf8 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsext.vf8 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vadc.vvm v0,v4,v8,v0'
+.*Error: illegal operands vd cannot overlap vm `vadc.vxm v0,v4,a1,v0'
+.*Error: illegal operands vd cannot overlap vm `vadc.vim v0,v4,15,v0'
+.*Error: illegal operands vd cannot overlap vm `vsbc.vvm v0,v4,v8,v0'
+.*Error: illegal operands vd cannot overlap vm `vsbc.vxm v0,v4,a1,v0'
+.*Error: illegal operands vd cannot overlap vm `vnot.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vand.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vand.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vand.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vor.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vor.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vor.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vxor.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vxor.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vxor.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsll.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsll.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsll.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsrl.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsrl.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsrl.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsra.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsra.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsra.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vminu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vminu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmin.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmin.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmaxu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmaxu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmax.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmax.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmul.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmul.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulh.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulh.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulhu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulhu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulhsu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulhsu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vdivu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vdivu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vdiv.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vdiv.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vremu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vremu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vrem.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vrem.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmacc.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmacc.vx v0,a1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vnmsac.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vnmsac.vx v0,a1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmadd.vx v0,a1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vnmsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vnmsub.vx v0,a1,v4,v0.t'

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.s

@@ -0,0 +1,213 @@
+# Vector Single-Width Integer Add and Subtract
+
+	vneg.v v4, v4			# OK
+	vneg.v v0, v4, v0.t		# vd overlap vm
+
+	vadd.vv v4, v4, v8		# OK
+	vadd.vv v8, v4, v8		# OK
+	vadd.vv v0, v4, v8, v0.t	# vd overlap vm
+	vadd.vx v4, v4, a1		# OK
+	vadd.vx v0, v4, a1, v0.t	# vd overlap vm
+	vadd.vi v4, v4, 15		# OK
+	vadd.vi v0, v4, 15, v0.t	# vd overlap vm
+
+	vsub.vv v4, v4, v8		# OK
+	vsub.vv v8, v4, v8		# OK
+	vsub.vv v0, v4, v8, v0.t	# vd overlap vm
+	vsub.vx v4, v4, a1		# OK
+	vsub.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vrsub.vx v4, v4, a1		# OK
+	vrsub.vx v0, v4, a1, v0.t	# vd overlap vm
+	vrsub.vi v4, v4, 15		# OK
+	vrsub.vi v0, v4, 15, v0.t	# vd overlap vm
+
+# Vector Integer Extension
+
+	vzext.vf2 v4, v4		# OK
+	vzext.vf2 v0, v4, v0.t		# vd overlap vm
+	vsext.vf2 v4, v4
+	vsext.vf2 v0, v4, v0.t
+	vzext.vf4 v4, v4
+	vzext.vf4 v0, v4, v0.t
+	vsext.vf4 v4, v4
+	vsext.vf4 v0, v4, v0.t
+	vzext.vf8 v4, v4
+	vzext.vf8 v0, v4, v0.t
+	vsext.vf8 v4, v4
+	vsext.vf8 v0, v4, v0.t
+
+# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+
+	vadc.vvm v4, v4, v8, v0		# OK
+	vadc.vvm v8, v4, v8, v0		# OK
+	vadc.vvm v0, v4, v8, v0		# vd overlap vm
+	vadc.vxm v4, v4, a1, v0		# OK
+	vadc.vxm v0, v4, a1, v0		# vd overlap vm
+	vadc.vim v4, v4, 15, v0		# OK
+	vadc.vim v0, v4, 15, v0		# vd overlap vm
+
+	vsbc.vvm v4, v4, v8, v0		# OK
+	vsbc.vvm v8, v4, v8, v0		# OK
+	vsbc.vvm v0, v4, v8, v0		# vd overlap vm
+	vsbc.vxm v4, v4, a1, v0		# OK
+	vsbc.vxm v0, v4, a1, v0		# vd overlap vm
+
+# Vector Bitwise Logical Instructions
+
+	vnot.v v4, v4			# OK
+	vnot.v v0, v4, v0.t		# vd overlap vm
+
+	vand.vv	v4, v4, v8		# OK
+	vand.vv v8, v4, v8		# OK
+	vand.vv v0, v4, v8, v0.t	# vd overlap vm
+	vand.vx v4, v4, a1		# OK
+	vand.vx v0, v4, a1, v0.t	# vd overlap vm
+	vand.vi v4, v4, 15		# OK
+	vand.vi v0, v4, 15, v0.t	# vd overlap vm
+
+	vor.vv	v4, v4, v8
+	vor.vv v8, v4, v8
+	vor.vv v0, v4, v8, v0.t
+	vor.vx v4, v4, a1
+	vor.vx v0, v4, a1, v0.t
+	vor.vi v4, v4, 15
+	vor.vi v0, v4, 15, v0.t
+
+	vxor.vv	v4, v4, v8
+	vxor.vv v8, v4, v8
+	vxor.vv v0, v4, v8, v0.t
+	vxor.vx v4, v4, a1
+	vxor.vx v0, v4, a1, v0.t
+	vxor.vi v4, v4, 15
+	vxor.vi v0, v4, 15, v0.t
+
+# Vector Single-Width Bit Shift Instructions
+
+	vsll.vv v4, v4, v8		# OK
+	vsll.vv v8, v4, v8		# OK
+	vsll.vv v0, v4, v8, v0.t	# vd overlap vm
+	vsll.vx v4, v4, a1		# OK
+	vsll.vx v0, v4, a1, v0.t	# vd overlap vm
+	vsll.vi v4, v4, 31		# OK
+	vsll.vi v0, v4, 31, v0.t	# vd overlap vm
+
+	vsrl.vv v4, v4, v8
+	vsrl.vv v8, v4, v8
+	vsrl.vv v0, v4, v8, v0.t
+	vsrl.vx v4, v4, a1
+	vsrl.vx v0, v4, a1, v0.t
+	vsrl.vi v4, v4, 31
+	vsrl.vi v0, v4, 31, v0.t
+
+	vsra.vv v4, v4, v8
+	vsra.vv v8, v4, v8
+	vsra.vv v0, v4, v8, v0.t
+	vsra.vx v4, v4, a1
+	vsra.vx v0, v4, a1, v0.t
+	vsra.vi v4, v4, 31
+	vsra.vi v0, v4, 31, v0.t
+
+# Vector Integer Min/Max Instructions
+
+	vminu.vv v4, v4, v8		# OK
+	vminu.vv v8, v4, v8		# OK
+	vminu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vminu.vx v4, v4, a1		# OK
+	vminu.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vmin.vv v4, v4, v8
+	vmin.vv v8, v4, v8
+	vmin.vv v0, v4, v8, v0.t
+	vmin.vx v4, v4, a1
+	vmin.vx v0, v4, a1, v0.t
+
+	vmaxu.vv v4, v4, v8
+	vmaxu.vv v8, v4, v8
+	vmaxu.vv v0, v4, v8, v0.t
+	vmaxu.vx v4, v4, a1
+	vmaxu.vx v0, v4, a1, v0.t
+
+	vmax.vv v4, v4, v8
+	vmax.vv v8, v4, v8
+	vmax.vv v0, v4, v8, v0.t
+	vmax.vx v4, v4, a1
+	vmax.vx v0, v4, a1, v0.t
+
+# Vector Single-Width Integer Multiply Instructions
+
+	vmul.vv v4, v4, v8		# OK
+	vmul.vv v8, v4, v8		# OK
+	vmul.vv v0, v4, v8, v0.t	# vd overlap vm
+	vmul.vx v4, v4, a1		# OK
+	vmul.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vmulh.vv v4, v4, v8
+	vmulh.vv v8, v4, v8
+	vmulh.vv v0, v4, v8, v0.t
+	vmulh.vx v4, v4, a1
+	vmulh.vx v0, v4, a1, v0.t
+
+	vmulhu.vv v4, v4, v8
+	vmulhu.vv v8, v4, v8
+	vmulhu.vv v0, v4, v8, v0.t
+	vmulhu.vx v4, v4, a1
+	vmulhu.vx v0, v4, a1, v0.t
+
+	vmulhsu.vv v4, v4, v8
+	vmulhsu.vv v8, v4, v8
+	vmulhsu.vv v0, v4, v8, v0.t
+	vmulhsu.vx v4, v4, a1
+	vmulhsu.vx v0, v4, a1, v0.t
+
+# Vector Integer Divide Instructions
+
+	vdivu.vv v4, v4, v8		# OK
+	vdivu.vv v8, v4, v8		# OK
+	vdivu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vdivu.vx v4, v4, a1		# OK
+	vdivu.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vdiv.vv v4, v4, v8
+	vdiv.vv v8, v4, v8
+	vdiv.vv v0, v4, v8, v0.t
+	vdiv.vx v4, v4, a1
+	vdiv.vx v0, v4, a1, v0.t
+
+	vremu.vv v4, v4, v8
+	vremu.vv v8, v4, v8
+	vremu.vv v0, v4, v8, v0.t
+	vremu.vx v4, v4, a1
+	vremu.vx v0, v4, a1, v0.t
+
+	vrem.vv v4, v4, v8
+	vrem.vv v8, v4, v8
+	vrem.vv v0, v4, v8, v0.t
+	vrem.vx v4, v4, a1
+	vrem.vx v0, v4, a1, v0.t
+
+# Vector Single-Width Integer Multiply-Add Instructions
+
+	vmacc.vv v4, v4, v8		# OK
+	vmacc.vv v8, v4, v8		# OK
+	vmacc.vv v0, v4, v8, v0.t	# vd overlap vm
+	vmacc.vx v4, a1, v4		# OK
+	vmacc.vx v0, a1, v4, v0.t	# vd overlap vm
+
+	vnmsac.vv v4, v4, v8
+	vnmsac.vv v8, v4, v8
+	vnmsac.vv v0, v4, v8, v0.t
+	vnmsac.vx v4, a1, v4
+	vnmsac.vx v0, a1, v4, v0.t
+
+	vmadd.vv v4, v4, v8
+	vmadd.vv v8, v4, v8
+	vmadd.vv v0, v4, v8, v0.t
+	vmadd.vx v4, a1, v4
+	vmadd.vx v0, a1, v4, v0.t
+
+	vnmsub.vv v4, v4, v8
+	vnmsub.vv v8, v4, v8
+	vnmsub.vv v0, v4, v8, v0.t
+	vnmsub.vx v4, a1, v4
+	vnmsub.vx v0, a1, v4, v0.t

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.d

@@ -0,0 +1,3 @@
+#as: -march=rv32ifv -mcheck-constraints
+#source: vector-insns-fail-arith-widen.s
+#error_output: vector-insns-fail-arith-widen.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l

@@ -0,0 +1,122 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vs2 `vwcvtu.x.x.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vwcvtu.x.x.v v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwcvt.x.x.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vwcvt.x.x.v v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwaddu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwaddu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vwaddu.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vwaddu.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwaddu.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vwaddu.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsubu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwsubu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vwsubu.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vwsubu.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwsubu.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vwsubu.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwadd.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwadd.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwadd.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwadd.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vwadd.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vwadd.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwadd.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vwadd.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwsub.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsub.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwsub.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwsub.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vwsub.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vwsub.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwsub.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vwsub.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmul.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmul.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwmul.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmul.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vwmul.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmulu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwmulu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vwmulu.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmulsu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwmulsu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vwmulsu.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vwmaccu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwmaccu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vx v2,a1,v2'
+.*Error: illegal operands vd cannot overlap vm `vwmaccu.vx v0,a1,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vwmacc.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwmacc.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vx v2,a1,v2'
+.*Error: illegal operands vd cannot overlap vm `vwmacc.vx v0,a1,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vwmaccsu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vwmaccsu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vx v2,a1,v2'
+.*Error: illegal operands vd cannot overlap vm `vwmaccsu.vx v0,a1,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccus.vx v2,a1,v2'
+.*Error: illegal operands vd cannot overlap vm `vwmaccus.vx v0,a1,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwadd.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwadd.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vf v2,v2,fa1'
+.*Error: illegal operands vd cannot overlap vm `vfwadd.vf v0,v2,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vfwadd.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwadd.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwsub.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwsub.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v2,fa1'
+.*Error: illegal operands vd cannot overlap vm `vfwsub.vf v0,v2,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vfwsub.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwsub.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmul.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmul.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwmul.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v2,fa1'
+.*Error: illegal operands vd cannot overlap vm `vfwsub.vf v0,v2,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmacc.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwmacc.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vf v2,fa1,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwmacc.vf v0,fa1,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vfwnmacc.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwnmacc.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vf v2,fa1,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwnmacc.vf v0,fa1,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmsac.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwmsac.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vf v2,fa1,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwmsac.vf v0,fa1,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs1 `vfwnmsac.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vfwnmsac.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vf v2,fa1,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwnmsac.vf v0,fa1,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.xu.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.xu.f.v v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.x.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.x.f.v v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.xu.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.x.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.rtz.x.f.v v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.xu.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.xu.v v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.x.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.x.v v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.f.v v0,v2,v0.t'

gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s

@@ -0,0 +1,297 @@
+# Vector Widening Integer Add/Subtract
+
+	# vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm
+	vwcvtu.x.x.v v1, v2		# OK since fractional LMUL.  vd should be multiple of 2
+	vwcvtu.x.x.v v2, v2		# vd overlap vs2
+	vwcvtu.x.x.v v2, v3		# OK since fractional LMUL.  vd overlap vs2
+	vwcvtu.x.x.v v0, v2, v0.t	# vd overlap vm
+
+	# vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm
+	vwcvt.x.x.v v1, v2
+	vwcvt.x.x.v v2, v2
+	vwcvt.x.x.v v2, v3
+	vwcvt.x.x.v v0, v2, v0.t
+
+	vwaddu.vv v1, v2, v4		# OK since fractional LMUL.  vd should be multiple of 2
+	vwaddu.vv v2, v2, v4		# vd overlap vs2
+	vwaddu.vv v2, v3, v4		# OK since fractional LMUL.  vd overlap vs2
+	vwaddu.vv v4, v2, v4		# vd overlap vs1
+	vwaddu.vv v4, v2, v5		# OK since fractional LMUL.  vd overlap vs1
+	vwaddu.vv v0, v2, v4, v0.t	# vd overlap vm
+	vwaddu.vx v1, v2, a1		# OK since fractional LMUL.  vd should be multiple of 2
+	vwaddu.vx v2, v2, a1		# vd overlap vs2
+	vwaddu.vx v2, v3, a1		# OK since fractional LMUL.  vd overlap vs2
+	vwaddu.vx v0, v2, a1, v0.t	# vd overlap vm
+	vwaddu.wv v1, v2, v4		# OK since fractional LMUL.  vd should be multiple of 2
+	vwaddu.wv v2, v2, v4		# OK
+	vwaddu.wv v2, v3, v4		# OK since fractional LMUL.  vs2 should be multiple of 2
+	vwaddu.wv v4, v2, v4		# vd overlap vs1
+	vwaddu.wv v4, v2, v5		# OK since fractional LMUL.  vd overlap vs1
+	vwaddu.wv v0, v2, v4, v0.t	# vd overlap vm
+	vwaddu.wx v1, v2, a1		# OK since fractional LMUL.  vd should be multiple of 2
+	vwaddu.wx v2, v2, a1		# OK
+	vwaddu.wx v2, v3, a1		# OK since fractional LMUL.  vs2 should be multiple of 2
+	vwaddu.wx v0, v2, a1, v0.t	# vd overlap vm
+
+	vwsubu.vv v1, v2, v4
+	vwsubu.vv v2, v2, v4
+	vwsubu.vv v2, v3, v4
+	vwsubu.vv v4, v2, v4
+	vwsubu.vv v4, v2, v5
+	vwsubu.vv v0, v2, v4, v0.t
+	vwsubu.vx v1, v2, a1
+	vwsubu.vx v2, v2, a1
+	vwsubu.vx v2, v3, a1
+	vwsubu.vx v0, v2, a1, v0.t
+	vwsubu.wv v1, v2, v4
+	vwsubu.wv v2, v2, v4
+	vwsubu.wv v2, v3, v4
+	vwsubu.wv v4, v2, v4
+	vwsubu.wv v4, v2, v5
+	vwsubu.wv v0, v2, v4, v0.t
+	vwsubu.wx v1, v2, a1
+	vwsubu.wx v2, v2, a1
+	vwsubu.wx v2, v3, a1
+	vwsubu.wx v0, v2, a1, v0.t
+
+	vwadd.vv v1, v2, v4
+	vwadd.vv v2, v2, v4
+	vwadd.vv v2, v3, v4
+	vwadd.vv v4, v2, v4
+	vwadd.vv v4, v2, v5
+	vwadd.vv v0, v2, v4, v0.t
+	vwadd.vx v1, v2, a1
+	vwadd.vx v2, v2, a1
+	vwadd.vx v2, v3, a1
+	vwadd.vx v0, v2, a1, v0.t
+	vwadd.wv v1, v2, v4
+	vwadd.wv v2, v2, v4
+	vwadd.wv v2, v3, v4
+	vwadd.wv v4, v2, v4
+	vwadd.wv v4, v2, v5
+	vwadd.wv v0, v2, v4, v0.t
+	vwadd.wx v1, v2, a1
+	vwadd.wx v2, v2, a1
+	vwadd.wx v2, v3, a1
+	vwadd.wx v0, v2, a1, v0.t
+
+	vwsub.vv v1, v2, v4
+	vwsub.vv v2, v2, v4
+	vwsub.vv v2, v3, v4
+	vwsub.vv v4, v2, v4
+	vwsub.vv v4, v2, v5
+	vwsub.vv v0, v2, v4, v0.t
+	vwsub.vx v1, v2, a1
+	vwsub.vx v2, v2, a1
+	vwsub.vx v2, v3, a1
+	vwsub.vx v0, v2, a1, v0.t
+	vwsub.wv v1, v2, v4
+	vwsub.wv v2, v2, v4
+	vwsub.wv v2, v3, v4
+	vwsub.wv v4, v2, v4
+	vwsub.wv v4, v2, v5
+	vwsub.wv v0, v2, v4, v0.t
+	vwsub.wx v1, v2, a1
+	vwsub.wx v2, v2, a1
+	vwsub.wx v2, v3, a1
+	vwsub.wx v0, v2, a1, v0.t
+
+# Vector Widening Integer Multiply Instructions
+
+	vwmul.vv v1, v2, v4		# OK since fractional LMUL.  vd should be multiple of 2
+	vwmul.vv v2, v2, v4		# vd overlap vs2
+	vwmul.vv v2, v3, v4		# OK since fractional LMUL.  vd overlap vs2
+	vwmul.vv v4, v2, v4		# vd overlap vs1
+	vwmul.vv v4, v2, v5		# OK since fractional LMUL.  vd overlap vs1
+	vwmul.vv v0, v2, v4, v0.t	# vd overlap vm
+	vwmul.vx v1, v2, a1		# OK since fractional LMUL.  vd should be multiple of 2
+	vwmul.vx v2, v2, a1		# vd overlap vs2
+	vwmul.vx v2, v3, a1		# OK since fractional LMUL.  vd overlap vs2
+	vwmul.vx v0, v2, a1, v0.t	# vd overlap vm
+
+	vwmulu.vv v1, v2, v4
+	vwmulu.vv v2, v2, v4
+	vwmulu.vv v2, v3, v4
+	vwmulu.vv v4, v2, v4
+	vwmulu.vv v4, v2, v5
+	vwmulu.vv v0, v2, v4, v0.t
+	vwmulu.vx v1, v2, a1
+	vwmulu.vx v2, v2, a1
+	vwmulu.vx v2, v3, a1
+	vwmulu.vx v0, v2, a1, v0.t
+
+	vwmulsu.vv v1, v2, v4
+	vwmulsu.vv v2, v2, v4
+	vwmulsu.vv v2, v3, v4
+	vwmulsu.vv v4, v2, v4
+	vwmulsu.vv v4, v2, v5
+	vwmulsu.vv v0, v2, v4, v0.t
+	vwmulsu.vx v1, v2, a1
+	vwmulsu.vx v2, v2, a1
+	vwmulsu.vx v2, v3, a1
+	vwmulsu.vx v0, v2, a1, v0.t
+
+# Vector Widening Integer Multiply-Add Instructions
+
+	vwmaccu.vv v1, v2, v4		# OK since fractional LMUL.  vd should be multiple of 2
+	vwmaccu.vv v2, v2, v4		# vd overlap vs1
+	vwmaccu.vv v2, v3, v4		# OK since fractional LMUL.  vd overlap vs1
+	vwmaccu.vv v4, v2, v4		# vd overlap vs2
+	vwmaccu.vv v4, v2, v5		# OK since fractional LMUL.  vd overlap vs2
+	vwmaccu.vv v0, v2, v4, v0.t	# vd overlap vm
+	vwmaccu.vx v1, a1, v2		# OK since fractional LMUL.  vd should be multiple of 2
+	vwmaccu.vx v2, a1, v2		# vd overlap vs2
+	vwmaccu.vx v2, a1, v3		# OK since fractional LMUL.  vd overlap vs2
+	vwmaccu.vx v0, a1, v2, v0.t	# vd overlap vm
+
+	vwmacc.vv v1, v2, v4
+	vwmacc.vv v2, v2, v4
+	vwmacc.vv v2, v3, v4
+	vwmacc.vv v4, v2, v4
+	vwmacc.vv v4, v2, v5
+	vwmacc.vv v0, v2, v4, v0.t
+	vwmacc.vx v1, a1, v2
+	vwmacc.vx v2, a1, v2
+	vwmacc.vx v2, a1, v3
+	vwmacc.vx v0, a1, v2, v0.t
+
+	vwmaccsu.vv v1, v2, v4
+	vwmaccsu.vv v2, v2, v4
+	vwmaccsu.vv v2, v3, v4
+	vwmaccsu.vv v4, v2, v4
+	vwmaccsu.vv v4, v2, v5
+	vwmaccsu.vv v0, v2, v4, v0.t
+	vwmaccsu.vx v1, a1, v2
+	vwmaccsu.vx v2, a1, v2
+	vwmaccsu.vx v2, a1, v3
+	vwmaccsu.vx v0, a1, v2, v0.t
+
+	vwmaccus.vx v1, a1, v2		# OK since fractional LMUL.  vd should be multiple of 2
+	vwmaccus.vx v2, a1, v2		# vd overlap vs2
+	vwmaccus.vx v2, a1, v3		# OK since fractional LMUL.  vd overlap vs2
+	vwmaccus.vx v0, a1, v2, v0.t	# vd overlap vm
+
+# Vector Widening Floating-Point Add/Subtract Instructions
+
+	vfwadd.vv v1, v2, v4		# OK since fractional LMUL.  vd should be multiple of 2
+	vfwadd.vv v2, v2, v4		# vd overlap vs2
+	vfwadd.vv v2, v3, v4		# OK since fractional LMUL.  vd overlap vs2
+	vfwadd.vv v4, v2, v4		# vd overlap vs1
+	vfwadd.vv v4, v2, v5		# OK since fractional LMUL.  vd overlap vs1
+	vfwadd.vv v0, v2, v4, v0.t	# vd overlap vm
+	vfwadd.vf v1, v2, fa1		# OK since fractional LMUL.  vd should be multiple of 2
+	vfwadd.vf v2, v2, fa1		# vd overlap vs2
+	vfwadd.vf v2, v3, fa1		# OK since fractional LMUL.  vd overlap vs2
+	vfwadd.vf v0, v2, fa1, v0.t	# vd overlap vm
+	vfwadd.wv v1, v2, v4		# OK since fractional LMUL.  vd should be multiple of 2
+	vfwadd.wv v2, v2, v4		# OK
+	vfwadd.wv v2, v3, v4		# OK since fractional LMUL.  vs2 should be multiple of 2
+	vfwadd.wv v4, v2, v4		# vd overlap vs1
+	vfwadd.wv v4, v2, v5		# OK since fractional LMUL.  vd overlap vs1
+	vfwadd.wv v0, v2, v4, v0.t	# vd overlap vm
+
+	vfwsub.vv v1, v2, v4
+	vfwsub.vv v2, v2, v4
+	vfwsub.vv v2, v3, v4
+	vfwsub.vv v4, v2, v4
+	vfwsub.vv v4, v2, v5
+	vfwsub.vv v0, v2, v4, v0.t
+	vfwsub.vf v1, v2, fa1
+	vfwsub.vf v2, v2, fa1
+	vfwsub.vf v2, v3, fa1
+	vfwsub.vf v0, v2, fa1, v0.t
+	vfwsub.wv v1, v2, v4
+	vfwsub.wv v2, v2, v4
+	vfwsub.wv v2, v3, v4
+	vfwsub.wv v4, v2, v4
+	vfwsub.wv v4, v2, v5
+	vfwsub.wv v0, v2, v4, v0.t
+
+# Vector Widening Floating-Point Multiply
+
+	vfwmul.vv v1, v2, v4		# OK since fractional LMUL.  vd should be multiple of 2
+	vfwmul.vv v2, v2, v4		# vd overlap vs2
+	vfwmul.vv v2, v3, v4		# OK since fractional LMUL.  vd overlap vs2
+	vfwmul.vv v4, v2, v4		# vd overlap vs1
+	vfwmul.vv v4, v2, v5		# OK since fractional LMUL.  vd overlap vs1
+	vfwmul.vv v0, v2, v4, v0.t	# vd overlap vm
+	vfwsub.vf v1, v2, fa1		# OK since fractional LMUL.  vd should be multiple of 2
+	vfwsub.vf v2, v2, fa1		# vd overlap vs2
+	vfwsub.vf v2, v3, fa1		# OK since fractional LMUL.  vd overlap vs2
+	vfwsub.vf v0, v2, fa1, v0.t	# vd overlap vm
+
+# Vector Widening Floating-Point Fused Multiply-Add Instructions
+	vfwmacc.vv v1, v2, v4		# OK since fractional LMUL.  vd should be multiple of 2
+	vfwmacc.vv v2, v2, v4		# vd overlap vs1
+	vfwmacc.vv v2, v3, v4		# OK since fractional LMUL.  vd overlap vs1
+	vfwmacc.vv v4, v2, v4		# vd overlap vs2
+	vfwmacc.vv v4, v2, v5		# OK since fractional LMUL.  vd overlap vs2
+	vfwmacc.vv v0, v2, v4, v0.t	# vd overlap vm
+	vfwmacc.vf v1, fa1, v2		# OK since fractional LMUL.  vd should be multiple of 2
+	vfwmacc.vf v2, fa1, v2		# vd overlap vs2
+	vfwmacc.vf v2, fa1, v3		# OK since fractional LMUL.  vd overlap vs2
+	vfwmacc.vf v0, fa1, v2, v0.t	# vd overlap vm
+
+	vfwnmacc.vv v1, v2, v4
+	vfwnmacc.vv v2, v2, v4
+	vfwnmacc.vv v2, v3, v4
+	vfwnmacc.vv v4, v2, v4
+	vfwnmacc.vv v4, v2, v5
+	vfwnmacc.vv v0, v2, v4, v0.t
+	vfwnmacc.vf v1, fa1, v2
+	vfwnmacc.vf v2, fa1, v2
+	vfwnmacc.vf v2, fa1, v3
+	vfwnmacc.vf v0, fa1, v2, v0.t
+
+	vfwmsac.vv v1, v2, v4
+	vfwmsac.vv v2, v2, v4
+	vfwmsac.vv v2, v3, v4
+	vfwmsac.vv v4, v2, v4
+	vfwmsac.vv v4, v2, v5
+	vfwmsac.vv v0, v2, v4, v0.t
+	vfwmsac.vf v1, fa1, v2
+	vfwmsac.vf v2, fa1, v2
+	vfwmsac.vf v2, fa1, v3
+	vfwmsac.vf v0, fa1, v2, v0.t
+
+	vfwnmsac.vv v1, v2, v4
+	vfwnmsac.vv v2, v2, v4
+	vfwnmsac.vv v2, v3, v4
+	vfwnmsac.vv v4, v2, v4
+	vfwnmsac.vv v4, v2, v5
+	vfwnmsac.vv v0, v2, v4, v0.t
+	vfwnmsac.vf v1, fa1, v2
+	vfwnmsac.vf v2, fa1, v2
+	vfwnmsac.vf v2, fa1, v3
+	vfwnmsac.vf v0, fa1, v2, v0.t
+
+# Widening Floating-Point/Integer Type-Convert Instructions
+
+	vfwcvt.xu.f.v v1, v2		# OK since fractional LMUL.  vd should be multiple of 2
+	vfwcvt.xu.f.v v2, v2		# vd overlap vs2
+	vfwcvt.xu.f.v v2, v3		# OK since fractional LMUL.  vd overlap vs2
+	vfwcvt.xu.f.v v0, v2, v0.t	# vd overlap vm
+	vfwcvt.x.f.v v1, v2
+	vfwcvt.x.f.v v2, v2
+	vfwcvt.x.f.v v2, v3
+	vfwcvt.x.f.v v0, v2, v0.t
+	vfwcvt.rtz.xu.f.v v1, v2
+	vfwcvt.rtz.xu.f.v v2, v2
+	vfwcvt.rtz.xu.f.v v2, v3
+	vfwcvt.rtz.xu.f.v v0, v2, v0.t
+	vfwcvt.rtz.x.f.v v1, v2
+	vfwcvt.rtz.x.f.v v2, v2
+	vfwcvt.rtz.x.f.v v2, v3
+	vfwcvt.rtz.x.f.v v0, v2, v0.t
+	vfwcvt.f.xu.v v1, v2
+	vfwcvt.f.xu.v v2, v2
+	vfwcvt.f.xu.v v2, v3
+	vfwcvt.f.xu.v v0, v2, v0.t
+	vfwcvt.f.x.v v1, v2
+	vfwcvt.f.x.v v2, v2
+	vfwcvt.f.x.v v2, v3
+	vfwcvt.f.x.v v0, v2, v0.t
+	vfwcvt.f.f.v v1, v2
+	vfwcvt.f.f.v v2, v2
+	vfwcvt.f.f.v v2, v3
+	vfwcvt.f.f.v v0, v2, v0.t

gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.d

@@ -0,0 +1,3 @@
+#as: -march=rv32iv -mcheck-constraints
+#source: vector-insns-fail-load-store.s
+#error_output: vector-insns-fail-load-store.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.l

@@ -0,0 +1,419 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vm `vle8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vse8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vse16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vse32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vse64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlse8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlse16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlse32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlse64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsse8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsse16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsse32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsse64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vloxei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vloxei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vloxei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vloxei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsoxei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsoxei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsoxei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsoxei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vluxei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vluxei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vluxei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vluxei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsuxei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsuxei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsuxei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsuxei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg2e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg3e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg4e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg5e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg6e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg7e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg8e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg2e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg3e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg4e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg5e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg6e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg7e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg8e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg2e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg3e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg4e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg5e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg6e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg7e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg8e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg2e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg3e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg4e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg5e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg6e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg7e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg8e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg2e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg2e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg3e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg3e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg4e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg4e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg5e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg5e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg6e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg6e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg7e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg7e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg8e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg8e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg2e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg2e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg3e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg3e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg4e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg4e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg5e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg5e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg6e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg6e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg7e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg7e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg8e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg8e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg2e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg2e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg3e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg3e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg4e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg4e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg5e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg5e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg6e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg6e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg7e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg7e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg8e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg8e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg2e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg2e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg3e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg3e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg4e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg4e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg5e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg5e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg6e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg6e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg7e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg7e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg8e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg8e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg2ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg3ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg4ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg5ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg6ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg7ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg8ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg2ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg3ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg4ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg5ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg6ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg7ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg8ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg2ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg3ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg4ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg5ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg6ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg7ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg8ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg2ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg3ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg4ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg5ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg6ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg7ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg8ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg2ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg3ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg4ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg5ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg6ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg7ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg8ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg2ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg3ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg4ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg5ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg6ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg7ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg8ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg2ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg3ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg4ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg5ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg6ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg7ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg8ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg2ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg3ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg4ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg5ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg6ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg7ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg8ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd must be multiple of nf `vl2r.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl2re8.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl2re16.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl2re32.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl2re64.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4r.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4re8.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4re16.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4re32.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4re64.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8r.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8re8.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8re16.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8re32.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8re64.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vs2r.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vs4r.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vs8r.v v26,\(a0\)'

gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.s

@@ -0,0 +1,481 @@
+# Vector Unit-Stride Loads and Stores
+
+	vle8.v v0, (a0), v0.t		# vd overlap vm
+	vle8ff.v v0, (a0), v0.t		# vd overlap vm
+	vle16.v v0, (a0), v0.t
+	vle16ff.v v0, (a0), v0.t
+	vle32.v v0, (a0), v0.t
+	vle32ff.v v0, (a0), v0.t
+	vle64.v v0, (a0), v0.t
+	vle64ff.v v0, (a0), v0.t
+
+	vse8.v v0, (a0), v0.t		# vd overlap vm
+	vse16.v v0, (a0), v0.t
+	vse32.v v0, (a0), v0.t
+	vse64.v v0, (a0), v0.t
+
+# Vector Strided Loads and Stores
+
+	vlse8.v v0, (a0), a1, v0.t	# vd overlap vm
+	vlse16.v v0, (a0), a1, v0.t
+	vlse32.v v0, (a0), a1, v0.t
+	vlse64.v v0, (a0), a1, v0.t
+
+	vsse8.v v0, (a0), a1, v0.t
+	vsse16.v v0, (a0), a1, v0.t
+	vsse32.v v0, (a0), a1, v0.t
+	vsse64.v v0, (a0), a1, v0.t
+
+# Vector Ordered Indexed Loads and Stores
+
+	vloxei8.v v4, (a0), v4		# OK
+	vloxei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vloxei16.v v4, (a0), v4
+	vloxei16.v v0, (a0), v4, v0.t
+	vloxei32.v v4, (a0), v4
+	vloxei32.v v0, (a0), v4, v0.t
+	vloxei64.v v4, (a0), v4
+	vloxei64.v v0, (a0), v4, v0.t
+
+	vsoxei8.v v4, (a0), v4
+	vsoxei8.v v0, (a0), v4, v0.t
+	vsoxei16.v v4, (a0), v4
+	vsoxei16.v v0, (a0), v4, v0.t
+	vsoxei32.v v4, (a0), v4
+	vsoxei32.v v0, (a0), v4, v0.t
+	vsoxei64.v v4, (a0), v4
+	vsoxei64.v v0, (a0), v4, v0.t
+
+# Vector Unordered Indexed Loads and Stores
+
+	vluxei8.v v4, (a0), v4		# OK
+	vluxei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vluxei16.v v4, (a0), v4
+	vluxei16.v v0, (a0), v4, v0.t
+	vluxei32.v v4, (a0), v4
+	vluxei32.v v0, (a0), v4, v0.t
+	vluxei64.v v4, (a0), v4
+	vluxei64.v v0, (a0), v4, v0.t
+
+	vsuxei8.v v4, (a0), v4
+	vsuxei8.v v0, (a0), v4, v0.t
+	vsuxei16.v v4, (a0), v4
+	vsuxei16.v v0, (a0), v4, v0.t
+	vsuxei32.v v4, (a0), v4
+	vsuxei32.v v0, (a0), v4, v0.t
+	vsuxei64.v v4, (a0), v4
+	vsuxei64.v v0, (a0), v4, v0.t
+
+# Vector Unit-Stride Segment Loads and Stores
+
+	vlseg2e8.v v0, (a0), v0.t	# vd overlap vm
+	vsseg2e8.v v0, (a0), v0.t	# vd overlap vm
+	vlseg2e8ff.v v0, (a0), v0.t	# vd overlap vm
+	vlseg3e8.v v0, (a0), v0.t
+	vsseg3e8.v v0, (a0), v0.t
+	vlseg3e8ff.v v0, (a0), v0.t
+	vlseg4e8.v v0, (a0), v0.t
+	vsseg4e8.v v0, (a0), v0.t
+	vlseg4e8ff.v v0, (a0), v0.t
+	vlseg5e8.v v0, (a0), v0.t
+	vsseg5e8.v v0, (a0), v0.t
+	vlseg5e8ff.v v0, (a0), v0.t
+	vlseg6e8.v v0, (a0), v0.t
+	vsseg6e8.v v0, (a0), v0.t
+	vlseg6e8ff.v v0, (a0), v0.t
+	vlseg7e8.v v0, (a0), v0.t
+	vsseg7e8.v v0, (a0), v0.t
+	vlseg7e8ff.v v0, (a0), v0.t
+	vlseg8e8.v v0, (a0), v0.t
+	vsseg8e8.v v0, (a0), v0.t
+	vlseg8e8ff.v v0, (a0), v0.t
+
+	vlseg2e16.v v0, (a0), v0.t
+	vsseg2e16.v v0, (a0), v0.t
+	vlseg2e16ff.v v0, (a0), v0.t
+	vlseg3e16.v v0, (a0), v0.t
+	vsseg3e16.v v0, (a0), v0.t
+	vlseg3e16ff.v v0, (a0), v0.t
+	vlseg4e16.v v0, (a0), v0.t
+	vsseg4e16.v v0, (a0), v0.t
+	vlseg4e16ff.v v0, (a0), v0.t
+	vlseg5e16.v v0, (a0), v0.t
+	vsseg5e16.v v0, (a0), v0.t
+	vlseg5e16ff.v v0, (a0), v0.t
+	vlseg6e16.v v0, (a0), v0.t
+	vsseg6e16.v v0, (a0), v0.t
+	vlseg6e16ff.v v0, (a0), v0.t
+	vlseg7e16.v v0, (a0), v0.t
+	vsseg7e16.v v0, (a0), v0.t
+	vlseg7e16ff.v v0, (a0), v0.t
+	vlseg8e16.v v0, (a0), v0.t
+	vsseg8e16.v v0, (a0), v0.t
+	vlseg8e16ff.v v0, (a0), v0.t
+
+	vlseg2e32.v v0, (a0), v0.t
+	vsseg2e32.v v0, (a0), v0.t
+	vlseg2e32ff.v v0, (a0), v0.t
+	vlseg3e32.v v0, (a0), v0.t
+	vsseg3e32.v v0, (a0), v0.t
+	vlseg3e32ff.v v0, (a0), v0.t
+	vlseg4e32.v v0, (a0), v0.t
+	vsseg4e32.v v0, (a0), v0.t
+	vlseg4e32ff.v v0, (a0), v0.t
+	vlseg5e32.v v0, (a0), v0.t
+	vsseg5e32.v v0, (a0), v0.t
+	vlseg5e32ff.v v0, (a0), v0.t
+	vlseg6e32.v v0, (a0), v0.t
+	vsseg6e32.v v0, (a0), v0.t
+	vlseg6e32ff.v v0, (a0), v0.t
+	vlseg7e32.v v0, (a0), v0.t
+	vsseg7e32.v v0, (a0), v0.t
+	vlseg7e32ff.v v0, (a0), v0.t
+	vlseg8e32.v v0, (a0), v0.t
+	vsseg8e32.v v0, (a0), v0.t
+	vlseg8e32ff.v v0, (a0), v0.t
+
+	vlseg2e64.v v0, (a0), v0.t
+	vsseg2e64.v v0, (a0), v0.t
+	vlseg2e64ff.v v0, (a0), v0.t
+	vlseg3e64.v v0, (a0), v0.t
+	vsseg3e64.v v0, (a0), v0.t
+	vlseg3e64ff.v v0, (a0), v0.t
+	vlseg4e64.v v0, (a0), v0.t
+	vsseg4e64.v v0, (a0), v0.t
+	vlseg4e64ff.v v0, (a0), v0.t
+	vlseg5e64.v v0, (a0), v0.t
+	vsseg5e64.v v0, (a0), v0.t
+	vlseg5e64ff.v v0, (a0), v0.t
+	vlseg6e64.v v0, (a0), v0.t
+	vsseg6e64.v v0, (a0), v0.t
+	vlseg6e64ff.v v0, (a0), v0.t
+	vlseg7e64.v v0, (a0), v0.t
+	vsseg7e64.v v0, (a0), v0.t
+	vlseg7e64ff.v v0, (a0), v0.t
+	vlseg8e64.v v0, (a0), v0.t
+	vsseg8e64.v v0, (a0), v0.t
+	vlseg8e64ff.v v0, (a0), v0.t
+
+# Vector Strided Segment Loads and Stores
+
+	vlsseg2e8.v v0, (a0), a1, v0.t		# vd overlap vm
+	vssseg2e8.v v0, (a0), a1, v0.t		# vd overlap vm
+	vlsseg3e8.v v0, (a0), a1, v0.t
+	vssseg3e8.v v0, (a0), a1, v0.t
+	vlsseg4e8.v v0, (a0), a1, v0.t
+	vssseg4e8.v v0, (a0), a1, v0.t
+	vlsseg5e8.v v0, (a0), a1, v0.t
+	vssseg5e8.v v0, (a0), a1, v0.t
+	vlsseg6e8.v v0, (a0), a1, v0.t
+	vssseg6e8.v v0, (a0), a1, v0.t
+	vlsseg7e8.v v0, (a0), a1, v0.t
+	vssseg7e8.v v0, (a0), a1, v0.t
+	vlsseg8e8.v v0, (a0), a1, v0.t
+	vssseg8e8.v v0, (a0), a1, v0.t
+
+	vlsseg2e16.v v0, (a0), a1, v0.t
+	vssseg2e16.v v0, (a0), a1, v0.t
+	vlsseg3e16.v v0, (a0), a1, v0.t
+	vssseg3e16.v v0, (a0), a1, v0.t
+	vlsseg4e16.v v0, (a0), a1, v0.t
+	vssseg4e16.v v0, (a0), a1, v0.t
+	vlsseg5e16.v v0, (a0), a1, v0.t
+	vssseg5e16.v v0, (a0), a1, v0.t
+	vlsseg6e16.v v0, (a0), a1, v0.t
+	vssseg6e16.v v0, (a0), a1, v0.t
+	vlsseg7e16.v v0, (a0), a1, v0.t
+	vssseg7e16.v v0, (a0), a1, v0.t
+	vlsseg8e16.v v0, (a0), a1, v0.t
+	vssseg8e16.v v0, (a0), a1, v0.t
+
+	vlsseg2e32.v v0, (a0), a1, v0.t
+	vssseg2e32.v v0, (a0), a1, v0.t
+	vlsseg3e32.v v0, (a0), a1, v0.t
+	vssseg3e32.v v0, (a0), a1, v0.t
+	vlsseg4e32.v v0, (a0), a1, v0.t
+	vssseg4e32.v v0, (a0), a1, v0.t
+	vlsseg5e32.v v0, (a0), a1, v0.t
+	vssseg5e32.v v0, (a0), a1, v0.t
+	vlsseg6e32.v v0, (a0), a1, v0.t
+	vssseg6e32.v v0, (a0), a1, v0.t
+	vlsseg7e32.v v0, (a0), a1, v0.t
+	vssseg7e32.v v0, (a0), a1, v0.t
+	vlsseg8e32.v v0, (a0), a1, v0.t
+	vssseg8e32.v v0, (a0), a1, v0.t
+
+	vlsseg2e64.v v0, (a0), a1, v0.t
+	vssseg2e64.v v0, (a0), a1, v0.t
+	vlsseg3e64.v v0, (a0), a1, v0.t
+	vssseg3e64.v v0, (a0), a1, v0.t
+	vlsseg4e64.v v0, (a0), a1, v0.t
+	vssseg4e64.v v0, (a0), a1, v0.t
+	vlsseg5e64.v v0, (a0), a1, v0.t
+	vssseg5e64.v v0, (a0), a1, v0.t
+	vlsseg6e64.v v0, (a0), a1, v0.t
+	vssseg6e64.v v0, (a0), a1, v0.t
+	vlsseg7e64.v v0, (a0), a1, v0.t
+	vssseg7e64.v v0, (a0), a1, v0.t
+	vlsseg8e64.v v0, (a0), a1, v0.t
+	vssseg8e64.v v0, (a0), a1, v0.t
+
+# Vector Ordered Indexed Segment Loads and Stores
+
+	vloxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+	vloxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vsoxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+	vsoxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vloxseg3ei8.v v4, (a0), v4
+	vloxseg3ei8.v v0, (a0), v4, v0.t
+	vsoxseg3ei8.v v4, (a0), v4
+	vsoxseg3ei8.v v0, (a0), v4, v0.t
+	vloxseg4ei8.v v4, (a0), v4
+	vloxseg4ei8.v v0, (a0), v4, v0.t
+	vsoxseg4ei8.v v4, (a0), v4
+	vsoxseg4ei8.v v0, (a0), v4, v0.t
+	vloxseg5ei8.v v4, (a0), v4
+	vloxseg5ei8.v v0, (a0), v4, v0.t
+	vsoxseg5ei8.v v4, (a0), v4
+	vsoxseg5ei8.v v0, (a0), v4, v0.t
+	vloxseg6ei8.v v4, (a0), v4
+	vloxseg6ei8.v v0, (a0), v4, v0.t
+	vsoxseg6ei8.v v4, (a0), v4
+	vsoxseg6ei8.v v0, (a0), v4, v0.t
+	vloxseg7ei8.v v4, (a0), v4
+	vloxseg7ei8.v v0, (a0), v4, v0.t
+	vsoxseg7ei8.v v4, (a0), v4
+	vsoxseg7ei8.v v0, (a0), v4, v0.t
+	vloxseg8ei8.v v4, (a0), v4
+	vloxseg8ei8.v v0, (a0), v4, v0.t
+	vsoxseg8ei8.v v4, (a0), v4
+	vsoxseg8ei8.v v0, (a0), v4, v0.t
+
+	vloxseg2ei16.v v4, (a0), v4
+	vloxseg2ei16.v v0, (a0), v4, v0.t
+	vsoxseg2ei16.v v4, (a0), v4
+	vsoxseg2ei16.v v0, (a0), v4, v0.t
+	vloxseg3ei16.v v4, (a0), v4
+	vloxseg3ei16.v v0, (a0), v4, v0.t
+	vsoxseg3ei16.v v4, (a0), v4
+	vsoxseg3ei16.v v0, (a0), v4, v0.t
+	vloxseg4ei16.v v4, (a0), v4
+	vloxseg4ei16.v v0, (a0), v4, v0.t
+	vsoxseg4ei16.v v4, (a0), v4
+	vsoxseg4ei16.v v0, (a0), v4, v0.t
+	vloxseg5ei16.v v4, (a0), v4
+	vloxseg5ei16.v v0, (a0), v4, v0.t
+	vsoxseg5ei16.v v4, (a0), v4
+	vsoxseg5ei16.v v0, (a0), v4, v0.t
+	vloxseg6ei16.v v4, (a0), v4
+	vloxseg6ei16.v v0, (a0), v4, v0.t
+	vsoxseg6ei16.v v4, (a0), v4
+	vsoxseg6ei16.v v0, (a0), v4, v0.t
+	vloxseg7ei16.v v4, (a0), v4
+	vloxseg7ei16.v v0, (a0), v4, v0.t
+	vsoxseg7ei16.v v4, (a0), v4
+	vsoxseg7ei16.v v0, (a0), v4, v0.t
+	vloxseg8ei16.v v4, (a0), v4
+	vloxseg8ei16.v v0, (a0), v4, v0.t
+	vsoxseg8ei16.v v4, (a0), v4
+	vsoxseg8ei16.v v0, (a0), v4, v0.t
+
+	vloxseg2ei32.v v4, (a0), v4
+	vloxseg2ei32.v v0, (a0), v4, v0.t
+	vsoxseg2ei32.v v4, (a0), v4
+	vsoxseg2ei32.v v0, (a0), v4, v0.t
+	vloxseg3ei32.v v4, (a0), v4
+	vloxseg3ei32.v v0, (a0), v4, v0.t
+	vsoxseg3ei32.v v4, (a0), v4
+	vsoxseg3ei32.v v0, (a0), v4, v0.t
+	vloxseg4ei32.v v4, (a0), v4
+	vloxseg4ei32.v v0, (a0), v4, v0.t
+	vsoxseg4ei32.v v4, (a0), v4
+	vsoxseg4ei32.v v0, (a0), v4, v0.t
+	vloxseg5ei32.v v4, (a0), v4
+	vloxseg5ei32.v v0, (a0), v4, v0.t
+	vsoxseg5ei32.v v4, (a0), v4
+	vsoxseg5ei32.v v0, (a0), v4, v0.t
+	vloxseg6ei32.v v4, (a0), v4
+	vloxseg6ei32.v v0, (a0), v4, v0.t
+	vsoxseg6ei32.v v4, (a0), v4
+	vsoxseg6ei32.v v0, (a0), v4, v0.t
+	vloxseg7ei32.v v4, (a0), v4
+	vloxseg7ei32.v v0, (a0), v4, v0.t
+	vsoxseg7ei32.v v4, (a0), v4
+	vsoxseg7ei32.v v0, (a0), v4, v0.t
+	vloxseg8ei32.v v4, (a0), v4
+	vloxseg8ei32.v v0, (a0), v4, v0.t
+	vsoxseg8ei32.v v4, (a0), v4
+	vsoxseg8ei32.v v0, (a0), v4, v0.t
+
+	vloxseg2ei64.v v4, (a0), v4
+	vloxseg2ei64.v v0, (a0), v4, v0.t
+	vsoxseg2ei64.v v4, (a0), v4
+	vsoxseg2ei64.v v0, (a0), v4, v0.t
+	vloxseg3ei64.v v4, (a0), v4
+	vloxseg3ei64.v v0, (a0), v4, v0.t
+	vsoxseg3ei64.v v4, (a0), v4
+	vsoxseg3ei64.v v0, (a0), v4, v0.t
+	vloxseg4ei64.v v4, (a0), v4
+	vloxseg4ei64.v v0, (a0), v4, v0.t
+	vsoxseg4ei64.v v4, (a0), v4
+	vsoxseg4ei64.v v0, (a0), v4, v0.t
+	vloxseg5ei64.v v4, (a0), v4
+	vloxseg5ei64.v v0, (a0), v4, v0.t
+	vsoxseg5ei64.v v4, (a0), v4
+	vsoxseg5ei64.v v0, (a0), v4, v0.t
+	vloxseg6ei64.v v4, (a0), v4
+	vloxseg6ei64.v v0, (a0), v4, v0.t
+	vsoxseg6ei64.v v4, (a0), v4
+	vsoxseg6ei64.v v0, (a0), v4, v0.t
+	vloxseg7ei64.v v4, (a0), v4
+	vloxseg7ei64.v v0, (a0), v4, v0.t
+	vsoxseg7ei64.v v4, (a0), v4
+	vsoxseg7ei64.v v0, (a0), v4, v0.t
+	vloxseg8ei64.v v4, (a0), v4
+	vloxseg8ei64.v v0, (a0), v4, v0.t
+	vsoxseg8ei64.v v4, (a0), v4
+	vsoxseg8ei64.v v0, (a0), v4, v0.t
+
+# Vector Unordered Indexed Segment Loads and Stores
+
+	vluxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+	vluxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vsuxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+	vsuxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vluxseg3ei8.v v4, (a0), v4
+	vluxseg3ei8.v v0, (a0), v4, v0.t
+	vsuxseg3ei8.v v4, (a0), v4
+	vsuxseg3ei8.v v0, (a0), v4, v0.t
+	vluxseg4ei8.v v4, (a0), v4
+	vluxseg4ei8.v v0, (a0), v4, v0.t
+	vsuxseg4ei8.v v4, (a0), v4
+	vsuxseg4ei8.v v0, (a0), v4, v0.t
+	vluxseg5ei8.v v4, (a0), v4
+	vluxseg5ei8.v v0, (a0), v4, v0.t
+	vsuxseg5ei8.v v4, (a0), v4
+	vsuxseg5ei8.v v0, (a0), v4, v0.t
+	vluxseg6ei8.v v4, (a0), v4
+	vluxseg6ei8.v v0, (a0), v4, v0.t
+	vsuxseg6ei8.v v4, (a0), v4
+	vsuxseg6ei8.v v0, (a0), v4, v0.t
+	vluxseg7ei8.v v4, (a0), v4
+	vluxseg7ei8.v v0, (a0), v4, v0.t
+	vsuxseg7ei8.v v4, (a0), v4
+	vsuxseg7ei8.v v0, (a0), v4, v0.t
+	vluxseg8ei8.v v4, (a0), v4
+	vluxseg8ei8.v v0, (a0), v4, v0.t
+	vsuxseg8ei8.v v4, (a0), v4
+	vsuxseg8ei8.v v0, (a0), v4, v0.t
+
+	vluxseg2ei16.v v4, (a0), v4
+	vluxseg2ei16.v v0, (a0), v4, v0.t
+	vsuxseg2ei16.v v4, (a0), v4
+	vsuxseg2ei16.v v0, (a0), v4, v0.t
+	vluxseg3ei16.v v4, (a0), v4
+	vluxseg3ei16.v v0, (a0), v4, v0.t
+	vsuxseg3ei16.v v4, (a0), v4
+	vsuxseg3ei16.v v0, (a0), v4, v0.t
+	vluxseg4ei16.v v4, (a0), v4
+	vluxseg4ei16.v v0, (a0), v4, v0.t
+	vsuxseg4ei16.v v4, (a0), v4
+	vsuxseg4ei16.v v0, (a0), v4, v0.t
+	vluxseg5ei16.v v4, (a0), v4
+	vluxseg5ei16.v v0, (a0), v4, v0.t
+	vsuxseg5ei16.v v4, (a0), v4
+	vsuxseg5ei16.v v0, (a0), v4, v0.t
+	vluxseg6ei16.v v4, (a0), v4
+	vluxseg6ei16.v v0, (a0), v4, v0.t
+	vsuxseg6ei16.v v4, (a0), v4
+	vsuxseg6ei16.v v0, (a0), v4, v0.t
+	vluxseg7ei16.v v4, (a0), v4
+	vluxseg7ei16.v v0, (a0), v4, v0.t
+	vsuxseg7ei16.v v4, (a0), v4
+	vsuxseg7ei16.v v0, (a0), v4, v0.t
+	vluxseg8ei16.v v4, (a0), v4
+	vluxseg8ei16.v v0, (a0), v4, v0.t
+	vsuxseg8ei16.v v4, (a0), v4
+	vsuxseg8ei16.v v0, (a0), v4, v0.t
+
+	vluxseg2ei32.v v4, (a0), v4
+	vluxseg2ei32.v v0, (a0), v4, v0.t
+	vsuxseg2ei32.v v4, (a0), v4
+	vsuxseg2ei32.v v0, (a0), v4, v0.t
+	vluxseg3ei32.v v4, (a0), v4
+	vluxseg3ei32.v v0, (a0), v4, v0.t
+	vsuxseg3ei32.v v4, (a0), v4
+	vsuxseg3ei32.v v0, (a0), v4, v0.t
+	vluxseg4ei32.v v4, (a0), v4
+	vluxseg4ei32.v v0, (a0), v4, v0.t
+	vsuxseg4ei32.v v4, (a0), v4
+	vsuxseg4ei32.v v0, (a0), v4, v0.t
+	vluxseg5ei32.v v4, (a0), v4
+	vluxseg5ei32.v v0, (a0), v4, v0.t
+	vsuxseg5ei32.v v4, (a0), v4
+	vsuxseg5ei32.v v0, (a0), v4, v0.t
+	vluxseg6ei32.v v4, (a0), v4
+	vluxseg6ei32.v v0, (a0), v4, v0.t
+	vsuxseg6ei32.v v4, (a0), v4
+	vsuxseg6ei32.v v0, (a0), v4, v0.t
+	vluxseg7ei32.v v4, (a0), v4
+	vluxseg7ei32.v v0, (a0), v4, v0.t
+	vsuxseg7ei32.v v4, (a0), v4
+	vsuxseg7ei32.v v0, (a0), v4, v0.t
+	vluxseg8ei32.v v4, (a0), v4
+	vluxseg8ei32.v v0, (a0), v4, v0.t
+	vsuxseg8ei32.v v4, (a0), v4
+	vsuxseg8ei32.v v0, (a0), v4, v0.t
+
+	vluxseg2ei64.v v4, (a0), v4
+	vluxseg2ei64.v v0, (a0), v4, v0.t
+	vsuxseg2ei64.v v4, (a0), v4
+	vsuxseg2ei64.v v0, (a0), v4, v0.t
+	vluxseg3ei64.v v4, (a0), v4
+	vluxseg3ei64.v v0, (a0), v4, v0.t
+	vsuxseg3ei64.v v4, (a0), v4
+	vsuxseg3ei64.v v0, (a0), v4, v0.t
+	vluxseg4ei64.v v4, (a0), v4
+	vluxseg4ei64.v v0, (a0), v4, v0.t
+	vsuxseg4ei64.v v4, (a0), v4
+	vsuxseg4ei64.v v0, (a0), v4, v0.t
+	vluxseg5ei64.v v4, (a0), v4
+	vluxseg5ei64.v v0, (a0), v4, v0.t
+	vsuxseg5ei64.v v4, (a0), v4
+	vsuxseg5ei64.v v0, (a0), v4, v0.t
+	vluxseg6ei64.v v4, (a0), v4
+	vluxseg6ei64.v v0, (a0), v4, v0.t
+	vsuxseg6ei64.v v4, (a0), v4
+	vsuxseg6ei64.v v0, (a0), v4, v0.t
+	vluxseg7ei64.v v4, (a0), v4
+	vluxseg7ei64.v v0, (a0), v4, v0.t
+	vsuxseg7ei64.v v4, (a0), v4
+	vsuxseg7ei64.v v0, (a0), v4, v0.t
+	vluxseg8ei64.v v4, (a0), v4
+	vluxseg8ei64.v v0, (a0), v4, v0.t
+	vsuxseg8ei64.v v4, (a0), v4
+	vsuxseg8ei64.v v0, (a0), v4, v0.t
+
+# Vector Load/Store Whole Register Instructions
+
+	vl1r.v v31, (a0)		# OK
+
+	vl2r.v v31, (a0)		# vd must be aligned to 2
+	vl2re8.v v31, (a0)
+	vl2re16.v v31, (a0)
+	vl2re32.v v31, (a0)
+	vl2re64.v v31, (a0)
+
+	vl4r.v v30, (a0)		# vd must be aligned to 4
+	vl4re8.v v30, (a0)
+	vl4re16.v v30, (a0)
+	vl4re32.v v30, (a0)
+	vl4re64.v v30, (a0)
+
+	vl8r.v v26, (a0)		# vd must be aligned to 8
+	vl8re8.v v26, (a0)
+	vl8re16.v v26, (a0)
+	vl8re32.v v26, (a0)
+	vl8re64.v v26, (a0)
+
+	vs2r.v v31, (a0)		# vs3 must be aligned to 2
+	vs4r.v v30, (a0)		# vs3 must be aligned to 4
+	vs8r.v v26, (a0)		# vs3 must be aligned to 8

gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.d

@@ -0,0 +1,3 @@
+#as: -march=rv32iv -mcheck-constraints
+#source: vector-insns-fail-mask.s
+#error_output: vector-insns-fail-mask.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.l

@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vs2 `vmsbf.m v4,v4'
+.*Error: illegal operands vd cannot overlap vm `vmsbf.m v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vmsif.m v4,v4'
+.*Error: illegal operands vd cannot overlap vm `vmsif.m v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vmsof.m v4,v4'
+.*Error: illegal operands vd cannot overlap vm `vmsof.m v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `viota.m v4,v4'
+.*Error: illegal operands vd cannot overlap vm `viota.m v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vid.v v0,v0.t'

gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.s

@@ -0,0 +1,23 @@
+# Vector Set-before-first Mask Bit
+
+	vmsbf.m v4, v4		# vd overlap vs2
+	vmsbf.m v0, v4, v0.t	# vd overlap vm
+
+# Vector Set-including-first Mask Bit
+
+	vmsif.m v4, v4		# vd overlap vs2
+	vmsif.m v0, v4, v0.t	# vd overlap vm
+
+# Vector Set-only-first Mask Bit
+
+	vmsof.m v4, v4		# vd overlap vs2
+	vmsof.m v0, v4, v0.t	# vd overlap vm
+
+# Vector Iota Instruction
+
+	viota.m v4, v4		# vd overlap vs2
+	viota.m v0, v4, v0.t	# vd overlap vm
+
+# Vector Element Index Instruction
+
+	vid.v v0, v0.t		# vd overlap vm

gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.d

@@ -0,0 +1,3 @@
+#as: -march=rv32ifv -mcheck-constraints
+#source: vector-insns-fail-permutation.s
+#error_output: vector-insns-fail-permutation.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.l

@@ -0,0 +1,31 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vs2 `vslideup.vx v4,v4,a1'
+.*Error: illegal operands vd cannot overlap vm `vslideup.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vslideup.vi v4,v4,31'
+.*Error: illegal operands vd cannot overlap vm `vslideup.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vslidedown.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vslidedown.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vslide1up.vx v4,v4,a1'
+.*Error: illegal operands vd cannot overlap vm `vslide1up.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfslide1up.vf v4,v4,fa1'
+.*Error: illegal operands vd cannot overlap vm `vfslide1up.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vslide1down.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfslide1down.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vrgather.vv v4,v4,v8'
+.*Error: illegal operands vd cannot overlap vs1 `vrgather.vv v8,v4,v8'
+.*Error: illegal operands vd cannot overlap vm `vrgather.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vrgather.vx v4,v4,a1'
+.*Error: illegal operands vd cannot overlap vm `vrgather.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vrgather.vi v4,v4,31'
+.*Error: illegal operands vd cannot overlap vm `vrgather.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vrgatherei16.vv v4,v4,v8'
+.*Error: illegal operands vd cannot overlap vs1 `vrgatherei16.vv v8,v4,v8'
+.*Error: illegal operands vd cannot overlap vm `vrgatherei16.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vcompress.vm v4,v4,v8'
+.*Error: illegal operands vd cannot overlap vs1 `vcompress.vm v8,v4,v8'
+.*Error: illegal operands vs2 must be multiple of nf `vmv2r.v v30,v31'
+.*Error: illegal operands vd must be multiple of nf `vmv2r.v v31,v30'
+.*Error: illegal operands vs2 must be multiple of nf `vmv4r.v v28,v30'
+.*Error: illegal operands vd must be multiple of nf `vmv4r.v v30,v28'
+.*Error: illegal operands vs2 must be multiple of nf `vmv8r.v v24,v26'
+.*Error: illegal operands vd must be multiple of nf `vmv8r.v v26,v24'

gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.s

@@ -0,0 +1,56 @@
+# Vector Slideup Instructions
+
+	vslideup.vx v4, v4, a1			# vd overlap vs2
+	vslideup.vx v0, v4, a1, v0.t		# vd overlap vm
+	vslideup.vi v4, v4, 31			# vd overlap vs2
+	vslideup.vi v0, v4, 31, v0.t		# vd overlap vm
+
+	vslidedown.vx v4, v4, a1		# OK
+	vslidedown.vx v0, v4, a1, v0.t		# vd overlap vm
+	vslidedown.vi v4, v4, 31		# OK
+	vslidedown.vi v0, v4, 31, v0.t		# vd overlap vm
+
+	vslide1up.vx v4, v4, a1			# vd overlap vs2
+	vslide1up.vx v0, v4, a1, v0.t		# vd overlap vm
+	vfslide1up.vf v4, v4, fa1		# vd overlap vs2
+	vfslide1up.vf v0, v4, fa1, v0.t		# vd overlap vm
+
+	vslide1down.vx v4, v4, a1		# OK
+	vslide1down.vx v0, v4, a1, v0.t		# vd overlap vm
+	vfslide1down.vf v4, v4, fa1		# OK
+	vfslide1down.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+# Vector Register Gather Instructions
+
+	vrgather.vv v4, v4, v8			# vd overlap vs2
+	vrgather.vv v8, v4, v8			# vd overlap vs1
+	vrgather.vv v0, v4, v8, v0.t		# vd overlap vm
+	vrgather.vx v4, v4, a1			# vd overlap vs2
+	vrgather.vx v0, v4, a1, v0.t		# vd overlap vm
+	vrgather.vi v4, v4, 31			# vd overlap vs2
+	vrgather.vi v0, v4, 31, v0.t		# vd overlap vm
+
+	vrgatherei16.vv v4, v4, v8		# vd overlap vs2
+	vrgatherei16.vv v8, v4, v8		# vd overlap vs1
+	vrgatherei16.vv v0, v4, v8, v0.t	# vd overlap vm
+
+# Vector Compress Instruction
+
+	vcompress.vm v4, v4, v8			# vd overlap vs2
+	vcompress.vm v8, v4, v8			# vd overlap vs1
+
+# Whole Vector Register Move
+
+	vmv1r.v v31, v31			# OK, HINT
+
+	vmv2r.v v30, v30			# OK, HINT
+	vmv2r.v v30, v31			# vs2 must be aligned to 2
+	vmv2r.v v31, v30			# vd must be aligned to 2
+
+	vmv4r.v v28, v28			# OK, HINT
+	vmv4r.v v28, v30			# vs2 must be aligned to 4
+	vmv4r.v v30, v28			# vd must be aligned to 4
+
+	vmv8r.v v24, v24			# OK, HINT
+	vmv8r.v v24, v26			# vs2 must be aligned to 8
+	vmv8r.v v26, v24			# vd must be aligned to 8

gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_zvamo -mcheck-constraints
+#source: vector-insns-fail-zvamo.s
+#error_output: vector-insns-fail-zvamo.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.l

@@ -0,0 +1,109 @@
+.*: Assembler messages:
+.*Error: illegal operands `vamoaddei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoswapei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoxorei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoandei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoorei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominuei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxuei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoaddei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoswapei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoxorei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoandei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoorei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominuei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxuei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoaddei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoswapei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoxorei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoandei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoorei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominuei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxuei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoaddei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoswapei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoxorei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoandei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoorei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominuei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxuei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'

gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.s

@@ -0,0 +1,217 @@
+# Vector AMO Operations
+
+	vamoaddei8.v v0, (a1), v4, v0		# OK
+	vamoaddei8.v v4, (a1), v4, v0		# vd must match vs3
+	vamoaddei8.v v0, (a1), v4, v0, v0.t	# vd overlap vm
+	vamoaddei8.v x0, (a1), v4, v0		# OK
+	vamoaddei8.v x0, (a1), v4, v0, v0.t	# vs3 overlap vm
+
+	vamoswapei8.v v0, (a1), v4, v0
+	vamoswapei8.v v4, (a1), v4, v0
+	vamoswapei8.v v0, (a1), v4, v0, v0.t
+	vamoswapei8.v x0, (a1), v4, v0
+	vamoswapei8.v x0, (a1), v4, v0, v0.t
+
+	vamoxorei8.v v0, (a1), v4, v0
+	vamoxorei8.v v4, (a1), v4, v0
+	vamoxorei8.v v0, (a1), v4, v0, v0.t
+	vamoxorei8.v x0, (a1), v4, v0
+	vamoxorei8.v x0, (a1), v4, v0, v0.t
+
+	vamoandei8.v v0, (a1), v4, v0
+	vamoandei8.v v4, (a1), v4, v0
+	vamoandei8.v v0, (a1), v4, v0, v0.t
+	vamoandei8.v x0, (a1), v4, v0
+	vamoandei8.v x0, (a1), v4, v0, v0.t
+
+	vamoorei8.v v0, (a1), v4, v0
+	vamoorei8.v v4, (a1), v4, v0
+	vamoorei8.v v0, (a1), v4, v0, v0.t
+	vamoorei8.v x0, (a1), v4, v0
+	vamoorei8.v x0, (a1), v4, v0, v0.t
+
+	vamominei8.v v0, (a1), v4, v0
+	vamominei8.v v4, (a1), v4, v0
+	vamominei8.v v0, (a1), v4, v0, v0.t
+	vamominei8.v x0, (a1), v4, v0
+	vamominei8.v x0, (a1), v4, v0, v0.t
+
+	vamomaxei8.v v0, (a1), v4, v0
+	vamomaxei8.v v4, (a1), v4, v0
+	vamomaxei8.v v0, (a1), v4, v0, v0.t
+	vamomaxei8.v x0, (a1), v4, v0
+	vamomaxei8.v x0, (a1), v4, v0, v0.t
+
+	vamominuei8.v v0, (a1), v4, v0
+	vamominuei8.v v4, (a1), v4, v0
+	vamominuei8.v v0, (a1), v4, v0, v0.t
+	vamominuei8.v x0, (a1), v4, v0
+	vamominuei8.v x0, (a1), v4, v0, v0.t
+
+	vamomaxuei8.v v0, (a1), v4, v0
+	vamomaxuei8.v v4, (a1), v4, v0
+	vamomaxuei8.v v0, (a1), v4, v0, v0.t
+	vamomaxuei8.v x0, (a1), v4, v0
+	vamomaxuei8.v x0, (a1), v4, v0, v0.t
+
+	vamoaddei16.v v0, (a1), v4, v0
+	vamoaddei16.v v4, (a1), v4, v0
+	vamoaddei16.v v0, (a1), v4, v0, v0.t
+	vamoaddei16.v x0, (a1), v4, v0
+	vamoaddei16.v x0, (a1), v4, v0, v0.t
+
+	vamoswapei16.v v0, (a1), v4, v0
+	vamoswapei16.v v0, (a1), v4, v0, v0.t
+	vamoswapei16.v v4, (a1), v4, v0
+	vamoswapei16.v x0, (a1), v4, v0
+	vamoswapei16.v x0, (a1), v4, v0, v0.t
+
+	vamoxorei16.v v0, (a1), v4, v0
+	vamoxorei16.v v0, (a1), v4, v0, v0.t
+	vamoxorei16.v v4, (a1), v4, v0
+	vamoxorei16.v x0, (a1), v4, v0
+	vamoxorei16.v x0, (a1), v4, v0, v0.t
+
+	vamoandei16.v v0, (a1), v4, v0
+	vamoandei16.v v0, (a1), v4, v0, v0.t
+	vamoandei16.v v4, (a1), v4, v0
+	vamoandei16.v x0, (a1), v4, v0
+	vamoandei16.v x0, (a1), v4, v0, v0.t
+
+	vamoorei16.v v0, (a1), v4, v0
+	vamoorei16.v v0, (a1), v4, v0, v0.t
+	vamoorei16.v v4, (a1), v4, v0
+	vamoorei16.v x0, (a1), v4, v0
+	vamoorei16.v x0, (a1), v4, v0, v0.t
+
+	vamominei16.v v0, (a1), v4, v0
+	vamominei16.v v0, (a1), v4, v0, v0.t
+	vamominei16.v v4, (a1), v4, v0
+	vamominei16.v x0, (a1), v4, v0
+	vamominei16.v x0, (a1), v4, v0, v0.t
+
+	vamomaxei16.v v0, (a1), v4, v0
+	vamomaxei16.v v0, (a1), v4, v0, v0.t
+	vamomaxei16.v v4, (a1), v4, v0
+	vamomaxei16.v x0, (a1), v4, v0
+	vamomaxei16.v x0, (a1), v4, v0, v0.t
+
+	vamominuei16.v v0, (a1), v4, v0
+	vamominuei16.v v0, (a1), v4, v0, v0.t
+	vamominuei16.v v4, (a1), v4, v0
+	vamominuei16.v x0, (a1), v4, v0
+	vamominuei16.v x0, (a1), v4, v0, v0.t
+
+	vamomaxuei16.v v0, (a1), v4, v0
+	vamomaxuei16.v v0, (a1), v4, v0, v0.t
+	vamomaxuei16.v v4, (a1), v4, v0
+	vamomaxuei16.v x0, (a1), v4, v0
+	vamomaxuei16.v x0, (a1), v4, v0, v0.t
+
+	vamoaddei32.v v0, (a1), v4, v0
+	vamoaddei32.v v0, (a1), v4, v0, v0.t
+	vamoaddei32.v v4, (a1), v4, v0
+	vamoaddei32.v x0, (a1), v4, v0
+	vamoaddei32.v x0, (a1), v4, v0, v0.t
+
+	vamoswapei32.v v0, (a1), v4, v0
+	vamoswapei32.v v4, (a1), v4, v0
+	vamoswapei32.v v0, (a1), v4, v0, v0.t
+	vamoswapei32.v x0, (a1), v4, v0
+	vamoswapei32.v x0, (a1), v4, v0, v0.t
+
+	vamoxorei32.v v0, (a1), v4, v0
+	vamoxorei32.v v4, (a1), v4, v0
+	vamoxorei32.v v0, (a1), v4, v0, v0.t
+	vamoxorei32.v x0, (a1), v4, v0
+	vamoxorei32.v x0, (a1), v4, v0, v0.t
+
+	vamoandei32.v v0, (a1), v4, v0
+	vamoandei32.v v4, (a1), v4, v0
+	vamoandei32.v v0, (a1), v4, v0, v0.t
+	vamoandei32.v x0, (a1), v4, v0
+	vamoandei32.v x0, (a1), v4, v0, v0.t
+
+	vamoorei32.v v0, (a1), v4, v0
+	vamoorei32.v v4, (a1), v4, v0
+	vamoorei32.v v0, (a1), v4, v0, v0.t
+	vamoorei32.v x0, (a1), v4, v0
+	vamoorei32.v x0, (a1), v4, v0, v0.t
+
+	vamominei32.v v0, (a1), v4, v0
+	vamominei32.v v4, (a1), v4, v0
+	vamominei32.v v0, (a1), v4, v0, v0.t
+	vamominei32.v x0, (a1), v4, v0
+	vamominei32.v x0, (a1), v4, v0, v0.t
+
+	vamomaxei32.v v0, (a1), v4, v0
+	vamomaxei32.v v4, (a1), v4, v0
+	vamomaxei32.v v0, (a1), v4, v0, v0.t
+	vamomaxei32.v x0, (a1), v4, v0
+	vamomaxei32.v x0, (a1), v4, v0, v0.t
+
+	vamominuei32.v v0, (a1), v4, v0
+	vamominuei32.v v4, (a1), v4, v0
+	vamominuei32.v v0, (a1), v4, v0, v0.t
+	vamominuei32.v x0, (a1), v4, v0
+	vamominuei32.v x0, (a1), v4, v0, v0.t
+
+	vamomaxuei32.v v0, (a1), v4, v0
+	vamomaxuei32.v v4, (a1), v4, v0
+	vamomaxuei32.v v0, (a1), v4, v0, v0.t
+	vamomaxuei32.v x0, (a1), v4, v0
+	vamomaxuei32.v x0, (a1), v4, v0, v0.t
+
+	vamoaddei64.v v0, (a1), v4, v0
+	vamoaddei64.v v4, (a1), v4, v0
+	vamoaddei64.v v0, (a1), v4, v0, v0.t
+	vamoaddei64.v x0, (a1), v4, v0
+	vamoaddei64.v x0, (a1), v4, v0, v0.t
+
+	vamoswapei64.v v0, (a1), v4, v0
+	vamoswapei64.v v4, (a1), v4, v0
+	vamoswapei64.v v0, (a1), v4, v0, v0.t
+	vamoswapei64.v x0, (a1), v4, v0
+	vamoswapei64.v x0, (a1), v4, v0, v0.t
+
+	vamoxorei64.v v0, (a1), v4, v0
+	vamoxorei64.v v4, (a1), v4, v0
+	vamoxorei64.v v0, (a1), v4, v0, v0.t
+	vamoxorei64.v x0, (a1), v4, v0
+	vamoxorei64.v x0, (a1), v4, v0, v0.t
+
+	vamoandei64.v v0, (a1), v4, v0
+	vamoandei64.v v4, (a1), v4, v0
+	vamoandei64.v v0, (a1), v4, v0, v0.t
+	vamoandei64.v x0, (a1), v4, v0
+	vamoandei64.v x0, (a1), v4, v0, v0.t
+
+	vamoorei64.v v0, (a1), v4, v0
+	vamoorei64.v v4, (a1), v4, v0
+	vamoorei64.v v0, (a1), v4, v0, v0.t
+	vamoorei64.v x0, (a1), v4, v0
+	vamoorei64.v x0, (a1), v4, v0, v0.t
+
+	vamominei64.v v0, (a1), v4, v0
+	vamominei64.v v4, (a1), v4, v0
+	vamominei64.v v0, (a1), v4, v0, v0.t
+	vamominei64.v x0, (a1), v4, v0
+	vamominei64.v x0, (a1), v4, v0, v0.t
+
+	vamomaxei64.v v0, (a1), v4, v0
+	vamomaxei64.v v4, (a1), v4, v0
+	vamomaxei64.v v0, (a1), v4, v0, v0.t
+	vamomaxei64.v x0, (a1), v4, v0
+	vamomaxei64.v x0, (a1), v4, v0, v0.t
+
+	vamominuei64.v v0, (a1), v4, v0
+	vamominuei64.v v4, (a1), v4, v0
+	vamominuei64.v v0, (a1), v4, v0, v0.t
+	vamominuei64.v x0, (a1), v4, v0
+	vamominuei64.v x0, (a1), v4, v0, v0.t
+
+	vamomaxuei64.v v0, (a1), v4, v0
+	vamomaxuei64.v v4, (a1), v4, v0
+	vamomaxuei64.v v0, (a1), v4, v0, v0.t
+	vamomaxuei64.v x0, (a1), v4, v0
+	vamomaxuei64.v x0, (a1), v4, v0, v0.t

gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_zvamo_zve32x
+#source: vector-insns-fail-zve32x.s
+#error_output: vector-insns-fail-zve32x.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l

@@ -0,0 +1,82 @@
+.*Assembler messages:
+.*Error: illegal vsew e64 for zve32x and zve32f
+.*Error: illegal vsew e128 for zve32x and zve32f
+.*Error: illegal vsew e256 for zve32x and zve32f
+.*Error: illegal vsew e512 for zve32x and zve32f
+.*Error: illegal vsew e1024 for zve32x and zve32f
+.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vl1re64.v v3,\(a0\)'
+.*Error: illegal opcode for zve32x `vl2re64.v v2,\(a0\)'
+.*Error: illegal opcode for zve32x `vl4re64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vl8re64.v v8,\(a0\)'

gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s

@@ -0,0 +1,413 @@
+	vsetvl a0, a1, a2
+	vsetvli a0, a1, e8
+	vsetvli a0, a1, e16, m2
+	vsetvli a0, a1, e32, m2, ta
+	vsetvli a0, a1, e64, m2, ta, ma
+	vsetvli a0, a1, e128
+	vsetvli a0, a1, e256, m2
+	vsetvli a0, a1, e512, m2, ta
+	vsetvli a0, a1, e1024, m2, ta, ma
+
+	vlm.v v4, (a0)
+	vle1.v v4, (a0)		# Alias of vlm.v
+	vsm.v v4, (a0)
+	vse1.v v4, (a0)		# Alias of vsm.v
+
+	vle8.v v4, (a0)
+	vse8.v v4, (a0)
+	vle16.v v4, (a0)
+	vse16.v v4, (a0)
+	vle32.v v4, (a0)
+	vse32.v v4, (a0)
+	vle64.v v4, (a0)
+	vse64.v v4, (a0)
+
+	vlse8.v v4, (a0), a1
+	vsse8.v v4, (a0), a1
+	vlse16.v v4, (a0), a1
+	vsse16.v v4, (a0), a1
+	vlse32.v v4, (a0), a1
+	vsse32.v v4, (a0), a1
+	vlse64.v v4, (a0), a1
+	vsse64.v v4, (a0), a1
+
+	vloxei8.v v4, (a0), v12
+	vsoxei8.v v4, (a0), v12
+	vluxei8.v v4, (a0), v12
+	vsuxei8.v v4, (a0), v12
+	vloxei16.v v4, (a0), v12
+	vsoxei16.v v4, (a0), v12
+	vluxei16.v v4, (a0), v12
+	vsuxei16.v v4, (a0), v12
+	vloxei32.v v4, (a0), v12
+	vsoxei32.v v4, (a0), v12
+	vluxei32.v v4, (a0), v12
+	vsuxei32.v v4, (a0), v12
+	vloxei64.v v4, (a0), v12
+	vsoxei64.v v4, (a0), v12
+	vluxei64.v v4, (a0), v12
+	vsuxei64.v v4, (a0), v12
+
+	vle8ff.v v4, (a0)
+	vle16ff.v v4, (a0)
+	vle32ff.v v4, (a0)
+	vle64ff.v v4, (a0)
+
+	vlseg2e8.v v4, (a0)
+	vsseg2e8.v v4, (a0)
+	vlseg3e8.v v4, (a0)
+	vsseg3e8.v v4, (a0)
+	vlseg4e8.v v4, (a0)
+	vsseg4e8.v v4, (a0)
+	vlseg5e8.v v4, (a0)
+	vsseg5e8.v v4, (a0)
+	vlseg6e8.v v4, (a0)
+	vsseg6e8.v v4, (a0)
+	vlseg7e8.v v4, (a0)
+	vsseg7e8.v v4, (a0)
+	vlseg8e8.v v4, (a0)
+	vsseg8e8.v v4, (a0)
+	vlseg2e16.v v4, (a0)
+	vsseg2e16.v v4, (a0)
+	vlseg3e16.v v4, (a0)
+	vsseg3e16.v v4, (a0)
+	vlseg4e16.v v4, (a0)
+	vsseg4e16.v v4, (a0)
+	vlseg5e16.v v4, (a0)
+	vsseg5e16.v v4, (a0)
+	vlseg6e16.v v4, (a0)
+	vsseg6e16.v v4, (a0)
+	vlseg7e16.v v4, (a0)
+	vsseg7e16.v v4, (a0)
+	vlseg8e16.v v4, (a0)
+	vsseg8e16.v v4, (a0)
+	vlseg2e32.v v4, (a0)
+	vsseg2e32.v v4, (a0)
+	vlseg3e32.v v4, (a0)
+	vsseg3e32.v v4, (a0)
+	vlseg4e32.v v4, (a0)
+	vsseg4e32.v v4, (a0)
+	vlseg5e32.v v4, (a0)
+	vsseg5e32.v v4, (a0)
+	vlseg6e32.v v4, (a0)
+	vsseg6e32.v v4, (a0)
+	vlseg7e32.v v4, (a0)
+	vsseg7e32.v v4, (a0)
+	vlseg8e32.v v4, (a0)
+	vsseg8e32.v v4, (a0)
+	vlseg2e64.v v4, (a0)
+	vsseg2e64.v v4, (a0)
+	vlseg3e64.v v4, (a0)
+	vsseg3e64.v v4, (a0)
+	vlseg4e64.v v4, (a0)
+	vsseg4e64.v v4, (a0)
+	vlseg5e64.v v4, (a0)
+	vsseg5e64.v v4, (a0)
+	vlseg6e64.v v4, (a0)
+	vsseg6e64.v v4, (a0)
+	vlseg7e64.v v4, (a0)
+	vsseg7e64.v v4, (a0)
+	vlseg8e64.v v4, (a0)
+	vsseg8e64.v v4, (a0)
+
+	vlsseg2e8.v v4, (a0), a1
+	vssseg2e8.v v4, (a0), a1
+	vlsseg3e8.v v4, (a0), a1
+	vssseg3e8.v v4, (a0), a1
+	vlsseg4e8.v v4, (a0), a1
+	vssseg4e8.v v4, (a0), a1
+	vlsseg5e8.v v4, (a0), a1
+	vssseg5e8.v v4, (a0), a1
+	vlsseg6e8.v v4, (a0), a1
+	vssseg6e8.v v4, (a0), a1
+	vlsseg7e8.v v4, (a0), a1
+	vssseg7e8.v v4, (a0), a1
+	vlsseg8e8.v v4, (a0), a1
+	vssseg8e8.v v4, (a0), a1
+	vlsseg2e16.v v4, (a0), a1
+	vssseg2e16.v v4, (a0), a1
+	vlsseg3e16.v v4, (a0), a1
+	vssseg3e16.v v4, (a0), a1
+	vlsseg4e16.v v4, (a0), a1
+	vssseg4e16.v v4, (a0), a1
+	vlsseg5e16.v v4, (a0), a1
+	vssseg5e16.v v4, (a0), a1
+	vlsseg6e16.v v4, (a0), a1
+	vssseg6e16.v v4, (a0), a1
+	vlsseg7e16.v v4, (a0), a1
+	vssseg7e16.v v4, (a0), a1
+	vlsseg8e16.v v4, (a0), a1
+	vssseg8e16.v v4, (a0), a1
+	vlsseg2e32.v v4, (a0), a1
+	vssseg2e32.v v4, (a0), a1
+	vlsseg3e32.v v4, (a0), a1
+	vssseg3e32.v v4, (a0), a1
+	vlsseg4e32.v v4, (a0), a1
+	vssseg4e32.v v4, (a0), a1
+	vlsseg5e32.v v4, (a0), a1
+	vssseg5e32.v v4, (a0), a1
+	vlsseg6e32.v v4, (a0), a1
+	vssseg6e32.v v4, (a0), a1
+	vlsseg7e32.v v4, (a0), a1
+	vssseg7e32.v v4, (a0), a1
+	vlsseg8e32.v v4, (a0), a1
+	vssseg8e32.v v4, (a0), a1
+	vlsseg2e64.v v4, (a0), a1
+	vssseg2e64.v v4, (a0), a1
+	vlsseg3e64.v v4, (a0), a1
+	vssseg3e64.v v4, (a0), a1
+	vlsseg4e64.v v4, (a0), a1
+	vssseg4e64.v v4, (a0), a1
+	vlsseg5e64.v v4, (a0), a1
+	vssseg5e64.v v4, (a0), a1
+	vlsseg6e64.v v4, (a0), a1
+	vssseg6e64.v v4, (a0), a1
+	vlsseg7e64.v v4, (a0), a1
+	vssseg7e64.v v4, (a0), a1
+	vlsseg8e64.v v4, (a0), a1
+	vssseg8e64.v v4, (a0), a1
+
+	vloxseg2ei8.v v4, (a0), v12
+	vsoxseg2ei8.v v4, (a0), v12
+	vloxseg3ei8.v v4, (a0), v12
+	vsoxseg3ei8.v v4, (a0), v12
+	vloxseg4ei8.v v4, (a0), v12
+	vsoxseg4ei8.v v4, (a0), v12
+	vloxseg5ei8.v v4, (a0), v12
+	vsoxseg5ei8.v v4, (a0), v12
+	vloxseg6ei8.v v4, (a0), v12
+	vsoxseg6ei8.v v4, (a0), v12
+	vloxseg7ei8.v v4, (a0), v12
+	vsoxseg7ei8.v v4, (a0), v12
+	vloxseg8ei8.v v4, (a0), v12
+	vsoxseg8ei8.v v4, (a0), v12
+	vloxseg2ei16.v v4, (a0), v12
+	vsoxseg2ei16.v v4, (a0), v12
+	vloxseg3ei16.v v4, (a0), v12
+	vsoxseg3ei16.v v4, (a0), v12
+	vloxseg4ei16.v v4, (a0), v12
+	vsoxseg4ei16.v v4, (a0), v12
+	vloxseg5ei16.v v4, (a0), v12
+	vsoxseg5ei16.v v4, (a0), v12
+	vloxseg6ei16.v v4, (a0), v12
+	vsoxseg6ei16.v v4, (a0), v12
+	vloxseg7ei16.v v4, (a0), v12
+	vsoxseg7ei16.v v4, (a0), v12
+	vloxseg8ei16.v v4, (a0), v12
+	vsoxseg8ei16.v v4, (a0), v12
+	vloxseg2ei32.v v4, (a0), v12
+	vsoxseg2ei32.v v4, (a0), v12
+	vloxseg3ei32.v v4, (a0), v12
+	vsoxseg3ei32.v v4, (a0), v12
+	vloxseg4ei32.v v4, (a0), v12
+	vsoxseg4ei32.v v4, (a0), v12
+	vloxseg5ei32.v v4, (a0), v12
+	vsoxseg5ei32.v v4, (a0), v12
+	vloxseg6ei32.v v4, (a0), v12
+	vsoxseg6ei32.v v4, (a0), v12
+	vloxseg7ei32.v v4, (a0), v12
+	vsoxseg7ei32.v v4, (a0), v12
+	vloxseg8ei32.v v4, (a0), v12
+	vsoxseg8ei32.v v4, (a0), v12
+	vloxseg2ei64.v v4, (a0), v12
+	vsoxseg2ei64.v v4, (a0), v12
+	vloxseg3ei64.v v4, (a0), v12
+	vsoxseg3ei64.v v4, (a0), v12
+	vloxseg4ei64.v v4, (a0), v12
+	vsoxseg4ei64.v v4, (a0), v12
+	vloxseg5ei64.v v4, (a0), v12
+	vsoxseg5ei64.v v4, (a0), v12
+	vloxseg6ei64.v v4, (a0), v12
+	vsoxseg6ei64.v v4, (a0), v12
+	vloxseg7ei64.v v4, (a0), v12
+	vsoxseg7ei64.v v4, (a0), v12
+	vloxseg8ei64.v v4, (a0), v12
+	vsoxseg8ei64.v v4, (a0), v12
+
+	vluxseg2ei8.v v4, (a0), v12
+	vsuxseg2ei8.v v4, (a0), v12
+	vluxseg3ei8.v v4, (a0), v12
+	vsuxseg3ei8.v v4, (a0), v12
+	vluxseg4ei8.v v4, (a0), v12
+	vsuxseg4ei8.v v4, (a0), v12
+	vluxseg5ei8.v v4, (a0), v12
+	vsuxseg5ei8.v v4, (a0), v12
+	vluxseg6ei8.v v4, (a0), v12
+	vsuxseg6ei8.v v4, (a0), v12
+	vluxseg7ei8.v v4, (a0), v12
+	vsuxseg7ei8.v v4, (a0), v12
+	vluxseg8ei8.v v4, (a0), v12
+	vsuxseg8ei8.v v4, (a0), v12
+	vluxseg2ei16.v v4, (a0), v12
+	vsuxseg2ei16.v v4, (a0), v12
+	vluxseg3ei16.v v4, (a0), v12
+	vsuxseg3ei16.v v4, (a0), v12
+	vluxseg4ei16.v v4, (a0), v12
+	vsuxseg4ei16.v v4, (a0), v12
+	vluxseg5ei16.v v4, (a0), v12
+	vsuxseg5ei16.v v4, (a0), v12
+	vluxseg6ei16.v v4, (a0), v12
+	vsuxseg6ei16.v v4, (a0), v12
+	vluxseg7ei16.v v4, (a0), v12
+	vsuxseg7ei16.v v4, (a0), v12
+	vluxseg8ei16.v v4, (a0), v12
+	vsuxseg8ei16.v v4, (a0), v12
+	vluxseg2ei32.v v4, (a0), v12
+	vsuxseg2ei32.v v4, (a0), v12
+	vluxseg3ei32.v v4, (a0), v12
+	vsuxseg3ei32.v v4, (a0), v12
+	vluxseg4ei32.v v4, (a0), v12
+	vsuxseg4ei32.v v4, (a0), v12
+	vluxseg5ei32.v v4, (a0), v12
+	vsuxseg5ei32.v v4, (a0), v12
+	vluxseg6ei32.v v4, (a0), v12
+	vsuxseg6ei32.v v4, (a0), v12
+	vluxseg7ei32.v v4, (a0), v12
+	vsuxseg7ei32.v v4, (a0), v12
+	vluxseg8ei32.v v4, (a0), v12
+	vsuxseg8ei32.v v4, (a0), v12
+	vluxseg2ei64.v v4, (a0), v12
+	vsuxseg2ei64.v v4, (a0), v12
+	vluxseg3ei64.v v4, (a0), v12
+	vsuxseg3ei64.v v4, (a0), v12
+	vluxseg4ei64.v v4, (a0), v12
+	vsuxseg4ei64.v v4, (a0), v12
+	vluxseg5ei64.v v4, (a0), v12
+	vsuxseg5ei64.v v4, (a0), v12
+	vluxseg6ei64.v v4, (a0), v12
+	vsuxseg6ei64.v v4, (a0), v12
+	vluxseg7ei64.v v4, (a0), v12
+	vsuxseg7ei64.v v4, (a0), v12
+	vluxseg8ei64.v v4, (a0), v12
+	vsuxseg8ei64.v v4, (a0), v12
+
+	vlseg2e8ff.v v4, (a0)
+	vlseg3e8ff.v v4, (a0)
+	vlseg4e8ff.v v4, (a0)
+	vlseg5e8ff.v v4, (a0)
+	vlseg6e8ff.v v4, (a0)
+	vlseg7e8ff.v v4, (a0)
+	vlseg8e8ff.v v4, (a0)
+	vlseg2e16ff.v v4, (a0)
+	vlseg3e16ff.v v4, (a0)
+	vlseg4e16ff.v v4, (a0)
+	vlseg5e16ff.v v4, (a0)
+	vlseg6e16ff.v v4, (a0)
+	vlseg7e16ff.v v4, (a0)
+	vlseg8e16ff.v v4, (a0)
+	vlseg2e32ff.v v4, (a0)
+	vlseg3e32ff.v v4, (a0)
+	vlseg4e32ff.v v4, (a0)
+	vlseg5e32ff.v v4, (a0)
+	vlseg6e32ff.v v4, (a0)
+	vlseg7e32ff.v v4, (a0)
+	vlseg8e32ff.v v4, (a0)
+	vlseg2e64ff.v v4, (a0)
+	vlseg3e64ff.v v4, (a0)
+	vlseg4e64ff.v v4, (a0)
+	vlseg5e64ff.v v4, (a0)
+	vlseg6e64ff.v v4, (a0)
+	vlseg7e64ff.v v4, (a0)
+	vlseg8e64ff.v v4, (a0)
+
+	vl1r.v v3, (a0)
+	vl1re8.v v3, (a0)
+	vl1re16.v v3, (a0)
+	vl1re32.v v3, (a0)
+	vl1re64.v v3, (a0)
+	vl2r.v v2, (a0)
+	vl2re8.v v2, (a0)
+	vl2re16.v v2, (a0)
+	vl2re32.v v2, (a0)
+	vl2re64.v v2, (a0)
+	vl4r.v v4, (a0)
+	vl4re8.v v4, (a0)
+	vl4re16.v v4, (a0)
+	vl4re32.v v4, (a0)
+	vl4re64.v v4, (a0)
+	vl8r.v v8, (a0)
+	vl8re8.v v8, (a0)
+	vl8re16.v v8, (a0)
+	vl8re32.v v8, (a0)
+	vl8re64.v v8, (a0)
+
+	vs1r.v v3, (a1)
+	vs2r.v v2, (a1)
+	vs4r.v v4, (a1)
+	vs8r.v v8, (a1)
+
+	vamoaddei8.v v4, (a1), v8, v4
+	vamoswapei8.v v4, (a1), v8, v4
+	vamoxorei8.v v4, (a1), v8, v4
+	vamoandei8.v v4, (a1), v8, v4
+	vamoorei8.v v4, (a1), v8, v4
+	vamominei8.v v4, (a1), v8, v4
+	vamomaxei8.v v4, (a1), v8, v4
+	vamominuei8.v v4, (a1), v8, v4
+	vamomaxuei8.v v4, (a1), v8, v4
+	vamoaddei8.v v4, 0(a1), v8, v4
+	vamoswapei8.v v4, 0(a1), v8, v4
+	vamoxorei8.v v4, 0(a1), v8, v4
+	vamoandei8.v v4, 0(a1), v8, v4
+	vamoorei8.v v4, 0(a1), v8, v4
+	vamominei8.v v4, 0(a1), v8, v4
+	vamomaxei8.v v4, 0(a1), v8, v4
+	vamominuei8.v v4, 0(a1), v8, v4
+	vamomaxuei8.v v4, 0(a1), v8, v4
+
+	vamoaddei16.v v4, (a1), v8, v4
+	vamoswapei16.v v4, (a1), v8, v4
+	vamoxorei16.v v4, (a1), v8, v4
+	vamoandei16.v v4, (a1), v8, v4
+	vamoorei16.v v4, (a1), v8, v4
+	vamominei16.v v4, (a1), v8, v4
+	vamomaxei16.v v4, (a1), v8, v4
+	vamominuei16.v v4, (a1), v8, v4
+	vamomaxuei16.v v4, (a1), v8, v4
+	vamoaddei16.v v4, 0(a1), v8, v4
+	vamoswapei16.v v4, 0(a1), v8, v4
+	vamoxorei16.v v4, 0(a1), v8, v4
+	vamoandei16.v v4, 0(a1), v8, v4
+	vamoorei16.v v4, 0(a1), v8, v4
+	vamominei16.v v4, 0(a1), v8, v4
+	vamomaxei16.v v4, 0(a1), v8, v4
+	vamominuei16.v v4, 0(a1), v8, v4
+	vamomaxuei16.v v4, 0(a1), v8, v4
+
+	vamoaddei32.v v4, (a1), v8, v4
+	vamoswapei32.v v4, (a1), v8, v4
+	vamoxorei32.v v4, (a1), v8, v4
+	vamoandei32.v v4, (a1), v8, v4
+	vamoorei32.v v4, (a1), v8, v4
+	vamominei32.v v4, (a1), v8, v4
+	vamomaxei32.v v4, (a1), v8, v4
+	vamominuei32.v v4, (a1), v8, v4
+	vamomaxuei32.v v4, (a1), v8, v4
+	vamoaddei32.v v4, 0(a1), v8, v4
+	vamoswapei32.v v4, 0(a1), v8, v4
+	vamoxorei32.v v4, 0(a1), v8, v4
+	vamoandei32.v v4, 0(a1), v8, v4
+	vamoorei32.v v4, 0(a1), v8, v4
+	vamominei32.v v4, 0(a1), v8, v4
+	vamomaxei32.v v4, 0(a1), v8, v4
+	vamominuei32.v v4, 0(a1), v8, v4
+	vamomaxuei32.v v4, 0(a1), v8, v4
+
+	vamoaddei64.v v4, (a1), v8, v4
+	vamoswapei64.v v4, (a1), v8, v4
+	vamoxorei64.v v4, (a1), v8, v4
+	vamoandei64.v v4, (a1), v8, v4
+	vamoorei64.v v4, (a1), v8, v4
+	vamominei64.v v4, (a1), v8, v4
+	vamomaxei64.v v4, (a1), v8, v4
+	vamominuei64.v v4, (a1), v8, v4
+	vamomaxuei64.v v4, (a1), v8, v4
+	vamoaddei64.v v4, 0(a1), v8, v4
+	vamoswapei64.v v4, 0(a1), v8, v4
+	vamoxorei64.v v4, 0(a1), v8, v4
+	vamoandei64.v v4, 0(a1), v8, v4
+	vamoorei64.v v4, 0(a1), v8, v4
+	vamominei64.v v4, 0(a1), v8, v4
+	vamomaxei64.v v4, 0(a1), v8, v4
+	vamominuei64.v v4, 0(a1), v8, v4
+	vamomaxuei64.v v4, 0(a1), v8, v4

gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.d

@@ -0,0 +1,3 @@
+#as: -march=rv32i_zvl65536b
+#source: ../empty.s
+#error_output: vector-insns-fail-zvl.l

gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.l

@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*Error: zvl\*b extensions need to enable either `v' or `zve' extension

gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d

@@ -0,0 +1,29 @@
+#as: -march=rv32iv
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+6e85c257[ 	]+vmslt.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
+[ 	]+[0-9a-f]+:[ 	]+6cc64457[ 	]+vmslt.vx[ 	]+v8,v12,a2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
+[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandn.mm[ 	]+v0,v0,v12
+[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandn.mm[ 	]+v12,v0,v12
+[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandn.mm[ 	]+v4,v4,v0
+[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
+[ 	]+[0-9a-f]+:[ 	]+6a85c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
+[ 	]+[0-9a-f]+:[ 	]+68c64457[ 	]+vmsltu.vx[ 	]+v8,v12,a2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
+[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandn.mm[ 	]+v0,v0,v12
+[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandn.mm[ 	]+v12,v0,v12
+[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandn.mm[ 	]+v4,v4,v0
+[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4

gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.s

@@ -0,0 +1,9 @@
+	vmsge.vx v4, v8, a1		# unmasked va >= x
+	vmsge.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
+	vmsge.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
+	vmsge.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
+
+	vmsgeu.vx v4, v8, a1		# unmasked va >= x
+	vmsgeu.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
+	vmsgeu.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
+	vmsgeu.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd

gas/testsuite/gas/riscv/extended/vector-insns-zero-imm.d

@@ -0,0 +1,17 @@
+#as: -march=rv32ifv
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+768fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1
+[ 	]+[0-9a-f]+:[ 	]+748fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+66840257[ 	]+vmsne.vv[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+64840257[ 	]+vmsne.vv[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+7e8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1
+[ 	]+[0-9a-f]+:[ 	]+7c8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62840257[ 	]+vmseq.vv[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+60840257[ 	]+vmseq.vv[ 	]+v4,v8,v8,v0.t

gas/testsuite/gas/riscv/extended/vector-insns-zero-imm.s

@@ -0,0 +1,8 @@
+	vmslt.vi v4, v8, 0
+	vmslt.vi v4, v8, 0, v0.t
+	vmsltu.vi v4, v8, 0
+	vmsltu.vi v4, v8, 0, v0.t
+	vmsge.vi v4, v8, 0
+	vmsge.vi v4, v8, 0, v0.t
+	vmsgeu.vi v4, v8, 0
+	vmsgeu.vi v4, v8, 0, v0.t

include/opcode/riscv.h

@@ -22,6 +22,7 @@
 #define _RISCV_H_
 
 #include "riscv-opc.h"
+#include "riscv-opc-extended.h"
 #include <stdlib.h>
 #include <stdint.h>
 
@@ -303,7 +304,6 @@ static const char * const riscv_pred_succ[16] =
 enum riscv_insn_class
 {
   INSN_CLASS_NONE,
-
   INSN_CLASS_I,
   INSN_CLASS_C,
   INSN_CLASS_A,
@@ -320,6 +320,7 @@ enum riscv_insn_class
   INSN_CLASS_ZBB,
   INSN_CLASS_ZBC,
   INSN_CLASS_ZBS,
+  INSN_CLASS_EXTENDED
 };
 
 /* This structure holds information for a particular instruction.  */
@@ -333,7 +334,7 @@ struct riscv_opcode
 
   /* Class to which this instruction belongs.  Used to decide whether or
      not this instruction is legal in the current -march context.  */
-  enum riscv_insn_class insn_class;
+  int insn_class;
 
   /* A string describing the arguments for this instruction.  */
   const char *args;
@@ -352,7 +353,8 @@ struct riscv_opcode
 
   /* A function to determine if a word corresponds to this instruction.
      Usually, this computes ((word & mask) == match).  */
-  int (*match_func) (const struct riscv_opcode *op, insn_t word);
+  int (*match_func) (const struct riscv_opcode *op, insn_t word,
+		     int constraints, const char **error);
 
   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
      of bits describing the instruction, notably any relevant hazard
@@ -423,7 +425,7 @@ enum
   M_ZEXTW,
   M_SEXTB,
   M_SEXTH,
-  M_NUM_MACROS
+  M_EXTENDED
 };
 
 /* The mapping symbol states.  */
@@ -442,4 +444,116 @@ extern const char * const riscv_fpr_names_abi[NFPR];
 extern const struct riscv_opcode riscv_opcodes[];
 extern const struct riscv_opcode riscv_insn_types[];
 
+/* Extended extensions.  */
+
+/* The insn_info fields.  */
+#define INSN_V_EEW64		0x10000000
+/* RVV IMM encodings.  */
+#define EXTRACT_RVV_VI_IMM(x) \
+  (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
+#define EXTRACT_RVV_VI_UIMM(x) \
+  (RV_X(x, 15, 5))
+#define EXTRACT_RVV_OFFSET(x) \
+  (RV_X(x, 29, 3))
+#define EXTRACT_RVV_VB_IMM(x) \
+  (RV_X(x, 20, 10))
+#define EXTRACT_RVV_VC_IMM(x) \
+  (RV_X(x, 20, 11))
+#define ENCODE_RVV_VB_IMM(x) \
+  (RV_X(x, 0, 10) << 20)
+#define ENCODE_RVV_VC_IMM(x) \
+  (RV_X(x, 0, 11) << 20)
+#define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
+#define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
+/* RVV fields.  */
+#define OP_MASK_VD		0x1f
+#define OP_SH_VD		7
+#define OP_MASK_VS1		0x1f
+#define OP_SH_VS1		15
+#define OP_MASK_VS2		0x1f
+#define OP_SH_VS2		20
+#define OP_MASK_VIMM		0x1f
+#define OP_SH_VIMM		15
+#define OP_MASK_VMASK		0x1
+#define OP_SH_VMASK		25
+#define OP_MASK_VFUNCT6		0x3f
+#define OP_SH_VFUNCT6		26
+#define OP_MASK_VLMUL		0x7
+#define OP_SH_VLMUL		0
+#define OP_MASK_VSEW		0x7
+#define OP_SH_VSEW		3
+#define OP_MASK_VTA		0x1
+#define OP_SH_VTA		6
+#define OP_MASK_VMA		0x1
+#define OP_SH_VMA		7
+#define OP_MASK_VTYPE_RES	0x1
+#define OP_SH_VTYPE_RES		10
+#define OP_MASK_VWD		0x1
+#define OP_SH_VWD		26
+/* RVV definitions.  */
+#define NVECR 32
+#define NVECM 1
+
+/* T-HEAD IMM Encoding.  */
+#define EXTRACT_VENDOR_THEAD_IMM(x,nbit,at) \
+  (RV_X(x, at, nbit))
+#define EXTRACT_VENDOR_THEAD_SIGN_IMM(x,nbit,at) \
+  (RV_X(x, at, nbit) | ((-(RV_X(x, (at+nbit-1),1))) << (nbit)))
+
+#define ENCODE_VENDOR_THEAD_IMM(x,nbit,at) \
+  (RV_X(x, 0, nbit) << at)
+#define ENCODE_VENDOR_THEAD_SIGN_IMM(x,nbit,at) \
+  (RV_X(x, 0, nbit) << at)
+
+#define VALID_VENDOR_THEAD_IMM(x,nbit,at) \
+  (EXTRACT_VENDOR_THEAD_IMM(ENCODE_VENDOR_THEAD_IMM(x,nbit,at),nbit,at) == (x))
+#define VALID_VENDOR_THEAD_SIGN_IMM(x,nbit,at) \
+  (EXTRACT_VENDOR_THEAD_SIGN_IMM(ENCODE_VENDOR_THEAD_SIGN_IMM(x,nbit,at),nbit,at) == (x))
+
+/* All RISC-V extended instructions belong to at least one of
+   these classes.  */
+enum riscv_extended_insn_class
+{
+  /* Draft */
+  INSN_CLASS_V = INSN_CLASS_EXTENDED,
+  INSN_CLASS_V_AND_F,
+  INSN_CLASS_ZVAMO,
+  INSN_CLASS_ZFH,
+  INSN_CLASS_D_AND_ZFH,
+  INSN_CLASS_Q_AND_ZFH,
+  INSN_CLASS_SVINVAL,
+
+  /* INSN class for THEAD.  */
+  INSN_CLASS_THEADC,
+  INSN_CLASS_THEADC_OR_THEADE,
+  INSN_CLASS_THEADC_OR_THEADE_OR_THEADSE,
+  INSN_CLASS_THEADE,
+  INSN_CLASS_THEADSE,
+
+  /* SiFive.  */
+  INSN_CLASS_XSF_CDISCARDDLONE,
+  INSN_CLASS_XSF_CFLUSHDLONE,
+  INSN_CLASS_XSF_CFLUSHILONE,
+};
+
+/* This is a list of macro expanded instructions for extended
+   extensions.  */
+enum
+{
+  M_VMSGE = M_EXTENDED,
+  M_VMSGEU,
+  M_FLH,
+  M_FSH,
+};
+
+/* RVV */
+extern const char * const riscv_vecr_names_numeric[NVECR];
+extern const char * const riscv_vecm_names_numeric[NVECM];
+extern const char * const riscv_vsew[8];
+extern const char * const riscv_vlmul[8];
+extern const char * const riscv_vta[2];
+extern const char * const riscv_vma[2];
+
+extern const struct riscv_opcode *riscv_extended_opcodes[];
+
 #endif /* _RISCV_H_ */

opcodes/riscv-dis.c

@@ -174,25 +174,179 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     pd->print_addr = (bfd_vma)(int32_t) pd->print_addr;
 }
 
+/* Print insn arguments for extended extensions.  */
+
+static bool
+print_extended_insn_args (const char **opcode_args,
+			  insn_t l,
+			  disassemble_info *info)
+{
+  fprintf_ftype print = info->fprintf_func;
+  const char *oparg = *opcode_args;
+
+  switch (*oparg)
+    {
+    case 'V': /* RVV */
+      switch (*++oparg)
+	{
+	case 'd':
+	case 'f':
+	  print (info->stream, "%s",
+		 riscv_vecr_names_numeric[EXTRACT_OPERAND (VD, l)]);
+	  break;
+
+	case 'e':
+	  if (!EXTRACT_OPERAND (VWD, l))
+	    print (info->stream, "%s", riscv_gpr_names[0]);
+	  else
+	    print (info->stream, "%s",
+		   riscv_vecr_names_numeric[EXTRACT_OPERAND (VD, l)]);
+	  break;
+
+	case 's':
+	  print (info->stream, "%s",
+		 riscv_vecr_names_numeric[EXTRACT_OPERAND (VS1, l)]);
+	  break;
+
+	case 't':
+	case 'u': /* VS1 == VS2 already verified at this point.  */
+	case 'v': /* VD == VS1 == VS2 already verified at this point.  */
+	  print (info->stream, "%s",
+		 riscv_vecr_names_numeric[EXTRACT_OPERAND (VS2, l)]);
+	  break;
+
+	case '0':
+	  print (info->stream, "%s", riscv_vecr_names_numeric[0]);
+	  break;
+
+	case 'b':
+	case 'c':
+	  {
+	    int imm = (*oparg == 'b') ? EXTRACT_RVV_VB_IMM (l)
+				      : EXTRACT_RVV_VC_IMM (l);
+	    unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm);
+	    unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
+	    unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
+	    unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
+	    unsigned int imm_vtype_res = EXTRACT_OPERAND (VTYPE_RES, imm);
+
+	    if (imm_vsew < ARRAY_SIZE (riscv_vsew)
+		&& imm_vlmul < ARRAY_SIZE (riscv_vlmul)
+		&& imm_vta < ARRAY_SIZE (riscv_vta)
+		&& imm_vma < ARRAY_SIZE (riscv_vma)
+		&& ! imm_vtype_res)
+	      print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew],
+		     riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
+		     riscv_vma[imm_vma]);
+	    else
+	      print (info->stream, "%d", imm);
+	  }
+	  break;
+
+	case 'i':
+	  print (info->stream, "%d", (int)EXTRACT_RVV_VI_IMM (l));
+	  break;
+
+	case 'j':
+	  print (info->stream, "%d", (int)EXTRACT_RVV_VI_UIMM (l));
+	  break;
+
+	case 'k':
+	  print (info->stream, "%d", (int)EXTRACT_RVV_OFFSET (l));
+	  break;
+
+	case 'm':
+	  if (! EXTRACT_OPERAND (VMASK, l))
+	      print (info->stream, ",%s", riscv_vecm_names_numeric[0]);
+	  break;
+
+	default:
+	  return false;
+	}
+      break;
+
+    case 'X':
+	{
+	  int nbit = 0;
+	  int at = -1;
+	  char c = 0;
+	  int shift = 0;
+	  oparg++;
+	  c = *oparg++;
+	  switch (c)
+	    {
+	    case 'I':
+	      nbit = strtol (oparg, (char **) &oparg, 10);
+	      if ((*oparg) =='@')
+		at = strtol (++oparg, (char **) &oparg, 10);
+
+	      oparg--;
+
+	      print (info->stream, "%d",
+		     (unsigned int) (EXTRACT_VENDOR_THEAD_IMM (l, nbit, at)
+				     << shift));
+	      break;
+
+	    case 'S':
+	      nbit = strtol (oparg, (char **) &oparg, 10);
+	      if ((*oparg) == '<' && (*(oparg + 1) == '<'))
+		{
+		  oparg += 2;
+		  shift = strtol (oparg, (char **) &oparg, 10);
+		}
+	      if ((*oparg) =='@')
+		at = strtol (++oparg, (char **) &oparg, 10);
+
+	      oparg--;
+
+	      print (info->stream, "%d",
+		     (unsigned) (EXTRACT_VENDOR_THEAD_SIGN_IMM (l, nbit, at)
+				 << shift));
+	      break;
+
+	    case 'g':
+	      nbit = strtol (oparg, (char **) &oparg, 10);
+	      if ((*oparg) =='@')
+		at = strtol (++oparg, (char **) &oparg, 10);
+
+	      oparg--;
+
+	      print (info->stream, "%s",
+		     riscv_gpr_names[EXTRACT_VENDOR_THEAD_IMM (l, nbit, at)]);
+	      break;
+	    }
+	}
+      break;
+
+    default:
+      return false;
+    }
+
+  *opcode_args = oparg;
+  return true;
+}
+
 /* Print insn arguments for 32/64-bit code.  */
 
 static void
-print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info)
 {
   struct riscv_private_data *pd = info->private_data;
   int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
   int rd = (l >> OP_SH_RD) & OP_MASK_RD;
   fprintf_ftype print = info->fprintf_func;
+  const char *opargStart;
 
-  if (*d != '\0')
+  if (*oparg != '\0')
     print (info->stream, "\t");
 
-  for (; *d != '\0'; d++)
+  for (; *oparg != '\0'; oparg++)
     {
-      switch (*d)
+      opargStart = oparg;
+      switch (*oparg)
 	{
 	case 'C': /* RVC */
-	  switch (*++d)
+	  switch (*++oparg)
 	    {
 	    case 's': /* RS1 x8-x15.  */
 	    case 'w': /* RS1 x8-x15.  */
@@ -281,12 +435,12 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 	case ')':
 	case '[':
 	case ']':
-	  print (info->stream, "%c", *d);
+	  print (info->stream, "%c", *oparg);
 	  break;
 
 	case '0':
 	  /* Only print constant 0 if it is the last argument.  */
-	  if (!d[1])
+	  if (!oparg[1])
 	    print (info->stream, "0");
 	  break;
 
@@ -415,6 +569,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
 		DECLARE_CSR (name, num, class, define_version, abort_version)
 #include "opcode/riscv-opc.h"
+#include "opcode/riscv-opc-extended.h"
 #undef DECLARE_CSR
 	      }
 
@@ -430,14 +585,86 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 	  break;
 
 	default:
-	  /* xgettext:c-format */
-	  print (info->stream, _("# internal error, undefined modifier (%c)"),
-		 *d);
-	  return;
+	  oparg = opargStart;
+	  if (!print_extended_insn_args (&oparg, l, info))
+	    {
+	      /* xgettext:c-format */
+	      print (info->stream,
+		     _("# internal error, undefined modifier (%s)"), opargStart);
+	      return;
+	    }
 	}
     }
 }
 
+/* Find the right opcode name when disassembling.  */
+
+static const struct riscv_opcode *
+riscv_disassemble_opcode (insn_t word,
+			  disassemble_info *info)
+{
+  static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
+  const struct riscv_opcode *op;
+  static bool init = 0;
+  unsigned xlen = 0;
+  unsigned int i;
+
+#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
+
+  /* Build a hash table to shorten the search time.  For now we just build
+     the hash for the standard instructions.  */
+  if (! init)
+    {
+      for (op = riscv_opcodes; op->name; op++)
+	if (!riscv_hash[OP_HASH_IDX (op->match)])
+	  riscv_hash[OP_HASH_IDX (op->match)] = op;
+
+      init = 1;
+    }
+
+  /* Search the standard instructions first.  */
+  op = riscv_hash[OP_HASH_IDX (word)];
+  i = 0;
+  do
+    {
+      /* The hash table entry might be NULL.  */
+      if (op != NULL)
+	{
+	  /* If XLEN is not known, get its value from the ELF class.  */
+	  if (info->mach == bfd_mach_riscv64)
+	    xlen = 64;
+	  else if (info->mach == bfd_mach_riscv32)
+	    xlen = 32;
+	  else if (info->section != NULL)
+	    {
+	      Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
+	      xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
+	    }
+
+	  for (; op->name; op++)
+	    {
+	      /* Does the opcode match?  */
+	      if (! (op->match_func) (op, word, 0, NULL))
+		continue;
+	      /* Is this a pseudo-instruction and may we print it as such?  */
+	      if (no_aliases && (op->pinfo & INSN_ALIAS))
+		continue;
+	      /* Is this instruction restricted to a certain value of XLEN?  */
+	      if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
+		continue;
+
+	      /* It's a match.  */
+	      return op;
+	    }
+	}
+      /* Keep searching extended opcode tables.  */
+      op = riscv_extended_opcodes[i++];
+    }
+  while (op != NULL);
+
+  return NULL;
+}
+
 /* Print the RISC-V instruction at address MEMADDR in debugged memory,
    on using INFO.  Returns length of the instruction, in bytes.
    BIGENDIAN must be 1 if this is big-endian code, 0 if
@@ -447,23 +674,9 @@ static int
 riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 {
   const struct riscv_opcode *op;
-  static bool init = 0;
-  static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
   struct riscv_private_data *pd;
   int insnlen;
 
-#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
-
-  /* Build a hash table to shorten the search time.  */
-  if (! init)
-    {
-      for (op = riscv_opcodes; op->name; op++)
-	if (!riscv_hash[OP_HASH_IDX (op->match)])
-	  riscv_hash[OP_HASH_IDX (op->match)] = op;
-
-      init = 1;
-    }
-
   if (info->private_data == NULL)
     {
       int i;
@@ -497,75 +710,48 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
   info->target = 0;
   info->target2 = 0;
 
-  op = riscv_hash[OP_HASH_IDX (word)];
+  op = riscv_disassemble_opcode (word, info);
   if (op != NULL)
     {
-      unsigned xlen = 0;
+      (*info->fprintf_func) (info->stream, "%s", op->name);
+      print_insn_args (op->args, word, memaddr, info);
 
-      /* If XLEN is not known, get its value from the ELF class.  */
-      if (info->mach == bfd_mach_riscv64)
-	xlen = 64;
-      else if (info->mach == bfd_mach_riscv32)
-	xlen = 32;
-      else if (info->section != NULL)
+      /* Try to disassemble multi-instruction addressing sequences.  */
+      if (pd->print_addr != (bfd_vma)-1)
 	{
-	  Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
-	  xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
+	  info->target = pd->print_addr;
+	  (*info->fprintf_func) (info->stream, " # ");
+	  (*info->print_address_func) (info->target, info);
+	  pd->print_addr = -1;
 	}
 
-      for (; op->name; op++)
+      /* Finish filling out insn_info fields.  */
+      switch (op->pinfo & INSN_TYPE)
 	{
-	  /* Does the opcode match?  */
-	  if (! (op->match_func) (op, word))
-	    continue;
-	  /* Is this a pseudo-instruction and may we print it as such?  */
-	  if (no_aliases && (op->pinfo & INSN_ALIAS))
-	    continue;
-	  /* Is this instruction restricted to a certain value of XLEN?  */
-	  if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
-	    continue;
-
-	  /* It's a match.  */
-	  (*info->fprintf_func) (info->stream, "%s", op->name);
-	  print_insn_args (op->args, word, memaddr, info);
-
-	  /* Try to disassemble multi-instruction addressing sequences.  */
-	  if (pd->print_addr != (bfd_vma)-1)
-	    {
-	      info->target = pd->print_addr;
-	      (*info->fprintf_func) (info->stream, " # ");
-	      (*info->print_address_func) (info->target, info);
-	      pd->print_addr = -1;
-	    }
-
-	  /* Finish filling out insn_info fields.  */
-	  switch (op->pinfo & INSN_TYPE)
-	    {
-	    case INSN_BRANCH:
-	      info->insn_type = dis_branch;
-	      break;
-	    case INSN_CONDBRANCH:
-	      info->insn_type = dis_condbranch;
-	      break;
-	    case INSN_JSR:
-	      info->insn_type = dis_jsr;
-	      break;
-	    case INSN_DREF:
-	      info->insn_type = dis_dref;
-	      break;
-	    default:
-	      break;
-	    }
-
-	  if (op->pinfo & INSN_DATA_SIZE)
-	    {
-	      int size = ((op->pinfo & INSN_DATA_SIZE)
-			  >> INSN_DATA_SIZE_SHIFT);
-	      info->data_size = 1 << (size - 1);
-	    }
-
-	  return insnlen;
+	case INSN_BRANCH:
+	  info->insn_type = dis_branch;
+	  break;
+	case INSN_CONDBRANCH:
+	  info->insn_type = dis_condbranch;
+	  break;
+	case INSN_JSR:
+	  info->insn_type = dis_jsr;
+	  break;
+	case INSN_DREF:
+	  info->insn_type = dis_dref;
+	  break;
+	default:
+	  break;
 	}
+
+      if (op->pinfo & INSN_DATA_SIZE)
+	{
+	  int size = ((op->pinfo & INSN_DATA_SIZE)
+		      >> INSN_DATA_SIZE_SHIFT);
+	  info->data_size = 1 << (size - 1);
+	}
+
+      return insnlen;
     }
 
   /* We did not find a match, so just print the instruction bits.  */