The new .debug_names reader will work by creating a cooked index from
.debug_names. This patch updates cooked_index::maybe_write_index to
avoid writing the index in this case.
However, in order to do this in a clean way, the readers are changed
so that a nullptr result from index_for_writing means "cannot be
done", and then the error message is moved into write_dwarf_index
(where it historically lived).
This moves the declaration of cooked_index_functions to
cooked-index.h. This makes it visible for use by the rewritten
.debug_names reader, and it also lets us move the implementation of
make_quick_functions into cooked-index.c, where it really belongs.
This adds a new 'lang' member to cooked_index_entry. This holds the
language of the symbol. This is primarily useful for the new
.debug_names reader, which will not scan the CUs for languages up
front.
This also changes cooked_index_shard::add to return a non-const
pointer. This doesn't impact the current code, but is needed for the
new reader.
GDB's new .debug_names implementation uses some extensions. This
patch adds some documentation on this to the manual.
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
While working on the previous patch, I saw that the handling of
quick-function installation could be unified
dwarf2_initialize_objfile. In particular, at the end of the function,
if there is an index table, then it can be used to create the quick
function object.
This cleanup will be useful when rewriting the .debug_names reader.
The new .debug_names reader will reuse the background reading
infrastructure of the cooked index code. In order to share the
handling of 'maint set dwarf synchronous' -- and to avoid having to
export this global -- this patch refactors this to be handled directly
in dwarf2_initialize_objfile.
Once in a while I'm looking at the gdb.log of an entire testsuite run, and I'm
trying to establish what glibc version is used. Sometimes this is possible,
sometimes not.
Make this easy by calling ldd --version in test-case
gdb.testsuite/dump-system-info.exp, which for instance on openSUSE Leap 15.4
gives:
...
$ ldd --version
ldd (GNU libc) 2.31
...
$
...
Tested on x86_64-linux.
Approved-By: Tom Tromey <tom@tromey.com>
We have APIs in sim-endian for working with 128-bit values like this code
is already doing for 8/16/32/64-bit values. Switch over to that to make
it a bit simpler, and drop the WITH_ALTIVEC check. The code probably is
only used when altivec is enabled, but it doesn't add much to always
compile it in, and avoids #ifdef rot by not actually compiling it.
This code creates a small buffer on the stack w/alloca, then proceeds to
write to it with a cast to a pointer type based on the register type, then
reads from it with a cast to a pointer type based on the register size.
gcc will flags only one of these lines as "maybe used uninitialized", but
it seems to track back to this memory abuse.
Create a large union with all the possible types that this code will read
or write as, and then use those. It's a bit ugly, but is probably better
than using raw memcpy's everywhere.
This corrects a counting problem, where prior to relocate_section relr
encoded relative relocs were allowed when it was known they were on
even boundaries, but relocate_section can only put relative relocs
(non-relr) on eight byte boundaries.
PR 30824
* elf64-ppc.c (RELR_ALIGN): Define, use throughout.
(maybe_relr): New function, use throughout.
Pass --hash-style=both to ld for -z mark-plt tests to support linker
configured with --enable-default-hash-style=gnu.
* testsuite/ld-x86-64/mark-plt-1b-x32.d: Pass --hash-style=both
to ld.
* testsuite/ld-x86-64/mark-plt-1b.d: Likewise.
* testsuite/ld-x86-64/mark-plt-1d-x32.d: Likewise.
* testsuite/ld-x86-64/mark-plt-1d.d: Likewise.
I got a report of a failure from Linaro's CI testing for the test
gdb.base/startup-with-shell.exp.
Looking at the log I see this:
(gdb) PASS: gdb.base/startup-with-shell.exp: startup_with_shell = on; run_args = *.unique-extension: inferior started
print argv[1]
$1 = 0xfffed978 "/home/tcwg-build/workspace/tcwg_gnu_4/abe/builds/armv8l-unknown-linux-gnueabihf/armv8l-unknown-linux-gnueabihf/gdb-gdb.git~master/gdb/testsuite/outputs/gdb.base/startup-with-shell/unique-file.unique-e"...
(gdb) FAIL: gdb.base/startup-with-shell.exp: startup_with_shell = on; run_args = *.unique-extension: first argument expanded
Notice that the value of $1 was truncated (indicated by the trailing
ellipses), and as a result it isn't going to match the expected output
pattern.
Avoid this by adding a call to 'set print characters unlimited' which
allows GDB to print strings of any length.
Approved-By: Tom de Vries <tdevries@suse.de>
When I run the struct-with-sig-2.exp test with the .debug_names-using
target board, I see a gdb crash. This happens because the reader
throws an exception without calling finalize_all_units. This causes
an assertion failure later because the number of CUs and TUs doesn't
match.
The fix is to clear 'all_units' on failure.
Approved-By: Tom de Vries <tdevries@suse.de>
I noticed that running the whole testsuite in serial mode (which means
all the .exp files are ran in the same TCL environment, one after the
other) with the native-extended-gdbserver board caused some weird
failures, for instance a lot of internal errors in the reverse tests,
like:
continue^M
Continuing.^M
/home/jenkins/workspace/binutils-gdb_master_linuxbuild/platform/deb12-amd64/target_board/native-extended-gdbserver/src/binutils-gdb/gdb/remot e.c:6922: internal-error: resume: Assertion `scope_ptid == inferior_ptid' failed.^M
A problem internal to GDB has been detected,^M
further debugging may prove unreliable.^M
----- Backtrace -----^M
FAIL: gdb.reverse/break-precsave.exp: run to end of main (GDB internal error)
This only happens after running gdb.multi/attach-while-running.exp.
That test does not restore GDBFLAGS properly when it's done, it leaves
`-ex \"maint set target-non-stop on\""` in there, which breaks some
subsequent tests. The problem is that this line:
save_vars { $::GDBFLAGS } {
should not use a `$` before the variable name. Passes the content of
`::GDBFLAGS` to save_vars, which is not what we want. We want to pass
the `::GDBFLAGS` string. Fix that.
Change-Id: I5ad32c527795fd10d0d94020e4fd15cebaca3a77
It occurred to me that there is no reason for addrmap_fixed::set_entry
to exist. This patch removes it and removes the abstract virtual
function from the base class. This then required a few minor changes
in the DWARF reader. I consider this a type-safety improvement.
Tested by rebuilding.
Reviewed-By: Tom de Vries <tdevries@suse.de>
Since SCFI isn't supported on x32:
Fatal error: SCFI is not supported for this ABI
skip SCFI tests for x32 targets.
PR gas/31245
* testsuite/gas/scfi/x86_64/scfi-x86-64.exp: Skip for x32
targets.
commit 1d506c26d9
Update copyright year range in header of all files managed by GDB
updated gnulib/Makefile.am but didn't regenerate gnulib/Makefile.in
also sim/Makefile.in was updated, but the Copyright hunks/years
were off. The first hunk comes from automake 1.15.1 header-vars.am
and so should have 2017 as last year, the second hunk does come from
sim/Makefile.am and so should have 2024 as last year.
* gnulib/Makefile.in: Regenerate.
* sim/Makefile.in: Likewise.
Along with the relevant unit-tests, this adds the following rcpc3
instructions:
STL1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAP1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]
LDAPUR <St>, [<Xn|SP>{, #<simm>}]
LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]
STLUR <Bt>, [<Xn|SP>{, #<simm>}]
STLUR <Ht>, [<Xn|SP>{, #<simm>}]
STLUR <St>, [<Xn|SP>{, #<simm>}]
STLUR <Dt>, [<Xn|SP>{, #<simm>}]
STLUR <Qt>, [<Xn|SP>{, #<simm>}]
with `#<simm>' taking on a signed 8-bit integer value in the range
[-256,255] and `index' the values 0 or 1.
Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Given the introduction of the new address operand types for rcpc3
instructions, this patch adds the necessary logic to teach
`general_constraint_met_p` how to proper handle these.
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
Beyond the need to encode any registers involved in data transfer and
the address base register for load/stores, it is necessary to specify
the data register addressing mode and whether the address register is
to be pre/post-indexed, whereby loads may be post-indexed and stores
pre-indexed with write-back.
The use of a single bit to specify both the indexing mode and indexing
value requires a novel function be written to accommodate this for
address operand insertion in assembly and another for extraction in
disassembly, along with the definition of two insn fields for use with
these instructions.
This therefore defines the following functions:
- aarch64_ins_rcpc3_addr_opt_offset
- aarch64_ins_rcpc3_addr_offset
- aarch64_ext_rcpc3_addr_opt_offset
- aarch64_ext_rcpc3_addr_offset
It extends the `do_special_{encoding|decoding}' functions and defines
two rcpc3 instruction fields:
- FLD_opc2
- FLD_rcpc3_size
The allowed immediate offsets in integer rcpc3 load store instructions
are not encoded explicitly in the instruction itself, being rather
implicitly equivalent to the amount of data loaded/stored by the
instruction.
This leads to the requirement that this quantity be calculated based on
the number of registers involved in the transfer, either as data
source or destination registers and their respective qualifiers.
This is done via `calc_ldst_datasize (const aarch64_opnd_info *opnds)'
implemented here, using a cumulative sum of qualifier sizes preceding
the address operand in the OPNDS operand list argument.
Indicating the presence of the Armv8.2-a feature adding further
support for the Release Consistency Model, the `+rcpc3' architectural
extension flag is added to the list of possible `-march' options in
Binutils, together with the necessary macro for encoding rcpc3
instructions.
This fixes the ld "Handle no DWARF information" testcase. Which
currently fails on riscv because a local label name is assumed
to be the current function name.
bfd/ChangeLog:
* elfnn-riscv.c (riscv_maybe_function_sym): Also check
_bfd_elf_is_local_label_name.
There are some tlbi operations that don't have a corresponding tlbip operation,
but we were incorrectly using the same list for both. Add the missing tlbi
*nxs operations, and use the F_REG_128 flag to filter tlbi operations that
don't have a tlbip analogue. For increased clarity, I have also used a macro
to reduce duplication between the 'nxs' and non-'nxs' variants, and added a
test to verify that no invalid combinations are accepted.
Additionally, fix two missing checks for AARCH64_OPND_SYSREG_TLBIP that were
preventing disassembly of tlbip instructions.
Hi,
This patch add support for SVE2.1 instructions ld1q,
ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction faddqv,
fmaxnmqv, fmaxqv, fminnmqv and fminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction dupq, eorqv and extq.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature
along with +sve2p1 optional flag to enabe this feature.
Also support for following SVE2p1 instructions is added
addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for FEAT_SME2p1 and "movaz" instructions
along with the optional flag +sme2p1.
Following "movaz" instructions are add:
Move and zero two ZA tile slices to vector registers.
Move and zero four ZA tile slices to vector registers.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
