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aarch64: Add the SVE FCLAMP instruction

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This commit is contained in:
Richard Sandiford
2023-03-30 11:09:18 +01:00
parent b368719a5a
commit e4cf4736e9
10 changed files with 873 additions and 760 deletions
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2
gas/testsuite/gas/aarch64/sme2-22-invalid.l
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@@ -1,5 +1,5 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `fclamp 0,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `fclamp 0,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fclamp {z0\.h-z1\.h},0,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fclamp {z0\.h-z1\.h},z0\.h,0'
[^ :]+:[0-9]+: Error: operand mismatch -- `fclamp {z0\.b-z1\.b},z0\.b,z0\.b'

3
gas/testsuite/gas/aarch64/sve2-sme2-7-invalid.d Normal file
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@@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: sve2-sme2-7-invalid.s
#error_output: sve2-sme2-7-invalid.l

29
gas/testsuite/gas/aarch64/sve2-sme2-7-invalid.l Normal file
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@@ -0,0 +1,29 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `fclamp 0,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fclamp z0\.h,0,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fclamp z0\.h,z0\.h,0'
[^ :]+:[0-9]+: Error: operand mismatch -- `fclamp z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fclamp z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fclamp z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fclamp z0\.d, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fclamp z0\.h,{z0\.h,z0\.h}'
[^ :]+:[0-9]+: Error: operand mismatch -- `fclamp z0\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fclamp z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fclamp z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fclamp z0\.d, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fclamp z0\.h,z0\.s,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fclamp z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fclamp z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fclamp z0\.d, z0\.d, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fclamp z0\.h,z0\.h,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fclamp z0\.h, z0\.h, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fclamp z0\.s, z0\.s, z0\.s
[^ :]+:[0-9]+: Info: fclamp z0\.d, z0\.d, z0\.d

9
gas/testsuite/gas/aarch64/sve2-sme2-7-invalid.s Normal file
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@@ -0,0 +1,9 @@
fclamp 0, z0.h, z0.h
fclamp z0.h, 0, z0.h
fclamp z0.h, z0.h, 0
fclamp z0.b, z0.b, z0.b
fclamp z0.h, { z0.h, z0.h }
fclamp z0.s, z0.h, z0.h
fclamp z0.h, z0.s, z0.h
fclamp z0.h, z0.h, z0.s

3
gas/testsuite/gas/aarch64/sve2-sme2-7-noarch.d Normal file
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@@ -0,0 +1,3 @@
#as: -march=armv8-a+sme
#source: sve2-sme2-7.s
#error_output: sve2-sme2-7-noarch.l

16
gas/testsuite/gas/aarch64/sve2-sme2-7-noarch.l Normal file
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@@ -0,0 +1,16 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z31\.h,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.h,z31\.h,z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.h,z0\.h,z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z9\.h,z22\.h,z21\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.s,z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z31\.s,z0\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.s,z31\.s,z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.s,z0\.s,z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z25\.s,z5\.s,z1\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z31\.d,z0\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.d,z31\.d,z0\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z0\.d,z0\.d,z31\.d'
[^ :]+:[0-9]+: Error: selected processor does not support `fclamp z3\.d,z30\.d,z28\.d'

24
gas/testsuite/gas/aarch64/sve2-sme2-7.d Normal file
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@@ -0,0 +1,24 @@
#as: -march=armv8-a+sme2
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: 64602400 fclamp z0\.h, z0\.h, z0\.h
[^:]+: 6460241f fclamp z31\.h, z0\.h, z0\.h
[^:]+: 646027e0 fclamp z0\.h, z31\.h, z0\.h
[^:]+: 647f2400 fclamp z0\.h, z0\.h, z31\.h
[^:]+: 647526c9 fclamp z9\.h, z22\.h, z21\.h
[^:]+: 64a02400 fclamp z0\.s, z0\.s, z0\.s
[^:]+: 64a0241f fclamp z31\.s, z0\.s, z0\.s
[^:]+: 64a027e0 fclamp z0\.s, z31\.s, z0\.s
[^:]+: 64bf2400 fclamp z0\.s, z0\.s, z31\.s
[^:]+: 64a124b9 fclamp z25\.s, z5\.s, z1\.s
[^:]+: 64e02400 fclamp z0\.d, z0\.d, z0\.d
[^:]+: 64e0241f fclamp z31\.d, z0\.d, z0\.d
[^:]+: 64e027e0 fclamp z0\.d, z31\.d, z0\.d
[^:]+: 64ff2400 fclamp z0\.d, z0\.d, z31\.d
[^:]+: 64fc27c3 fclamp z3\.d, z30\.d, z28\.d

17
gas/testsuite/gas/aarch64/sve2-sme2-7.s Normal file
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@@ -0,0 +1,17 @@
fclamp z0.h, z0.h, z0.h
fclamp z31.h, z0.h, z0.h
fclamp z0.h, z31.h, z0.h
fclamp z0.h, z0.h, z31.h
fclamp z9.h, z22.h, z21.h
fclamp z0.s, z0.s, z0.s
fclamp z31.s, z0.s, z0.s
fclamp z0.s, z31.s, z0.s
fclamp z0.s, z0.s, z31.s
fclamp z25.s, z5.s, z1.s
fclamp z0.d, z0.d, z0.d
fclamp z31.d, z0.d, z0.d
fclamp z0.d, z31.d, z0.d
fclamp z0.d, z0.d, z31.d
fclamp z3.d, z30.d, z28.d

1529
opcodes/aarch64-dis-2.c
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File diff suppressed because it is too large Load Diff

1
opcodes/aarch64-tbl.h
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@@ -5366,6 +5366,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSNC ("bfmlslt", 0x64e0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("fdot", 0x64204000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("fdot", 0x64208000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("fclamp", 0x64202400, 0xff20fc00, sme_size_22_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("sdot", 0x4480c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_19_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("sdot", 0x4400c800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSN ("sqcvtn", 0x45314000, 0xfffffc20, sve_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0),