Replace CET bit with IBT and SHSTK bits.

The latest specification for Intel CET technology defined two new bits instead of previously used CET bit. These are IBT and SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits. gas/ * config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk. (cpu_noarch): Add noibt, noshstk. (parse_insn): Change cpucet to cpuibt. * doc/c-i386.texi: Delete .cet. Add .ibt, .shstk. * testsuite/gas/i386/cet-ibt-inval.l: New test. * testsuite/gas/i386/cet-ibt-inval.s: Likewise. * testsuite/gas/i386/cet-shstk-inval.l: Likewise. * testsuite/gas/i386/cet-shstk-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise. * testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. (cpu_flags): Add CpuIBT, CpuSHSTK. * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. (i386_cpu_flags): Add cpuibt, cpushstk. * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2018-01-17 19:45:52 +03:00
parent 4bfce12836
commit d777820bf5
18 changed files with 5671 additions and 5563 deletions
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,18 @@
+2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
+	(cpu_noarch): Add noibt, noshstk.
+	(parse_insn): Change cpucet to cpuibt.
+	* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
+	* testsuite/gas/i386/cet-ibt-inval.l: New test.
+	* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
+	* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
+	* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
+	* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
+	* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
+	* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
+	* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.
+
 2018-01-16  Nick Clifton  <nickc@redhat.com>

 	* po/fr.po: Updated French translation.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -997,8 +997,10 @@ static const arch_entry cpu_arch[] =
    CPU_RDPID_FLAGS, 0 },
  { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
    CPU_PTWRITE_FLAGS, 0 },
-  { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
-    CPU_CET_FLAGS, 0 },
+  { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
+    CPU_IBT_FLAGS, 0 },
+  { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
+    CPU_SHSTK_FLAGS, 0 },
  { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
    CPU_GFNI_FLAGS, 0 },
  { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
@@ -1038,6 +1040,8 @@ static const noarch_entry cpu_noarch[] =
  { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
  { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
  { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
+  { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
+  { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
 };

 #ifdef I386COFF
@@ -4048,7 +4052,7 @@ parse_insn (char *line, char *mnemonic)
 		case PREFIX_EXIST:
 		  return NULL;
 		case PREFIX_DS:
-		  if (current_templates->start->cpu_flags.bitfield.cpucet)
+		  if (current_templates->start->cpu_flags.bitfield.cpuibt)
 		    i.notrack_prefix = current_templates->start->name;
 		  break;
 		case PREFIX_REP:
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -1239,12 +1239,12 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
@item @samp{.avx512_bitalg}
-@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.cet}
+@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
+@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
-@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.gfni}
-@item @samp{.vaes} @tab @samp{.vpclmulqdq}
+@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
@end multitable

 Apart from the warning, there are only two other effects on
--- a/gas/testsuite/gas/i386/cet-ibt-inval.l
+++ b/gas/testsuite/gas/i386/cet-ibt-inval.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:6: Error: `endbr32' is not supported on `i386.noibt'
+.*:7: Error: `endbr64' is not supported on `i386.noibt'
--- a/gas/testsuite/gas/i386/cet-ibt-inval.s
+++ b/gas/testsuite/gas/i386/cet-ibt-inval.s
@@ -0,0 +1,7 @@
+	.arch .ibt
+	endbr32
+	endbr64
+
+	.arch .noibt
+	endbr32
+	endbr64
--- a/gas/testsuite/gas/i386/cet-shstk-inval.l
+++ b/gas/testsuite/gas/i386/cet-shstk-inval.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:6: Error: `incsspd' is not supported on `i386.noshstk'
+.*:7: Error: `rdsspd' is not supported on `i386.noshstk'
--- a/gas/testsuite/gas/i386/cet-shstk-inval.s
+++ b/gas/testsuite/gas/i386/cet-shstk-inval.s
@@ -0,0 +1,7 @@
+	.arch .shstk
+	incsspd %ecx
+	rdsspd %ecx
+
+	.arch .noshstk
+	incsspd %ecx
+	rdsspd %ecx
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -418,6 +418,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
    run_dump_test "fpu-bad"
    run_dump_test "cet"
    run_dump_test "cet-intel"
+    run_list_test "cet-ibt-inval"
+    run_list_test "cet-shstk-inval"
    run_dump_test "pseudos"
    run_dump_test "notrack"
    run_dump_test "notrack-intel"
@@ -886,6 +888,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
    run_dump_test "x86-64-opcode-bad"
    run_dump_test "x86-64-cet"
    run_dump_test "x86-64-cet-intel"
+    run_list_test "x86-64-cet-ibt-inval"
+    run_list_test "x86-64-cet-shstk-inval"
    run_dump_test "x86-64-pseudos"
    run_dump_test "x86-64-notrack"
    run_dump_test "x86-64-notrack-intel"
--- a/gas/testsuite/gas/i386/x86-64-cet-ibt-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-cet-ibt-inval.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:6: Error: `endbr32' is not supported on `x86_64.noibt'
+.*:7: Error: `endbr64' is not supported on `x86_64.noibt'
--- a/gas/testsuite/gas/i386/x86-64-cet-ibt-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-cet-ibt-inval.s
@@ -0,0 +1,7 @@
+	.arch .ibt
+	endbr32
+	endbr64
+
+	.arch .noibt
+	endbr32
+	endbr64
--- a/gas/testsuite/gas/i386/x86-64-cet-shstk-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-cet-shstk-inval.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:6: Error: `incsspd' is not supported on `x86_64.noshstk'
+.*:7: Error: `rdsspd' is not supported on `x86_64.noshstk'
--- a/gas/testsuite/gas/i386/x86-64-cet-shstk-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-cet-shstk-inval.s
@@ -0,0 +1,7 @@
+	.arch .shstk
+	incsspd %ecx
+	rdsspd %ecx
+
+	.arch .noshstk
+	incsspd %ecx
+	rdsspd %ecx
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
+
+	* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
+	Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
+	CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
+	(cpu_flags): Add CpuIBT, CpuSHSTK.
+	* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
+	(i386_cpu_flags): Add cpuibt, cpushstk.
+	* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
+	* i386-init.h: Regenerate.
+	* i386-tbl.h: Likewise.
+
 2018-01-16  Nick Clifton  <nickc@redhat.com>

 	* po/pt_BR.po: Updated Brazilian Portugese translation.
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -269,8 +269,10 @@ static initializer cpu_flag_init[] =
    "CpuRDPID" },
  { "CPU_PTWRITE_FLAGS",
    "CpuPTWRITE" },
-  { "CPU_CET_FLAGS",
-    "CpuCET" },
+  { "CPU_IBT_FLAGS",
+    "CpuIBT" },
+  { "CPU_SHSTK_FLAGS",
+    "CpuSHSTK" },
  { "CPU_GFNI_FLAGS",
    "CpuGFNI" },
  { "CPU_VAES_FLAGS",
@@ -327,6 +329,10 @@ static initializer cpu_flag_init[] =
    "CpuAVX512_4VNNIW" },
  { "CPU_ANY_AVX512_VPOPCNTDQ_FLAGS",
    "CpuAVX512_VPOPCNTDQ" },
+  { "CPU_ANY_IBT_FLAGS",
+    "CpuIBT" },
+  { "CPU_ANY_SHSTK_FLAGS",
+    "CpuSHSTK" },
  { "CPU_ANY_AVX512_VBMI2_FLAGS",
    "CpuAVX512_VBMI2" },
  { "CPU_ANY_AVX512_VNNI_FLAGS",
@@ -558,7 +564,8 @@ static bitfield cpu_flags[] =
  BITFIELD (CpuOSPKE),
  BITFIELD (CpuRDPID),
  BITFIELD (CpuPTWRITE),
-  BITFIELD (CpuCET),
+  BITFIELD (CpuIBT),
+  BITFIELD (CpuSHSTK),
  BITFIELD (CpuGFNI),
  BITFIELD (CpuVAES),
  BITFIELD (CpuVPCLMULQDQ),
--- a/opcodes/i386-init.h
+++ b/opcodes/i386-init.h
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -214,8 +214,9 @@ enum
  CpuRDPID,
  /* PTWRITE instruction required */
  CpuPTWRITE,
-  /* CET instruction support required */
-  CpuCET,
+  /* CET instructions support required */
+  CpuIBT,
+  CpuSHSTK,
  /* GFNI instructions required */
  CpuGFNI,
  /* VAES instructions required */
@@ -346,7 +347,8 @@ typedef union i386_cpu_flags
      unsigned int cpuospke:1;
      unsigned int cpurdpid:1;
      unsigned int cpuptwrite:1;
-      unsigned int cpucet:1;
+      unsigned int cpuibt:1;
+      unsigned int cpushstk:1;
      unsigned int cpugfni:1;
      unsigned int cpuvaes:1;
      unsigned int cpuvpclmulqdq:1;
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -6114,22 +6114,22 @@ ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf

 // CET instructions.

-incsspd, 1, 0xf30fae, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
-incsspq, 1, 0xf30fae, 0x5, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
-rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
-rdsspq, 1, 0xf30f1e, 0x1, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
-saveprevssp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-rstorssp, 1, 0xf30f01, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
-wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex }
-wrssq, 2, 0x0f38f6, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex }
-wrussd, 2, 0x660f38f5, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex }
-wrussq, 2, 0x660f38f5, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex }
-setssbsy, 0, 0xf30f01e8, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-clrssbsy, 1, 0xf30fae, 0x6, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
-endbr64, 0, 0xf30f1efa, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-endbr32, 0, 0xf30f1efb, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+incsspd, 1, 0xf30fae, 0x5, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
+incsspq, 1, 0xf30fae, 0x5, 2, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
+rdsspd, 1, 0xf30f1e, 0x1, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
+rdsspq, 1, 0xf30f1e, 0x1, 2, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 }
+saveprevssp, 0, 0xf30f01ea, None, 3, CpuSHSTK, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+rstorssp, 1, 0xf30f01, 0x5, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
+wrssd, 2, 0x0f38f6, None, 3, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex }
+wrssq, 2, 0x0f38f6, None, 3, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex }
+wrussd, 2, 0x660f38f5, None, 3, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex }
+wrussq, 2, 0x660f38f5, None, 3, CpuSHSTK|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex }
+setssbsy, 0, 0xf30f01e8, None, 3, CpuSHSTK, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+clrssbsy, 1, 0xf30fae, 0x6, 2, CpuSHSTK, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
+endbr64, 0, 0xf30f1efa, None, 3, CpuIBT, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+endbr32, 0, 0xf30f1efb, None, 3, CpuIBT, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }

 // notrack prefix
-notrack, 0, 0x3e, None, 1, CpuCET, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+notrack, 0, 0x3e, None, 1, CpuIBT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }

 // CET instructions end.
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h