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aarch64: add E3DSE feature and its associated registers

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AArch64 defines new registers for the feature e3dse (Delegated SError
exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A
feature.

This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
This commit is contained in:
Matthieu Longo
2024-06-19 20:08:17 +01:00
parent 97bf50bb61
commit a15809c010
6 changed files with 39 additions and 1 deletions
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3
gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.d Normal file
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@@ -0,0 +1,3 @@
#source: armv9_5-a-sysregs.s
#as: -march=armv9.4-a -I$srcdir/$subdir
#error_output: armv9_5-a-sysregs-archv9_4-unsupported.l

9
gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l Normal file
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@@ -0,0 +1,9 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el3'
[^ :]+:[0-9]+: Info: macro invoked from here
[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vdisr_el3'
[^ :]+:[0-9]+: Info: macro invoked from here
[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el3'
[^ :]+:[0-9]+: Info: macro invoked from here
[^ :]+:[0-9]+: Error: selected processor does not support system register name 'vsesr_el3'
[^ :]+:[0-9]+: Info: macro invoked from here

13
gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d Normal file
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@@ -0,0 +1,13 @@
#source: armv9_5-a-sysregs.s
#as: -march=armv9.5-a -I$srcdir/$subdir
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: d51ec120 msr vdisr_el3, x0
.*: d53ec120 mrs x0, vdisr_el3
.*: d51e5260 msr vsesr_el3, x0
.*: d53e5260 mrs x0, vsesr_el3

7
gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s Normal file
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@@ -0,0 +1,7 @@
.include "sysreg-test-utils.inc"
.text
/* Delegated SError exceptions for EL3. */
rw_sys_reg sys_reg=vdisr_el3 xreg=x0 r=1 w=1
rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1

6
include/opcode/aarch64.h
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@@ -183,6 +183,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_LSE128,
/* ARMv8.9-A RAS Extensions. */
AARCH64_FEATURE_RASv2,
/* Delegated SError exceptions for EL3. */
AARCH64_FEATURE_E3DSE,
/* System Control Register2. */
AARCH64_FEATURE_SCTLR2,
/* Fine Grained Traps. */
@@ -366,7 +368,9 @@ enum aarch64_feature_bit {
#define AARCH64_ARCH_V9_5A_FEATURES(X) (AARCH64_FEATBIT (X, V9_5A) \
| AARCH64_FEATBIT (X, CPA) \
| AARCH64_FEATBIT (X, LUT) \
| AARCH64_FEATBIT (X, FAMINMAX))
| AARCH64_FEATBIT (X, FAMINMAX)\
| AARCH64_FEATBIT (X, E3DSE) \
)
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \

2
opcodes/aarch64-sys-regs.def
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@@ -1229,6 +1229,7 @@
SYSREG ("vbar_el2", CPENC (3,4,12,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vbar_el3", CPENC (3,6,12,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vdisr_el2", CPENC (3,4,12,1,1), F_ARCHEXT, AARCH64_FEATURE (RAS))
SYSREG ("vdisr_el3", CPENC (3,6,12,1,1), F_ARCHEXT, AARCH64_FEATURE (E3DSE))
SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), 0, AARCH64_NO_FEATURES)
SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vmpidr_el2", CPENC (3,4,0,0,5), 0, AARCH64_NO_FEATURES)
@@ -1236,6 +1237,7 @@
SYSREG ("vpidr_el2", CPENC (3,4,0,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vsctlr_el2", CPENC (3,4,2,0,0), F_ARCHEXT, AARCH64_FEATURE (V8R))
SYSREG ("vsesr_el2", CPENC (3,4,5,2,3), F_ARCHEXT, AARCH64_FEATURE (RAS))
SYSREG ("vsesr_el3", CPENC (3,6,5,2,3), F_ARCHEXT, AARCH64_FEATURE (E3DSE))
SYSREG ("vstcr_el2", CPENC (3,4,2,6,2), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("vsttbr_el2", CPENC (3,4,2,6,0), F_ARCHEXT, AARCH64_FEATURES (2, V8A, V8_4A))
SYSREG ("vtcr_el2", CPENC (3,4,2,1,2), 0, AARCH64_NO_FEATURES)