forked from Imagelibrary/binutils-gdb
checkpoint
This commit is contained in:
Doug Evans
@@ -22,8 +22,8 @@ Boston, MA 02111-1307, USA. */
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/* Type to denote a TXVU instruction (at least a 32 bit unsigned int). */
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typedef unsigned int TXVU_INSN;
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/* Maximum number of operands an instruction can have. */
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#define TXVU_MAX_OPERANDS 8
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/* Maximum number of operands and syntax chars an instruction can have. */
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#define TXVU_MAX_OPERANDS 16
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struct txvu_opcode {
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char *mnemonic;
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@@ -94,8 +94,8 @@ struct txvu_operand {
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/* This operand is a long immediate value. */
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#define TXVU_OPERAND_LIMM 0x10
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/* This operand takes signed values. */
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#define TXVU_OPERAND_SIGNED 0x20
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/* This operand takes unsigned values (default is signed). */
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#define TXVU_OPERAND_UNSIGNED 0x20
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/* This operand takes signed values, but also accepts a full positive
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range of values. That is, if bits is 16, it takes any value from
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@@ -191,12 +191,13 @@ struct txvu_operand {
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/* Given an operand entry, return the table index. */
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#define TXVU_OPERAND_INDEX(op) ((op) - 128)
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/* Positions and masks of various fields. */
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/* Positions, masks, and values of various fields used in multiple places
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(the opcode table, the disassembler, GAS). */
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#define TXVU_SHIFT_DEST 21
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#define TXVU_SHIFT_FTREG 16
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#define TXVU_SHIFT_FSREG 11
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#define TXVU_SHIFT_FDREG 6
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#define TXVU_MASK_VFREG 31
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#define TXVU_SHIFT_TREG 16
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#define TXVU_SHIFT_SREG 11
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#define TXVU_SHIFT_DREG 6
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#define TXVU_MASK_REG 31
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#define TXVU_DEST_X 8
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#define TXVU_DEST_Y 4
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#define TXVU_DEST_Z 2
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@@ -54,6 +54,8 @@ INSERT_FN (dotdest);
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EXTRACT_FN (dotdest);
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PRINT_FN (dotdest);
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PARSE_FN (dotsdest);
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PARSE_FN (vfreg);
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PRINT_FN (vfreg);
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@@ -85,6 +87,9 @@ PRINT_FN (vi01);
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INSERT_FN (limm12);
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EXTRACT_FN (limm12);
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INSERT_FN (luimm15);
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EXTRACT_FN (luimm15);
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/* Various types of TXVU operands, including insn suffixes.
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Fields are:
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@@ -100,32 +105,37 @@ const struct txvu_operand txvu_operands[] =
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#define UNUSED 128
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{ 0 },
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/* Upper word operands. */
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/* Operands that exist in the same place for essentially the same purpose
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in both upper and lower instructions. */
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/* Destination indicator, with leading '.'. */
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#define UDOTDEST (UNUSED + 1)
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/* Destination indicator attached to mnemonic, with leading '.'.
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After parsing this, the value is stored in global `dest' so that the
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register parser can verify the same choice of xyzw is used. */
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#define DOTDEST (UNUSED + 1)
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{ 4, TXVU_SHIFT_DEST, TXVU_OPERAND_SUFFIX,
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parse_dotdest, insert_dotdest, extract_dotdest, print_dotdest },
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/* ft reg */
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#define UVFTREG (UDOTDEST + 1)
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{ 5, TXVU_SHIFT_FTREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* ft reg, with vector specification same as DOTDEST */
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#define VFTREG (DOTDEST + 1)
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{ 5, TXVU_SHIFT_TREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* fs reg */
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#define UVFSREG (UVFTREG + 1)
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{ 5, TXVU_SHIFT_FSREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* fs reg, with vector specification same as DOTDEST */
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#define VFSREG (VFTREG + 1)
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{ 5, TXVU_SHIFT_SREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* fd reg */
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#define UVFDREG (UVFSREG + 1)
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{ 5, TXVU_SHIFT_FDREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* fd reg, with vector specification same as DOTDEST */
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#define VFDREG (VFSREG + 1)
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{ 5, TXVU_SHIFT_DREG, 0, parse_vfreg, 0, 0, print_vfreg },
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/* Upper word operands. */
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/* broadcast */
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#define UBC (UVFDREG + 1)
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#define UBC (VFDREG + 1)
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{ 2, 0, 0, parse_bc, 0, 0, print_bc },
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/* ftreg in broadcast case */
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#define UBCFTREG (UBC + 1)
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{ 5, TXVU_SHIFT_FTREG, 0, parse_bcftreg, 0, 0, print_bcftreg },
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{ 5, TXVU_SHIFT_TREG, 0, parse_bcftreg, 0, 0, print_bcftreg },
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/* accumulator dest */
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#define UACCDEST (UBCFTREG + 1)
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@@ -139,11 +149,23 @@ const struct txvu_operand txvu_operands[] =
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/* Lower word operands. */
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/* 11 bit immediate. */
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#define LIMM11 (UXYZ + 1)
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#define LIMM5 (UXYZ + 1)
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{ 5, 6, 0, 0, 0, 0, 0 },
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/* 11 bit immediate. */
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#define LIMM11 (LIMM5 + 1)
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{ 11, 0, 0, 0, 0, 0, 0 },
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/* 15 bit unsigned immediate. */
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#define LUIMM15 (LIMM11 + 1)
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{ 15, 0, TXVU_OPERAND_UNSIGNED, 0, insert_luimm15, extract_luimm15, 0 },
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/* ID register. */
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#define LIDREG (LUIMM15 + 1)
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{ 5, 6, 0, parse_ireg, 0, 0, print_ireg },
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/* IS register. */
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#define LISREG (LIMM11 + 1)
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#define LISREG (LIDREG + 1)
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{ 5, 11, 0, parse_ireg, 0, 0, print_ireg },
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/* IT register. */
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@@ -174,6 +196,17 @@ const struct txvu_operand txvu_operands[] =
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#define LIMM12 (LIMM24 + 1)
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{ 12, 0, 0, 0, insert_limm12, extract_limm12, 0 },
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/* 11 bit pc-releative immediate. */
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#define LPCREL11 (LIMM12 + 1)
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{ 11, 0, TXVU_OPERAND_RELATIVE_BRANCH, 0, 0, 0, 0 },
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/* Destination indicator, with leading '.'. */
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#define LDOTSDEST (DOTDEST + 1)
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{ 4, TXVU_SHIFT_DEST, TXVU_OPERAND_SUFFIX,
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/* Note that we borrow the insert/extract/print functions from the
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vector case. */
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parse_dotsdest, insert_dotdest, extract_dotdest, print_dotdest },
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/* end of list place holder */
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{ 0 }
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};
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@@ -184,20 +217,32 @@ const struct txvu_operand txvu_operands[] =
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/* value X, B bits, shift S */
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#define R(x,b,s) (((x) & ((1 << (b)) - 1)) << (s))
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/* Field value macros for both upper and lower instructions.
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These shift a value into the right place in the instruction. */
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/* [FI] T reg field (remember it's V for value, not vector, here). */
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#define VT(x) R ((x), 5, TXVU_SHIFT_TREG)
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/* [FI] S reg field. */
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#define VS(x) R ((x), 5, TXVU_SHIFT_SREG)
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/* [FI] D reg field. */
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#define VD(x) R ((x), 5, TXVU_SHIFT_DREG)
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/* DEST field. */
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#define VDEST(x) R ((x), 4, 21)
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/* Masks for fields in both upper and lower instructions.
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These mask out all bits but the ones for the field in the instruction. */
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#define MT VT (~0)
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#define MS VS (~0)
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#define MD VD (~0)
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#define MDEST VDEST (~0)
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/* Upper instruction Value macros. */
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/* Upper Flag bits. */
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#define VUF(x) R ((x), 5, 27)
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/* Upper REServed two bits next to flag bits. */
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#define VURES(x) R ((x), 2, 25)
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/* DEST field. */
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#define VUDEST(x) R ((x), 4, 21)
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/* FT reg field. */
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#define VUFT(x) R ((x), 5, TXVU_SHIFT_FTREG)
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/* FS reg field. */
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#define VUFS(x) R ((x), 5, TXVU_SHIFT_FSREG)
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/* FD reg field. */
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#define VUFD(x) R ((x), 5, TXVU_SHIFT_FDREG)
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/* 4 bit opcode field. */
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#define VUOP4(x) R ((x), 4, 2)
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/* 6 bit opcode field. */
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@@ -209,7 +254,7 @@ const struct txvu_operand txvu_operands[] =
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/* BroadCast field. */
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#define VUBC(x) R ((x), 2, 0)
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/* Field masks. */
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/* Upper instruction field masks. */
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#define MUUBITS (VUF (~0) + VURES (~0))
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#define MURES VURES (~0)
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#define MUOP4 VUOP4 (~0)
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@@ -217,42 +262,6 @@ const struct txvu_operand txvu_operands[] =
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#define MUOP9 VUOP9 (~0)
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#define MUOP11 VUOP11 (~0)
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/* Lower instruction Value macros. */
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/* 7 bit opcode. */
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#define VLOP7(x) R ((x), 7, 25)
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/* 11 bit opcode. */
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#define VLOP11(x) R ((x), 11, 0)
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/* dest field. */
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#define VLDEST(x) R ((x), 4, 21)
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/* IT reg. */
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#define VLIT(x) R ((x), 5, 16)
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/* IS reg. */
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#define VLIS(x) R ((x), 5, 11)
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/* 11 bit immediate. */
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#define VLIMM11(x) R ((x), 11, 0)
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/* FTF field. */
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#define VLFTF(x) R ((x), 2, 23)
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/* FSF field. */
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#define VLFSF(x) R ((x), 2, 21)
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/* FT reg. */
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#define VLFT(x) R ((x), 5, 16)
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/* FS reg. */
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#define VLFS(x) R ((x), 5, 11)
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/* Field masks. */
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#define MLOP7 VLOP7 (~0)
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#define MLOP11 VLOP11 (~0)
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#define MLDEST VLDEST (~0)
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#define MLIT VLIT (~0)
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#define MLIS VLIS (~0)
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#define MLIMM11 VLIMM11 (~0)
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#define MLB24 R (1, 1, 24)
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/* 12 bit immediates are split into two parts, 1 bit and 11 bits.
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The upper 1 bit is part of the `dest' field. This mask is for the
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other 3 bits of the dest field. */
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#define MLIMM12TOP R (7, 3, 22)
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/* A space, separates instruction name (mnemonic + mnemonic operands) from operands. */
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#define SP ' '
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@@ -287,68 +296,94 @@ struct txvu_opcode txvu_upper_opcodes[] = {
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/* FIXME: When close to being finished, clean up by aligning fields. */
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/* The rest of these needn't be sorted, but it helps to find them if they are. */
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{ "abs", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x1fd) },
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{ "add", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x28) },
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{ "addi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x22) },
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{ "addq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x20) },
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{ "add", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (0) },
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{ "adda", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2bc) },
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{ "addai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x23e) },
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{ "addaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x23c) },
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{ "adda", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0xf) },
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{ "clip", { UDOTDEST, SP, UVFSREG }, MURES + VUDEST (~0) + VUFT (~0) + MUOP11, VUDEST (0xf) + VUOP11 (0x1ff) },
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{ "ftoi0", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x17c) },
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{ "ftoi4", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x17d) },
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{ "ftoi12", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x17e) },
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{ "ftoi15", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x17f) },
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{ "itof0", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x13c) },
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{ "itof4", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x13d) },
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{ "itof12", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x13e) },
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{ "itof15", { UDOTDEST, SP, UVFTREG, UVFSREG }, MURES + MUOP11, VUOP11 (0x13f) },
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{ "madd", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x29) },
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{ "maddi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x23) },
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{ "maddq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x21) },
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{ "madd", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x2) },
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{ "madda", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2bd) },
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{ "maddai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x23f) },
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{ "maddaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x23d) },
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{ "madda", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x2f) },
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{ "max", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2b) },
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{ "maxi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x2d) },
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{ "max", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x4) },
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{ "abs", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x1fd) },
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{ "add", { DOTDEST, SP, VFDREG, VFSREG, VFTREG }, MURES + MUOP6, VUOP6 (0x28) },
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{ "addi", { DOTDEST, SP, VFDREG, VFSREG, 'i' }, MURES + MT + MUOP6, VUOP6 (0x22) },
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{ "addq", { DOTDEST, SP, VFDREG, VFSREG, 'q' }, MURES + MT + MUOP6, VUOP6 (0x20) },
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{ "add", { UBC, DOTDEST, SP, VFDREG, VFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (0) },
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{ "adda", { DOTDEST, SP, UACCDEST, VFSREG, VFTREG }, MURES + MUOP11, VUOP11 (0x2bc) },
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{ "addai", { DOTDEST, SP, UACCDEST, VFSREG, 'i' }, MURES + MT + MUOP11, VUOP11 (0x23e) },
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{ "addaq", { DOTDEST, SP, UACCDEST, VFSREG, 'q' }, MURES + MT + MUOP11, VUOP11 (0x23c) },
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{ "adda", { UBC, DOTDEST, SP, UACCDEST, VFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0xf) },
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{ "clip", { DOTDEST, SP, VFSREG }, MURES + MDEST + MT + MUOP11, VDEST (0xf) + VUOP11 (0x1ff) },
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{ "ftoi0", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x17c) },
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{ "ftoi4", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x17d) },
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{ "ftoi12", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x17e) },
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{ "ftoi15", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x17f) },
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{ "itof0", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x13c) },
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{ "itof4", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x13d) },
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{ "itof12", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x13e) },
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{ "itof15", { DOTDEST, SP, VFTREG, VFSREG }, MURES + MUOP11, VUOP11 (0x13f) },
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{ "madd", { DOTDEST, SP, VFDREG, VFSREG, VFTREG }, MURES + MUOP6, VUOP6 (0x29) },
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{ "maddi", { DOTDEST, SP, VFDREG, VFSREG, 'i' }, MURES + MT + MUOP6, VUOP6 (0x23) },
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{ "maddq", { DOTDEST, SP, VFDREG, VFSREG, 'q' }, MURES + MT + MUOP6, VUOP6 (0x21) },
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{ "madd", { UBC, DOTDEST, SP, VFDREG, VFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x2) },
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{ "madda", { DOTDEST, SP, UACCDEST, VFSREG, VFTREG }, MURES + MUOP11, VUOP11 (0x2bd) },
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{ "maddai", { DOTDEST, SP, UACCDEST, VFSREG, 'i' }, MURES + MT + MUOP11, VUOP11 (0x23f) },
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{ "maddaq", { DOTDEST, SP, UACCDEST, VFSREG, 'q' }, MURES + MT + MUOP11, VUOP11 (0x23d) },
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{ "madda", { UBC, DOTDEST, SP, UACCDEST, VFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x2f) },
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{ "max", { DOTDEST, SP, VFDREG, VFSREG, VFTREG }, MURES + MUOP6, VUOP6 (0x2b) },
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{ "maxi", { DOTDEST, SP, VFDREG, VFSREG, 'i' }, MURES + MT + MUOP6, VUOP6 (0x2d) },
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{ "max", { UBC, DOTDEST, SP, VFDREG, VFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x4) },
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/* FIXME: mini or min? */
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{ "mini", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2f) },
|
||||
{ "mini", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x1f) },
|
||||
{ "mini", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x5) },
|
||||
{ "msub", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2d) },
|
||||
{ "msubi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x27) },
|
||||
{ "msubq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x25) },
|
||||
{ "msub", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x3) },
|
||||
{ "msuba", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2fd) },
|
||||
{ "msubai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x27f) },
|
||||
{ "msubaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x27d) },
|
||||
{ "msuba", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x3f) },
|
||||
{ "mul", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2a) },
|
||||
{ "muli", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x1e) },
|
||||
{ "mulq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x1c) },
|
||||
{ "mul", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (6) },
|
||||
{ "mula", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2be) },
|
||||
{ "mulai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x1fe) },
|
||||
{ "mulaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x1fc) },
|
||||
{ "mula", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x6f) },
|
||||
{ "nop", { 0 }, MURES + VUDEST (~0) + VUFT (~0) + VUFS (~0) + MUOP11, VUOP11 (0x2ff) },
|
||||
{ "opmula", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG, UXYZ }, MURES + MUOP11, VUOP11 (0x2fe) },
|
||||
{ "opmsub", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG, UXYZ }, MURES + MUOP6, VUOP6 (0x2e) },
|
||||
{ "sub", { UDOTDEST, SP, UVFDREG, UVFSREG, UVFTREG }, MURES + MUOP6, VUOP6 (0x2c) },
|
||||
{ "subi", { UDOTDEST, SP, UVFDREG, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x26) },
|
||||
{ "subq", { UDOTDEST, SP, UVFDREG, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP6, VUOP6 (0x24) },
|
||||
{ "sub", { UBC, UDOTDEST, SP, UVFDREG, UVFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (1) },
|
||||
{ "suba", { UDOTDEST, SP, UACCDEST, UVFSREG, UVFTREG }, MURES + MUOP11, VUOP11 (0x2fc) },
|
||||
{ "subai", { UDOTDEST, SP, UACCDEST, UVFSREG, 'i' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x27e) },
|
||||
{ "subaq", { UDOTDEST, SP, UACCDEST, UVFSREG, 'q' }, MURES + VUFT (~0) + MUOP11, VUOP11 (0x27c) },
|
||||
{ "suba", { UBC, UDOTDEST, SP, UACCDEST, UVFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x1f) }
|
||||
{ "mini", { DOTDEST, SP, VFDREG, VFSREG, VFTREG }, MURES + MUOP6, VUOP6 (0x2f) },
|
||||
{ "mini", { DOTDEST, SP, VFDREG, VFSREG, 'i' }, MURES + MT + MUOP6, VUOP6 (0x1f) },
|
||||
{ "mini", { UBC, DOTDEST, SP, VFDREG, VFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x5) },
|
||||
{ "msub", { DOTDEST, SP, VFDREG, VFSREG, VFTREG }, MURES + MUOP6, VUOP6 (0x2d) },
|
||||
{ "msubi", { DOTDEST, SP, VFDREG, VFSREG, 'i' }, MURES + MT + MUOP6, VUOP6 (0x27) },
|
||||
{ "msubq", { DOTDEST, SP, VFDREG, VFSREG, 'q' }, MURES + MT + MUOP6, VUOP6 (0x25) },
|
||||
{ "msub", { UBC, DOTDEST, SP, VFDREG, VFSREG, UBCFTREG }, MURES + MUOP4, VUOP4 (0x3) },
|
||||
{ "msuba", { DOTDEST, SP, UACCDEST, VFSREG, VFTREG }, MURES + MUOP11, VUOP11 (0x2fd) },
|
||||
{ "msubai", { DOTDEST, SP, UACCDEST, VFSREG, 'i' }, MURES + MT + MUOP11, VUOP11 (0x27f) },
|
||||
{ "msubaq", { DOTDEST, SP, UACCDEST, VFSREG, 'q' }, MURES + MT + MUOP11, VUOP11 (0x27d) },
|
||||
{ "msuba", { UBC, DOTDEST, SP, UACCDEST, VFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x3f) },
|
||||
{ "mul", { DOTDEST, SP, VFDREG, VFSREG, VFTREG }, MURES + MUOP6, VUOP6 (0x2a) },
|
||||
{ "muli", { DOTDEST, SP, VFDREG, VFSREG, 'i' }, MURES + MT + MUOP6, VUOP6 (0x1e) },
|
||||
{ "mulq", { DOTDEST, SP, VFDREG, VFSREG, 'q' }, MURES + MT + MUOP6, VUOP6 (0x1c) },
|
||||
{ "mul", { UBC, DOTDEST, SP, VFDREG, VFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (6) },
|
||||
{ "mula", { DOTDEST, SP, UACCDEST, VFSREG, VFTREG }, MURES + MUOP11, VUOP11 (0x2be) },
|
||||
{ "mulai", { DOTDEST, SP, UACCDEST, VFSREG, 'i' }, MURES + MT + MUOP11, VUOP11 (0x1fe) },
|
||||
{ "mulaq", { DOTDEST, SP, UACCDEST, VFSREG, 'q' }, MURES + MT + MUOP11, VUOP11 (0x1fc) },
|
||||
{ "mula", { UBC, DOTDEST, SP, UACCDEST, VFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x6f) },
|
||||
{ "nop", { 0 }, MURES + MDEST + MT + MS + MUOP11, VUOP11 (0x2ff) },
|
||||
{ "opmula", { DOTDEST, SP, UACCDEST, VFSREG, VFTREG, UXYZ }, MURES + MUOP11, VUOP11 (0x2fe) },
|
||||
{ "opmsub", { DOTDEST, SP, VFDREG, VFSREG, VFTREG, UXYZ }, MURES + MUOP6, VUOP6 (0x2e) },
|
||||
{ "sub", { DOTDEST, SP, VFDREG, VFSREG, VFTREG }, MURES + MUOP6, VUOP6 (0x2c) },
|
||||
{ "subi", { DOTDEST, SP, VFDREG, VFSREG, 'i' }, MURES + MT + MUOP6, VUOP6 (0x26) },
|
||||
{ "subq", { DOTDEST, SP, VFDREG, VFSREG, 'q' }, MURES + MT + MUOP6, VUOP6 (0x24) },
|
||||
{ "sub", { UBC, DOTDEST, SP, VFDREG, VFSREG, UBCFTREG }, MURES + VUOP4 (~0), VUOP4 (1) },
|
||||
{ "suba", { DOTDEST, SP, UACCDEST, VFSREG, VFTREG }, MURES + MUOP11, VUOP11 (0x2fc) },
|
||||
{ "subai", { DOTDEST, SP, UACCDEST, VFSREG, 'i' }, MURES + MT + MUOP11, VUOP11 (0x27e) },
|
||||
{ "subaq", { DOTDEST, SP, UACCDEST, VFSREG, 'q' }, MURES + MT + MUOP11, VUOP11 (0x27c) },
|
||||
{ "suba", { UBC, DOTDEST, SP, UACCDEST, VFSREG, UBCFTREG }, MURES + MUOP9, VUOP9 (0x1f) }
|
||||
};
|
||||
const int txvu_upper_opcodes_count = sizeof (txvu_upper_opcodes) / sizeof (txvu_opcodes[0]);
|
||||
|
||||
/* Lower instruction Value macros. */
|
||||
|
||||
/* 6 bit opcode. */
|
||||
#define VLOP6(x) R ((x), 6, 0)
|
||||
/* 7 bit opcode. */
|
||||
#define VLOP7(x) R ((x), 7, 25)
|
||||
/* 11 bit opcode. */
|
||||
#define VLOP11(x) R ((x), 11, 0)
|
||||
/* 11 bit immediate. */
|
||||
#define VLIMM11(x) R ((x), 11, 0)
|
||||
/* FTF field. */
|
||||
#define VLFTF(x) R ((x), 2, 23)
|
||||
/* FSF field. */
|
||||
#define VLFSF(x) R ((x), 2, 21)
|
||||
|
||||
/* Lower instruction field masks. */
|
||||
#define MLOP6 VLOP6 (~0)
|
||||
#define MLOP7 VLOP7 (~0)
|
||||
#define MLOP11 VLOP11 (~0)
|
||||
#define MLIMM11 VLIMM11 (~0)
|
||||
#define MLB24 R (1, 1, 24)
|
||||
/* 12 bit immediates are split into two parts, 1 bit and 11 bits.
|
||||
The upper 1 bit is part of the `dest' field. This mask is for the
|
||||
other 3 bits of the dest field. */
|
||||
#define MLIMM12TOP R (7, 3, 22)
|
||||
|
||||
struct txvu_opcode txvu_lower_opcodes[] = {
|
||||
|
||||
@@ -356,39 +391,82 @@ struct txvu_opcode txvu_lower_opcodes[] = {
|
||||
/* ??? Any aliases? */
|
||||
|
||||
/* The rest of these needn't be sorted, but it helps to find them if they are. */
|
||||
{ "b", { SP, LIMM11 }, MLOP7 + MLDEST + MLIT + MLIS, VLOP7 (0x20) },
|
||||
{ "bal", { SP, LITREG, LIMM11 }, MLOP7 + MLDEST + MLIS, VLOP7 (0x21) },
|
||||
{ "div", { 'q', LFSFFSREG, LFTFFTREG }, MLOP7 + MLOP11, VLOP7 (0x40) + VLOP11 (0x3bc) },
|
||||
{ "eatan", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fd) },
|
||||
{ "eatanxy", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x77c) },
|
||||
{ "eatanxz", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x77d) },
|
||||
{ "eexp", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fe) },
|
||||
{ "eleng", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x74e) },
|
||||
{ "ercpr", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7be) },
|
||||
{ "erleng", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x73f) },
|
||||
{ "ersadd", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x73d) },
|
||||
{ "ersqrt", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7bd) },
|
||||
{ "esadd", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x73c) },
|
||||
{ "esin", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fc) },
|
||||
{ "esqrt", { 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLOP11 (0x7bc) },
|
||||
{ "esum", { 'p', LFSREG }, MLOP7 + MLDEST + VLFT (~0) + MLOP11, VLOP7 (0x40) + VLDEST (0xf) + VLOP11 (0x77e) },
|
||||
{ "fcand", { LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x12) },
|
||||
{ "fceq", { LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x10) },
|
||||
{ "fcget", { LITREG }, MLOP7 + MLDEST + MLIS + MLIMM11, VLOP7 (0x1c) },
|
||||
{ "fcor", { LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x13) },
|
||||
{ "fcset", { LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x11) },
|
||||
{ "fmand", { LITREG, LISREG }, MLOP7 + MLDEST + MLIMM11, VLOP7 (0x1a) },
|
||||
{ "fmeq", { LITREG, LISREG }, MLOP7 + MLDEST + MLIMM11, VLOP7 (0x18) },
|
||||
{ "fmor", { LITREG, LISREG }, MLOP7 + MLDEST + MLIMM11, VLOP7 (0x1b) },
|
||||
{ "fsand", { LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MLIS, VLOP7 (0x16) },
|
||||
{ "fseq", { LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MLIS, VLOP7 (0x14) },
|
||||
{ "fsor", { LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MLIS, VLOP7 (0x17) },
|
||||
{ "fsset", { LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MLIS, VLOP7 (0x15) },
|
||||
{ "waitp", { 0 }, 0xffffffff, 0x800007bf },
|
||||
{ "waitq", { 0 }, 0xffffffff, 0x800003bf },
|
||||
{ "b", { SP, LPCREL11 }, MLOP7 + MDEST + MT + MS, VLOP7 (0x20) },
|
||||
{ "bal", { SP, LITREG, LPCREL11 }, MLOP7 + MDEST + MS, VLOP7 (0x21) },
|
||||
{ "div", { SP, 'q', LFSFFSREG, LFTFFTREG }, MLOP7 + MLOP11, VLOP7 (0x40) + VLOP11 (0x3bc) },
|
||||
{ "eatan", { SP, 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + MT + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fd) },
|
||||
{ "eatanxy", { SP, 'p', LFSREG }, MLOP7 + MDEST + MT + MLOP11, VLOP7 (0x40) + VDEST (0xf) + VLOP11 (0x77c) },
|
||||
{ "eatanxz", { SP, 'p', LFSREG }, MLOP7 + MDEST + MT + MLOP11, VLOP7 (0x40) + VDEST (0xf) + VLOP11 (0x77d) },
|
||||
{ "eexp", { SP, 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + MT + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fe) },
|
||||
{ "eleng", { SP, 'p', LFSREG }, MLOP7 + MDEST + MT + MLOP11, VLOP7 (0x40) + VDEST (0xf) + VLOP11 (0x74e) },
|
||||
{ "ercpr", { SP, 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + MT + MLOP11, VLOP7 (0x40) + VLOP11 (0x7be) },
|
||||
{ "erleng", { SP, 'p', LFSREG }, MLOP7 + MDEST + MT + MLOP11, VLOP7 (0x40) + VDEST (0xf) + VLOP11 (0x73f) },
|
||||
{ "ersadd", { SP, 'p', LFSREG }, MLOP7 + MDEST + MT + MLOP11, VLOP7 (0x40) + VDEST (0xf) + VLOP11 (0x73d) },
|
||||
{ "ersqrt", { SP, 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + MT + MLOP11, VLOP7 (0x40) + VLOP11 (0x7bd) },
|
||||
{ "esadd", { SP, 'p', LFSREG }, MLOP7 + MDEST + MT + MLOP11, VLOP7 (0x40) + VDEST (0xf) + VLOP11 (0x73c) },
|
||||
{ "esin", { SP, 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + MT + MLOP11, VLOP7 (0x40) + VLOP11 (0x7fc) },
|
||||
{ "esqrt", { SP, 'p', LFSFFSREG }, MLOP7 + VLFTF (~0) + MT + MLOP11, VLOP7 (0x40) + VLOP11 (0x7bc) },
|
||||
{ "esum", { SP, 'p', LFSREG }, MLOP7 + MDEST + MT + MLOP11, VLOP7 (0x40) + VDEST (0xf) + VLOP11 (0x77e) },
|
||||
{ "fcand", { SP, LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x12) },
|
||||
{ "fceq", { SP, LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x10) },
|
||||
{ "fcget", { SP, LITREG }, MLOP7 + MDEST + MS + MLIMM11, VLOP7 (0x1c) },
|
||||
{ "fcor", { SP, LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x13) },
|
||||
{ "fcset", { SP, LVI01, LIMM24 }, MLOP7 + MLB24, VLOP7 (0x11) },
|
||||
{ "fmand", { SP, LITREG, LISREG }, MLOP7 + MDEST + MLIMM11, VLOP7 (0x1a) },
|
||||
{ "fmeq", { SP, LITREG, LISREG }, MLOP7 + MDEST + MLIMM11, VLOP7 (0x18) },
|
||||
{ "fmor", { SP, LITREG, LISREG }, MLOP7 + MDEST + MLIMM11, VLOP7 (0x1b) },
|
||||
{ "fsand", { SP, LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MS, VLOP7 (0x16) },
|
||||
{ "fseq", { SP, LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MS, VLOP7 (0x14) },
|
||||
{ "fsor", { SP, LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MS, VLOP7 (0x17) },
|
||||
{ "fsset", { SP, LITREG, LIMM12 }, MLOP7 + MLIMM12TOP + MS, VLOP7 (0x15) },
|
||||
{ "iadd", { SP, LIDREG, LISREG, LITREG }, MLOP7 + MDEST + MLOP6, VLOP7 (0x40) + VLOP6 (0x30) },
|
||||
{ "iaddi", { SP, LITREG, LISREG, LIMM5 }, MLOP7 + MDEST + MLOP6, VLOP7 (0x40) + VLOP6 (0x32) },
|
||||
{ "iaddiu", { SP, LITREG, LISREG, LUIMM15 }, MLOP7, VLOP7 (0x08) },
|
||||
{ "iand", { SP, LIDREG, LISREG, LITREG }, MLOP7 + MDEST + MLOP6, VLOP7 (0x40) + VLOP6 (0x34) },
|
||||
{ "ibeq", { SP, LITREG, LISREG, LPCREL11 }, MLOP7 + MDEST, VLOP7 (0x28) },
|
||||
{ "ibgez", { SP, LISREG, LPCREL11 }, MLOP7 + MDEST + MT, VLOP7 (0x2f) },
|
||||
{ "iblez", { SP, LISREG, LPCREL11 }, MLOP7 + MDEST + MT, VLOP7 (0x2e) },
|
||||
{ "ibltz", { SP, LISREG, LPCREL11 }, MLOP7 + MDEST + MT, VLOP7 (0x2c) },
|
||||
{ "ibne", { SP, LITREG, LISREG, LPCREL11 }, MLOP7 + MDEST, VLOP7 (0x29) },
|
||||
/* FIXME: Need to not require commas around parens. */
|
||||
{ "ilw", { LDOTSDEST, SP, LITREG, LIMM11, '(', LISREG, ')' }, MLOP7, VLOP7 (0x04) },
|
||||
{ "ilwr", { LDOTSDEST, SP, LITREG, '(', LISREG, ')' }, MLOP7, VLOP7 (0x40) + VLIMM11 (0x3fe) },
|
||||
{ "ior", { SP, LIDREG, LISREG, LITREG }, MLOP7 + MDEST + MLOP6, VLOP7 (0x40) + VLOP6 (0x34) },
|
||||
{ "isub", { SP, LIDREG, LISREG, LITREG }, MLOP7 + MDEST + MLOP6, VLOP7 (0x40) + VLOP6 (0x31) },
|
||||
{ "isubiu", { SP, LITREG, LISREG, LUIMM15 }, MLOP7, VLOP7 (0x09) },
|
||||
{ "isw", { LDOTSDEST, SP, LITREG, LIMM11, '(', LISREG, ')' }, MLOP7, VLOP7 (0x05) },
|
||||
{ "iswr", { LDOTSDEST, SP, LITREG, '(', LISREG, ')' }, MLOP7, VLOP7 (0x40) + VLIMM11 (0x3ff) },
|
||||
{ "jalr", { SP, LITREG, LISREG }, MLOP7 + MDEST + MLIMM11, VLOP7 (0x25) },
|
||||
{ "jr", { SP, LISREG }, MLOP7 + MDEST + MT + MLIMM11, VLOP7 (0x24) },
|
||||
{ "lq", { DOTDEST, SP, VFTREG, LIMM11, '(', LISREG, ')' }, MLOP7, VLOP7 (0x00) },
|
||||
/* FIXME: No commas around -/+. */
|
||||
{ "lqd", { DOTDEST, SP, VFTREG, LIMM11, '(', '-', '-', LISREG, ')' }, MLOP7, VLOP7 (0x40) + VLIMM11 (0x37e) },
|
||||
{ "lqi", { DOTDEST, SP, VFTREG, LIMM11, '(', LISREG, '+', '+', ')' }, MLOP7, VLOP7 (0x40) + VLIMM11 (0x37c) },
|
||||
/* Only a single VF reg is allowed here. We can use VFTREG because LDOTSDEST
|
||||
handles verifying only a single choice of xyzw is present. */
|
||||
{ "mfir", { LDOTSDEST, SP, VFTREG, LISREG }, MLOP7 + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x3fc) },
|
||||
{ "mfp", { DOTDEST, SP, VFTREG, 'p' }, MLOP7 + MS + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x67c) },
|
||||
{ "move", { DOTDEST, SP, VFTREG, VFSREG }, MLOP7 + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x33c) },
|
||||
{ "mr32", { DOTDEST, SP, VFTREG, VFSREG }, MLOP7 + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x33d) },
|
||||
{ "mtir", { LDOTSDEST, SP, LITREG, LFSREG }, MLOP7 + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x3fd) },
|
||||
{ "rget", { DOTDEST, SP, VFTREG, 'r' }, MLOP7 + MS + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x43d) },
|
||||
{ "rinit", { SP, 'r', LFSFFSREG }, MLOP7 + VLFTF (~0) + MT + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x43e) },
|
||||
{ "rnext", { DOTDEST, SP, VFTREG, 'r' }, MLOP7 + MS + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x43c) },
|
||||
{ "rsqrt", { SP, 'q', LFSFFSREG, LFTFFTREG }, MLOP7 + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x3be) },
|
||||
{ "rxor", { 'r', LFSFFSREG }, MLOP7 + VLFTF (~0) + MT + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x43f) },
|
||||
{ "sq", { DOTDEST, SP, VFTREG, LIMM11, '(', LISREG, ')' }, MLOP7, VLOP7 (0x01) },
|
||||
/* FIXME: No commas around -/+. */
|
||||
{ "sqd", { DOTDEST, SP, VFTREG, LIMM11, '(', '-', '-', LISREG, ')' }, MLOP7, VLOP7 (0x40) + VLIMM11 (0x37f) },
|
||||
{ "sqi", { DOTDEST, SP, VFTREG, LIMM11, '(', LISREG, '+', '+', ')' }, MLOP7, VLOP7 (0x40) + VLIMM11 (0x37d) },
|
||||
{ "sqrt", { SP, 'q', LFTFFTREG }, MLOP7 + VLFSF (~0) + MS + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x3bd) },
|
||||
{ "waitp", { 0 }, 0xffffffff, VLOP7 (0x40) + VLIMM11 (0x7bf) },
|
||||
{ "waitq", { 0 }, 0xffffffff, VLOP7 (0x40) + VLIMM11 (0x3bf) },
|
||||
{ "xgkick", { LISREG }, MLOP7 + MDEST + MT + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x6fc) },
|
||||
{ "xitop", { LITREG }, MLOP7 + MDEST + MS + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x6bd) },
|
||||
{ "xtop", { LITREG }, MLOP7 + MDEST + MS + MLIMM11, VLOP7 (0x40) + VLIMM11 (0x6bc) }
|
||||
};
|
||||
const int txvu_lower_opcodes_count = sizeof (txvu_lower_opcodes) / sizeof (txvu_opcodes[0]);
|
||||
|
||||
|
||||
/* Indexed by first letter of opcode. Points to chain of opcodes with same
|
||||
first letter. */
|
||||
/* ??? One can certainly use a better hash. Later. */
|
||||
@@ -522,7 +600,7 @@ txvu_opcode_init_print ()
|
||||
bc = -1;
|
||||
}
|
||||
|
||||
/* Destination choice support.
|
||||
/* Multiple destination choice support.
|
||||
The "dest" string selects any combination of x,y,z,w.
|
||||
[The letters are ordered that way to follow the manual's style.] */
|
||||
|
||||
@@ -577,6 +655,34 @@ parse_dotdest (pstr, errmsg)
|
||||
return dest;
|
||||
}
|
||||
|
||||
/* Parse a `dest' spec where only a single letter is allowed. */
|
||||
|
||||
static long
|
||||
parse_dotsdest (pstr, errmsg)
|
||||
char **pstr;
|
||||
const char **errmsg;
|
||||
{
|
||||
long dest;
|
||||
|
||||
if (**pstr != '.')
|
||||
{
|
||||
*errmsg = "missing `.'";
|
||||
return 0;
|
||||
}
|
||||
|
||||
++*pstr;
|
||||
switch (**pstr)
|
||||
{
|
||||
case 'x' : case 'X' : dest = TXVU_BC_X; break;
|
||||
case 'y' : case 'Y' : dest = TXVU_BC_Y; break;
|
||||
case 'z' : case 'Z' : dest = TXVU_BC_Z; break;
|
||||
case 'w' : case 'W' : dest = TXVU_BC_W; break;
|
||||
default : *errmsg = "invalid `dest'"; return 0;
|
||||
}
|
||||
*errmsg = NULL;
|
||||
return dest;
|
||||
}
|
||||
|
||||
static TXVU_INSN
|
||||
insert_dotdest (insn, operand, mods, value, errmsg)
|
||||
TXVU_INSN insn;
|
||||
@@ -1063,3 +1169,24 @@ extract_limm12 (insn, operand, mods, pinvalid)
|
||||
int *pinvalid;
|
||||
{
|
||||
}
|
||||
|
||||
/* Lower instruction 15 bit unsigned immediate. */
|
||||
|
||||
static TXVU_INSN
|
||||
insert_luimm15 (insn, operand, mods, value, errmsg)
|
||||
TXVU_INSN insn;
|
||||
const struct txvu_operand *operand;
|
||||
int mods;
|
||||
long value;
|
||||
const char **errmsg;
|
||||
{
|
||||
}
|
||||
|
||||
static long
|
||||
extract_luimm15 (insn, operand, mods, pinvalid)
|
||||
TXVU_INSN insn;
|
||||
const struct txvu_operand *operand;
|
||||
int mods;
|
||||
int *pinvalid;
|
||||
{
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user