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RISC-V: Add FP register core file support.

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This adds fp reg support similar to the existing general reg support.

This fixes one gdb testsuite failure
FAIL: gdb.base/gcore.exp: corefile restored system registers
which fails without the patch because fcsr was missing.  Otherwise, no
regressions with riscv64-linux native testsuite run.

	gdb/
	* riscv-linux-tdep.c (riscv_linux_fregmap): New.
	(riscv_linux_fregset): New.
	(riscv_linux_iterate_over_regset_sections): Call cb for .reg2 section.
This commit is contained in:
Jim Wilson
2019-02-04 17:31:10 -08:00
parent 21820ebe58
commit 617126bc8a
2 changed files with 27 additions and 2 deletions
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6
gdb/ChangeLog
View File

@@ -1,3 +1,9 @@
2019-02-08 Jim Wilson <jimw@sifive.com>
* riscv-linux-tdep.c (riscv_linux_fregmap): New.
(riscv_linux_fregset): New.
(riscv_linux_iterate_over_regset_sections): Call cb for .reg2 section.
2019-02-07 Tom Tromey <tom@tromey.com>
* thread.c (thread_cancel_execution_command): Update.

23
gdb/riscv-linux-tdep.c
View File

@@ -37,6 +37,16 @@ static const struct regcache_map_entry riscv_linux_gregmap[] =
{ 0 }
};
/* Define the FP register mapping. The kernel puts the 32 FP regs first, and
then FCSR. */
static const struct regcache_map_entry riscv_linux_fregmap[] =
{
{ 32, RISCV_FIRST_FP_REGNUM, 0 },
{ 1, RISCV_CSR_FCSR_REGNUM, 0 },
{ 0 }
};
/* Define the general register regset. */
static const struct regset riscv_linux_gregset =
@@ -44,6 +54,13 @@ static const struct regset riscv_linux_gregset =
riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset
};
/* Define the FP register regset. */
static const struct regset riscv_linux_fregset =
{
riscv_linux_fregmap, regcache_supply_regset, regcache_collect_regset
};
/* Define hook for core file support. */
static void
@@ -54,8 +71,10 @@ riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
{
cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)),
&riscv_linux_gregset, NULL, cb_data);
/* TODO: Add FP register support. */
/* The kernel is adding 8 bytes for FCSR. */
cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8,
(32 * riscv_isa_flen (gdbarch)) + 8,
&riscv_linux_fregset, NULL, cb_data);
}
/* Signal trampoline support. */