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sim: bfin: handle saturation with RND12 sub insns

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The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved.  So add handling for this edge
case to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
2011-03-27 04:03:05 +00:00
parent f65d3d6b99
commit 36aef94270
2 changed files with 11 additions and 1 deletions
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5
sim/bfin/ChangeLog
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@@ -1,3 +1,8 @@
2011-03-26 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Set result to 0x7FFFFFFF when
the result was 0x80000000 for RND12 subtraction.
2011-03-26 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Set VS when V is set.

7
sim/bfin/bfin-sim.c
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@@ -4009,7 +4009,12 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
/* If subtract, just invert and add one. */
if (aop & 0x1)
val1 = ~val1 + 1;
{
if (val1 == 0x80000000)
val1 = 0x7FFFFFFF;
else
val1 = ~val1 + 1;
}
/* Get the sign bits, since we need them later. */
sBit1 = !!(val0 & 0x80000000);