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LoongArch: Corrected to GNU style code

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This commit is contained in:
Lulu Cai
2024-10-25 20:52:18 +08:00
committed by liuzhensong
parent 5168ed9912
commit 287938873c
2 changed files with 25 additions and 25 deletions
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30
bfd/elfnn-loongarch.c
View File

@@ -4909,7 +4909,7 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec,
/* Change rj to $tp. */
insn_rj = 0x2 << 5;
/* Get rd register. */
insn_rd = LARCH_GET_RD(insn);
insn_rd = LARCH_GET_RD (insn);
/* Write symbol offset. */
symval <<= 10;
/* Writes the modified instruction. */
@@ -4928,7 +4928,7 @@ loongarch_relax_tls_le (bfd *abfd, asection *sec,
break;
case R_LARCH_TLS_LE_LO12:
bfd_put (32, abfd, LARCH_OP_ORI | LARCH_GET_RD(insn),
bfd_put (32, abfd, LARCH_OP_ORI | LARCH_GET_RD (insn),
contents + rel->r_offset);
break;
@@ -4974,7 +4974,7 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec,
Elf_Internal_Rela *rel_lo = rel_hi + 2;
uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset);
uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset);
uint32_t rd = LARCH_GET_RD(pca);
uint32_t rd = LARCH_GET_RD (pca);
/* This section's output_offset need to subtract the bytes of instructions
relaxed by the previous sections, so it needs to be updated beforehand.
@@ -4999,10 +4999,10 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec,
/* Is pcalau12i + addi.d insns? */
if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_PCALA_LO12)
|| !LARCH_INSN_ADDI_D(add)
|| !LARCH_INSN_ADDI_D (add)
/* Is pcalau12i $rd + addi.d $rd,$rd? */
|| (LARCH_GET_RD(add) != rd)
|| (LARCH_GET_RJ(add) != rd)
|| (LARCH_GET_RD (add) != rd)
|| (LARCH_GET_RJ (add) != rd)
/* Can be relaxed to pcaddi? */
|| (symval & 0x3) /* 4 bytes align. */
|| ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xffe00000)
@@ -5035,7 +5035,7 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec,
{
bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
uint32_t jirl = bfd_get (32, abfd, contents + rel->r_offset + 4);
uint32_t rd = LARCH_GET_RD(jirl);
uint32_t rd = LARCH_GET_RD (jirl);
/* This section's output_offset need to subtract the bytes of instructions
relaxed by the previous sections, so it needs to be updated beforehand.
@@ -5094,13 +5094,13 @@ loongarch_relax_pcala_ld (bfd *abfd, asection *sec,
Elf_Internal_Rela *rel_lo = rel_hi + 2;
uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset);
uint32_t ld = bfd_get (32, abfd, contents + rel_lo->r_offset);
uint32_t rd = LARCH_GET_RD(pca);
uint32_t rd = LARCH_GET_RD (pca);
uint32_t addi_d = LARCH_OP_ADDI_D;
if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12)
|| (LARCH_GET_RD(ld) != rd)
|| (LARCH_GET_RJ(ld) != rd)
|| !LARCH_INSN_LD_D(ld))
|| (LARCH_GET_RD (ld) != rd)
|| (LARCH_GET_RJ (ld) != rd)
|| !LARCH_INSN_LD_D (ld))
return false;
addi_d = addi_d | (rd << 5) | rd;
@@ -5194,7 +5194,7 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec,
Elf_Internal_Rela *rel_lo = rel_hi + 2;
uint32_t pca = bfd_get (32, abfd, contents + rel_hi->r_offset);
uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset);
uint32_t rd = LARCH_GET_RD(pca);
uint32_t rd = LARCH_GET_RD (pca);
/* This section's output_offset need to subtract the bytes of instructions
relaxed by the previous sections, so it needs to be updated beforehand.
@@ -5220,10 +5220,10 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec,
/* Is pcalau12i + addi.d insns? */
if ((ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_GOT_PC_LO12
&& ELFNN_R_TYPE (rel_lo->r_info) != R_LARCH_TLS_DESC_PC_LO12)
|| !LARCH_INSN_ADDI_D(add)
|| !LARCH_INSN_ADDI_D (add)
/* Is pcalau12i $rd + addi.d $rd,$rd? */
|| (LARCH_GET_RD(add) != rd)
|| (LARCH_GET_RJ(add) != rd)
|| (LARCH_GET_RD (add) != rd)
|| (LARCH_GET_RJ (add) != rd)
/* Can be relaxed to pcaddi? */
|| (symval & 0x3) /* 4 bytes align. */
|| ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xffe00000)

20
gas/config/tc-loongarch.c
View File

@@ -1080,7 +1080,7 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip)
}
/* check all atomic memory insns */
else if (ip->insn->mask == LARCH_MK_ATOMIC_MEM
&& LARCH_INSN_ATOMIC_MEM(ip->insn_bin))
&& LARCH_INSN_ATOMIC_MEM (ip->insn_bin))
{
/* For AMO insn amswap.[wd], amadd.[wd], etc. */
if (ip->args[0] != 0
@@ -1090,22 +1090,22 @@ check_this_insn_before_appending (struct loongarch_cl_insn *ip)
}
else if ((ip->insn->mask == LARCH_MK_BSTRINS_W
/* bstr(ins|pick).w rd, rj, msbw, lsbw */
&& (LARCH_INSN_BSTRINS_W(ip->insn_bin)
|| LARCH_INSN_BSTRPICK_W(ip->insn_bin)))
&& (LARCH_INSN_BSTRINS_W (ip->insn_bin)
|| LARCH_INSN_BSTRPICK_W (ip->insn_bin)))
|| (ip->insn->mask == LARCH_MK_BSTRINS_D
/* bstr(ins|pick).d rd, rj, msbd, lsbd */
&& (LARCH_INSN_BSTRINS_D(ip->insn_bin)
|| LARCH_INSN_BSTRPICK_D(ip->insn_bin))))
&& (LARCH_INSN_BSTRINS_D (ip->insn_bin)
|| LARCH_INSN_BSTRPICK_D (ip->insn_bin))))
{
/* For bstr(ins|pick).[wd]. */
if (ip->args[2] < ip->args[3])
as_bad (_("bstr(ins|pick).[wd] require msbd >= lsbd"));
}
else if (ip->insn->mask != 0
&& (LARCH_INSN_CSRXCHG(ip->insn_bin)
|| LARCH_INSN_GCSRXCHG(ip->insn_bin))
&& (LARCH_GET_RJ(ip->insn_bin) == 0
|| LARCH_GET_RJ(ip->insn_bin) == 1)
&& (LARCH_INSN_CSRXCHG (ip->insn_bin)
|| LARCH_INSN_GCSRXCHG (ip->insn_bin))
&& (LARCH_GET_RJ (ip->insn_bin) == 0
|| LARCH_GET_RJ (ip->insn_bin) == 1)
/* csrxchg rd, rj, csr_num */
&& (strcmp ("csrxchg", ip->name) == 0
|| strcmp ("gcsrxchg", ip->name) == 0))
@@ -2231,7 +2231,7 @@ loongarch_convert_frag_branch (fragS *fragp)
case RELAX_BRANCH_26:
insn = bfd_getl32 (buf);
/* Invert the branch condition. */
if (LARCH_INSN_FLOAT_BRANCH(insn))
if (LARCH_INSN_FLOAT_BRANCH (insn))
insn ^= LARCH_FLOAT_BRANCH_INVERT_BIT;
else
insn ^= LARCH_BRANCH_INVERT_BIT;