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MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1

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Fix an issue caused by commit f9419b056f ("MIPS gas: code cleanup"),
<https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace
the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR.
While the register referred by its number is $31 in both cases, these
instructions operate on the floating-point control register file rather
than general-purpose registers.

	gas/
	* config/tc-mips.c (FCSR): New macro.
	(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
This commit is contained in:
Maciej W. Rozycki
2021-05-29 03:26:32 +02:00
parent c445a93910
commit 25663db430
2 changed files with 11 additions and 4 deletions
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5
gas/ChangeLog
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@@ -1,3 +1,8 @@
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* config/tc-mips.c (FCSR): New macro.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
2021-05-28 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27905

10
gas/config/tc-mips.c
View File

@@ -104,6 +104,8 @@ static char *mips_flags_frag;
#define FP 30
#define RA 31
#define FCSR 31
#define ILLEGAL_REG (32)
#define AT mips_opts.at
@@ -13835,18 +13837,18 @@ macro (struct mips_cl_insn *ip, char *str)
* or is there a reason for it?
*/
start_noreorder ();
macro_build (NULL, "cfc1", "t,G", op[2], RA);
macro_build (NULL, "cfc1", "t,G", op[2], RA);
macro_build (NULL, "cfc1", "t,G", op[2], FCSR);
macro_build (NULL, "cfc1", "t,G", op[2], FCSR);
macro_build (NULL, "nop", "");
expr1.X_add_number = 3;
macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16);
expr1.X_add_number = 2;
macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
macro_build (NULL, "ctc1", "t,G", AT, RA);
macro_build (NULL, "ctc1", "t,G", AT, FCSR);
macro_build (NULL, "nop", "");
macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
op[0], op[1]);
macro_build (NULL, "ctc1", "t,G", op[2], RA);
macro_build (NULL, "ctc1", "t,G", op[2], FCSR);
macro_build (NULL, "nop", "");
end_noreorder ();
break;