aarch64: Add support for the id_aa64isar3_el1 system register

Hi,

[PATCH][Binutils] aarch64: Add support for the id_aa64isar3_el1 system register

AArch64 defines a read-only system register called id_aa64isar3_el1.
This patch also adds relevant tests.

Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets
and no regressions was found.

Is this Ok for trunk? I do not have commit rights, if OK, can someone commit on my behalf?

Thanks,
Yury Khrustalev

From e42c835e8f2ee81150f498675f2faf108bbe79f8 Mon Sep 17 00:00:00 2001
From: Yury Khrustalev <yury.khrustalev@arm.com>
Date: Tue, 6 Feb 2024 11:05:39 +0000
Subject: [PATCH] [PATCH][Binutils] aarch64: Add support for the
 id_aa64isar3_el1 system register

AArch64 defines a read-only system register called id_aa64isar3_el1.
This patch also adds relevant tests.

Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets
and no regressions was found.
This commit is contained in:
Yury Khrustalev
2024-02-09 13:52:14 +00:00
committed by Nick Clifton
parent d0446acf3d
commit 1bc24c0dab
6 changed files with 9 additions and 0 deletions

View File

@@ -13,3 +13,4 @@ Disassembly of section \.text:
.*: d5330503 mrs x3, dbgdtrrx_el0
.*: d5180003 msr midr_el1, x3 // note: writing to a read-only register
.*: d5180640 msr id_aa64isar2_el1, x0 // note: writing to a read-only register
.*: d5180660 msr id_aa64isar3_el1, x0 // note: writing to a read-only register

View File

@@ -3,3 +3,4 @@
.*:5: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
.*:6: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
.*:7: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64isar2_el1,x0'
.*:8: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64isar3_el1,x0'

View File

@@ -5,3 +5,4 @@
mrs x3, dbgdtrtx_el0
msr midr_el1, x3
msr id_aa64isar2_el1, x0
msr id_aa64isar3_el1, x0

View File

@@ -31,3 +31,5 @@ Disassembly of section \.text:
5c: d5110300 msr trcstatr, x0
60: d5380640 mrs x0, id_aa64isar2_el1
64: d538065e mrs x30, id_aa64isar2_el1
68: d5380660 mrs x0, id_aa64isar3_el1
6c: d538067e mrs x30, id_aa64isar3_el1

View File

@@ -33,3 +33,6 @@
mrs x0, id_aa64isar2_el1
mrs x30, id_aa64isar2_el1
mrs x0, id_aa64isar3_el1
mrs x30, id_aa64isar3_el1

View File

@@ -521,6 +521,7 @@
SYSREG ("id_aa64isar0_el1", CPENC (3,0,0,6,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64isar1_el1", CPENC (3,0,0,6,1), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64isar2_el1", CPENC (3,0,0,6,2), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64isar3_el1", CPENC (3,0,0,6,3), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64mmfr0_el1", CPENC (3,0,0,7,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64mmfr1_el1", CPENC (3,0,0,7,1), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64mmfr2_el1", CPENC (3,0,0,7,2), F_REG_READ, AARCH64_NO_FEATURES)