forked from Imagelibrary/binutils-gdb
aarch64: Add support for Armv8-R DFB alias
This adds support for the DFB alias introduced in Armv8-R AArch64. gas/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * testsuite/gas/aarch64/dfb.d: New test. * testsuite/gas/aarch64/dfb.s: Input. opcodes/ChangeLog: 2020-09-08 Alex Coplan <alex.coplan@arm.com> * aarch64-tbl.h (aarch64_feature_v8_r): New. (ARMV8_R): New. (V8_R_INSN): New. (aarch64_opcode_table): Add dfb. * aarch64-opc-2.c: Regenerate. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate.
This commit is contained in:
Alex Coplan
@@ -1,3 +1,8 @@
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2020-09-08 Alex Coplan <alex.coplan@arm.com>
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* testsuite/gas/aarch64/dfb.d: New test.
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* testsuite/gas/aarch64/dfb.s: Input.
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2020-09-08 Alex Coplan <alex.coplan@arm.com>
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* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
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8
gas/testsuite/gas/aarch64/dfb.d
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8
gas/testsuite/gas/aarch64/dfb.d
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@@ -0,0 +1,8 @@
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#objdump: -dr -m aarch64:armv8-r
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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.*: d5033c9f dfb
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2
gas/testsuite/gas/aarch64/dfb.s
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2
gas/testsuite/gas/aarch64/dfb.s
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@@ -0,0 +1,2 @@
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.arch armv8-r
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dfb
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@@ -1,3 +1,13 @@
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2020-09-08 Alex Coplan <alex.coplan@arm.com>
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* aarch64-tbl.h (aarch64_feature_v8_r): New.
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(ARMV8_R): New.
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(V8_R_INSN): New.
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(aarch64_opcode_table): Add dfb.
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* aarch64-opc-2.c: Regenerate.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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2020-09-08 Alex Coplan <alex.coplan@arm.com>
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* aarch64-dis.c (arch_variant): New.
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@@ -426,14 +426,14 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1184: /* movz */
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value = 1184; /* --> movz. */
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break;
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case 1238: /* autibsp */
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case 1237: /* autibz */
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case 1236: /* autiasp */
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case 1235: /* autiaz */
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case 1234: /* pacibsp */
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case 1233: /* pacibz */
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case 1232: /* paciasp */
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case 1231: /* paciaz */
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case 1239: /* autibsp */
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case 1238: /* autibz */
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case 1237: /* autiasp */
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case 1236: /* autiaz */
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case 1235: /* pacibsp */
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case 1234: /* pacibz */
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case 1233: /* paciasp */
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case 1232: /* paciaz */
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case 1211: /* tsb */
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case 1210: /* psb */
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case 1209: /* esb */
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@@ -453,140 +453,141 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1194: /* hint */
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value = 1194; /* --> hint. */
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break;
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case 1215: /* pssbb */
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case 1214: /* ssbb */
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case 1216: /* pssbb */
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case 1215: /* ssbb */
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case 1214: /* dfb */
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case 1213: /* dsb */
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value = 1213; /* --> dsb. */
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break;
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case 1226: /* cpp */
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case 1225: /* dvp */
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case 1224: /* cfp */
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case 1223: /* tlbi */
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case 1222: /* ic */
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case 1221: /* dc */
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case 1220: /* at */
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case 1219: /* sys */
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value = 1219; /* --> sys. */
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case 1227: /* cpp */
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case 1226: /* dvp */
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case 1225: /* cfp */
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case 1224: /* tlbi */
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case 1223: /* ic */
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case 1222: /* dc */
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case 1221: /* at */
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case 1220: /* sys */
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value = 1220; /* --> sys. */
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break;
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case 2036: /* bic */
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case 1286: /* and */
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value = 1286; /* --> and. */
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case 2037: /* bic */
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case 1287: /* and */
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value = 1287; /* --> and. */
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break;
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case 1269: /* mov */
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case 1288: /* and */
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value = 1288; /* --> and. */
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case 1270: /* mov */
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case 1289: /* and */
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value = 1289; /* --> and. */
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break;
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case 1273: /* movs */
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case 1289: /* ands */
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value = 1289; /* --> ands. */
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case 1274: /* movs */
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case 1290: /* ands */
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value = 1290; /* --> ands. */
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break;
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case 2037: /* cmple */
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case 1324: /* cmpge */
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value = 1324; /* --> cmpge. */
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case 2038: /* cmple */
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case 1325: /* cmpge */
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value = 1325; /* --> cmpge. */
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break;
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case 2040: /* cmplt */
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case 1327: /* cmpgt */
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value = 1327; /* --> cmpgt. */
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case 2041: /* cmplt */
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case 1328: /* cmpgt */
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value = 1328; /* --> cmpgt. */
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break;
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case 2038: /* cmplo */
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case 1329: /* cmphi */
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value = 1329; /* --> cmphi. */
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case 2039: /* cmplo */
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case 1330: /* cmphi */
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value = 1330; /* --> cmphi. */
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break;
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case 2039: /* cmpls */
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case 1332: /* cmphs */
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value = 1332; /* --> cmphs. */
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case 2040: /* cmpls */
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case 1333: /* cmphs */
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value = 1333; /* --> cmphs. */
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break;
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case 1266: /* mov */
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case 1354: /* cpy */
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value = 1354; /* --> cpy. */
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break;
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case 1268: /* mov */
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case 1267: /* mov */
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case 1355: /* cpy */
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value = 1355; /* --> cpy. */
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break;
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case 2047: /* fmov */
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case 1271: /* mov */
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case 1269: /* mov */
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case 1356: /* cpy */
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value = 1356; /* --> cpy. */
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break;
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case 1261: /* mov */
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case 1368: /* dup */
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value = 1368; /* --> dup. */
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case 2048: /* fmov */
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case 1272: /* mov */
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case 1357: /* cpy */
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value = 1357; /* --> cpy. */
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break;
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case 1263: /* mov */
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case 1260: /* mov */
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case 1262: /* mov */
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case 1369: /* dup */
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value = 1369; /* --> dup. */
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break;
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case 2046: /* fmov */
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case 1265: /* mov */
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case 1264: /* mov */
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case 1261: /* mov */
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case 1370: /* dup */
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value = 1370; /* --> dup. */
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break;
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case 1264: /* mov */
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case 1371: /* dupm */
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value = 1371; /* --> dupm. */
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case 2047: /* fmov */
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case 1266: /* mov */
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case 1371: /* dup */
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value = 1371; /* --> dup. */
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break;
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case 2041: /* eon */
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case 1373: /* eor */
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value = 1373; /* --> eor. */
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case 1265: /* mov */
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case 1372: /* dupm */
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value = 1372; /* --> dupm. */
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break;
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case 1274: /* not */
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case 1375: /* eor */
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value = 1375; /* --> eor. */
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case 2042: /* eon */
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case 1374: /* eor */
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value = 1374; /* --> eor. */
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break;
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case 1275: /* nots */
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case 1376: /* eors */
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value = 1376; /* --> eors. */
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case 1275: /* not */
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case 1376: /* eor */
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value = 1376; /* --> eor. */
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break;
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case 2042: /* facle */
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case 1381: /* facge */
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value = 1381; /* --> facge. */
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case 1276: /* nots */
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case 1377: /* eors */
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value = 1377; /* --> eors. */
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break;
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case 2043: /* faclt */
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case 1382: /* facgt */
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value = 1382; /* --> facgt. */
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case 2043: /* facle */
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case 1382: /* facge */
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value = 1382; /* --> facge. */
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break;
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case 2044: /* fcmle */
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case 1395: /* fcmge */
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value = 1395; /* --> fcmge. */
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case 2044: /* faclt */
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case 1383: /* facgt */
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value = 1383; /* --> facgt. */
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break;
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case 2045: /* fcmlt */
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case 1397: /* fcmgt */
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value = 1397; /* --> fcmgt. */
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case 2045: /* fcmle */
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case 1396: /* fcmge */
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value = 1396; /* --> fcmge. */
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break;
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case 2046: /* fcmlt */
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case 1398: /* fcmgt */
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value = 1398; /* --> fcmgt. */
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break;
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case 1259: /* fmov */
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case 1404: /* fcpy */
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value = 1404; /* --> fcpy. */
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break;
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case 1258: /* fmov */
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case 1403: /* fcpy */
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value = 1403; /* --> fcpy. */
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case 1427: /* fdup */
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value = 1427; /* --> fdup. */
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break;
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case 1257: /* fmov */
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case 1426: /* fdup */
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value = 1426; /* --> fdup. */
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break;
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case 1259: /* mov */
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case 1757: /* orr */
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value = 1757; /* --> orr. */
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break;
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case 2048: /* orn */
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case 1260: /* mov */
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case 1758: /* orr */
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value = 1758; /* --> orr. */
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break;
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case 1262: /* mov */
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case 1760: /* orr */
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value = 1760; /* --> orr. */
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case 2049: /* orn */
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case 1759: /* orr */
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value = 1759; /* --> orr. */
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break;
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case 1272: /* movs */
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case 1761: /* orrs */
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value = 1761; /* --> orrs. */
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case 1263: /* mov */
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case 1761: /* orr */
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value = 1761; /* --> orr. */
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break;
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case 1267: /* mov */
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case 1823: /* sel */
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value = 1823; /* --> sel. */
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case 1273: /* movs */
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case 1762: /* orrs */
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value = 1762; /* --> orrs. */
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break;
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case 1270: /* mov */
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case 1268: /* mov */
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case 1824: /* sel */
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value = 1824; /* --> sel. */
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break;
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case 1271: /* mov */
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case 1825: /* sel */
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value = 1825; /* --> sel. */
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break;
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default: return NULL;
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}
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File diff suppressed because it is too large
Load Diff
@@ -310,17 +310,17 @@ static const unsigned op_enum_table [] =
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391,
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413,
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415,
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1262,
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1267,
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1260,
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1259,
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1263,
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1270,
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1272,
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1268,
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1261,
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1260,
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1264,
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1271,
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1273,
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1269,
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1275,
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1274,
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1270,
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1276,
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1275,
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131,
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};
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@@ -2406,6 +2406,8 @@ static const aarch64_feature_set aarch64_feature_f32mm_sve =
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static const aarch64_feature_set aarch64_feature_f64mm_sve =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F64MM
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| AARCH64_FEATURE_SVE, 0);
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static const aarch64_feature_set aarch64_feature_v8_r =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_R, 0);
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#define CORE &aarch64_feature_v8
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@@ -2450,6 +2452,7 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
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#define F32MM_SVE &aarch64_feature_f32mm_sve
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#define F64MM_SVE &aarch64_feature_f64mm_sve
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#define I8MM &aarch64_feature_i8mm
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#define ARMV8_R &aarch64_feature_v8_r
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#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
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@@ -2553,6 +2556,8 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
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{ NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
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#define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
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{ NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
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#define V8_R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL }
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struct aarch64_opcode aarch64_opcode_table[] =
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{
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@@ -3845,6 +3850,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
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CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
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CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
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V8_R_INSN ("dfb", 0xd5033c9f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
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CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
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CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
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CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0),
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