Commit Graph

4615 Commits

Author SHA1 Message Date
Gerwin Klein
6b204b3fe4 Merge branch 'master' into lsf37/riscv-clock-test 2024-12-20 11:32:19 +11:00
Gerwin Klein
1732c05ef6 github: pin Ubuntu 22.04 for deployment step
Python 3.12 in Ubuntu 24.04 has incompatible packages.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-12-19 17:42:27 +11:00
Michael McInerney
84163bd855 mcs: refactor refill_budget_check
This refactors refill_budget_check and schedule_used to
ease verification by limiting heap access via refill_head
and refill_tail, and providing (inlined) named functions
for both the condition and bodies of the loops.

Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2024-12-19 16:35:54 +11:00
Gerwin Klein
ae077fd738 tqma: remove virtualisation project settings
The settings KernelArmVtimerUpdateVOffset and
KernelArmDisableWFIWFETraps should be project settings, not platform
settings, and the values set here are not required for the platform to
work -- they just provide a different default.

Setting these in platform configs could lead to inconsistent project
builds when switching between platforms.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-12-19 11:48:44 +11:00
Gerwin Klein
7d493561cb github: pin style check to ubuntu-22.04
The default python version changes on ubuntu-24, which breaks the
version of cmake-format we are currently using.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-12-19 11:05:25 +11:00
Gerwin Klein
69aec5c642 hifive: reflect lower TIMER_PRECISION in config
Reflect the slow timer read on this platform by increasing the value
for TIMER_PRECISION.

MCS+SMP+debug tests have been failing the clock sync boot test (see
also issue #1053). The proposed fix, which was to make reading the
timer faster, only works for certain OpenSBI versions and is not
enabled by default.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-12-19 10:43:27 +11:00
Indan Zupancic
b7ce213654 Add i.MX93 SoC support
Signed-off-by: Indan Zupancic <indan@nul.nu>
2024-12-18 16:41:44 +11:00
Indan Zupancic
635d74639e Add fsl,imx7ulp-lpuart alias
Signed-off-by: Indan Zupancic <indan@nul.nu>
2024-12-18 16:41:44 +11:00
Yanfeng Liu
80e60fe397 manual/objects: clean garbage
This drops unnecessary `iz` text at chapter end.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-12-11 13:25:50 +11:00
Yanfeng Liu
5632069576 riscv/vspace.c: revise comments
This revises comments for `map_kernel_window()` to be in line with
the code.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-12-05 09:12:40 +11:00
Yanfeng Liu
b67ff0bcdf riscv/hardware.h: simplify RISCV_GET_PT_INDEX
This simplifies RISCV_GET_PT_INDEX by reusing RISCV_GET_LVL_PGSIZE_BITS.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-12-05 09:12:40 +11:00
Yanfeng Liu
5041edaad5 model/statedata.c: align idle thread block
Current TCB_PTR_CTE_PTR assumes that thread blocks are aligned at
BIT(seL4_TCBBits). However the idle thread blocks are aligned
differently at BIT(TCB_SIZE_BITS), thus TCB_PTR_CTE_PTR cannot be
used for idle threads.

This changes idle thread alignment to be consistent with standard
TCBs. Even though macros like TCB_PTR_CTE_PTR should not be used
for idle thread, verification assumes consistent alignment for all
TCBs.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-12-04 16:11:44 +11:00
Nick Spinale
24156aafc3 remove UNREACHABLE() from resolveAddressBits
The binary verification tools do not support __builtin_unreachable.

Signed-off-by: Nick Spinale <nick@nickspinale.com>
2024-12-04 15:23:38 +11:00
Yanfeng Liu
7c3bc020fa machine/capdl.c: fix memory corruption
This fixes memory corruption in `add_to_seen()` when watermark
equals to array length.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-12-04 10:02:35 +11:00
Nick Spinale
8b298285dc x86: initialize variables
Multiple versions of GCC were unable to determine that these variables
in decodeX86PortInvocation are initialized in all cases.

Oddly, this compilation failure was only observed with -O1. Compilation
with -O2 was not failing.

Signed-off-by: Nick Spinale <nick@nickspinale.com>
2024-12-03 16:22:46 +11:00
Ivan-Velickovic
e45d229601 Fix printing when IRQ is out of range
Signed-off-by: Ivan-Velickovic <i.velickovic@unsw.edu.au>
2024-12-03 08:56:47 +11:00
Yanfeng Liu
58674cdaec arch/riscv64: revise address space comments
This revises comments of virtual space mapping.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-11-27 09:20:25 +11:00
Szymon Duchniewicz
4b233815fd docs: README: Fix url to kernel features
Signed-off-by: Szymon Duchniewicz <s.duchniewicz@unsw.edu.au>
2024-11-22 18:33:13 +00:00
FennelFoxxo
e995b64653 boot: remove unnecessary reserve increment
The increment and reserve here is not an issue, but to keep
consistency with the change made in 291af86 we should remove it.

See PR #1317 for more info

Signed-off-by: James Martin <fennelfoxxo@gmail.com>
2024-11-17 11:00:24 +00:00
FennelFoxxo
4018ad5942 boot: fix init_freemem skipping reserved regions
In cases where the kernel is passed a very fragmented map of
available memory (specifically when booting from GRUB on x86),
it is possible for multiple available regions to overlap with
a single reserved region.

Currently, if there is an overlap
(where avail_reg[a].start >= reserved[r].start), the available
region is trimmed and the region index is incremented. This causes
any other overlapping regions to be handled as if they are
non-overlapping, since it's now looking at the next reserved region.
This eventually leads to reserved memory being passed to the root
task and can cause corruption issues if it is used.

It is fine to skip this index increment, since the available region
is now either empty or non-overlapping, and both cases are already
trivially handled.

Signed-off-by: James Martin <fennelfoxxo@gmail.com>
2024-11-17 11:00:24 +00:00
julia
d6b4e774ca riscv: Fix MAX_IRQ for QEMU platform
A better solution would be to parse the DTS; however QEMU
hasn't changed this in 6 years.

Signed-off-by: julia <git.ts@trainwit.ch>
2024-11-11 12:25:13 +00:00
julia
640643954c riscv: fix off-by-1 write for PLIC IRQ priorities
This produced 'sifive_plic_write: Invalid register write 0x180' in QEMU.
https://github.com/seL4/seL4/issues/1350#issuecomment-2464273308

Signed-off-by: julia <git.ts@trainwit.ch>
2024-11-11 12:25:13 +00:00
Matt Rossouw
65825d4df8 Re-enabled PLIC for Ariane
Signed-off-by: Matt Rossouw <matthew.rossouw@unsw.edu.au>
2024-11-06 10:02:41 +00:00
Yanfeng Liu
9edd2704ea manual: add CapSMC to table 9.1
This adds `seL4_CapSMC` to table 9.1 and updates section 9.1 so
that to be in line with latest upstream code.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-11-03 15:09:59 +00:00
Gerwin Klein
c5b23791ea configs: additional verified platforms
With recent proof improvements the proofs now apply to further platforms
in the ARM and AARCH64 configurations.

Refactor the verified configs to build on one include file per major
architecture which is then used for each platform with potentially
modified settings. Add path argument to `cmake_script_build_kernel`
macro to accommodate inclusion from different locations in the file
system.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-10-25 16:23:44 +11:00
Gerwin Klein
03ad568c89 move cache flush from untyped reset to retype
Do not perform cache flushing in clearMemory. Instead flush the cache
only for those object types where it is necessary, and only when the
object is retyped, not when the untyped cap is reset.

This reduces overall need for flushing and delays it to the point of
use. This should speed up boot time significantly, but may impact WCET,
because the largest flush is now the largest page size (e.g. 24) instead
of CONFIG_RESET_CHUNK_BITS (8). The user could already request a flush
of the largest page size before, though, so it this may not actually
impact WCET. Remains to be investigated.

Why this is safe:

- Flushing is only necessary for objects that are seen by other parts of
  the system, not for kernel-internal object. These objects are
  non-device frames (including IOMMU pages) and page tables. All other
  objects are only read/written by the kernel. Frames need to be flushed
  to RAM (as clearMemory did), because they could be seen uncached by
  devices. Page tables only to PoU for the page table walker.

- Before createNewObject in retype, these objects do not exist and
  cannot be seen by any part of the system. createNewObject is the point
  where new objects can become visible to the user.

- Theoretically, we could defer flushing further to the point where
  frames or page tables are mapped, but it is more complex to track
  whether a flush has already happened when they are mapped multiple
  times, whereas at retype the object cannot have been flushed already.

- The original implementation, before clearing memory was moved into
  reset untyped, also flushed at the same points.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-10-24 15:33:44 +11:00
Michael McInerney
5dd34db629 mcs: refactor cancelAllIPC and cancelBadgedSends
This factors out code from cancelAllIPC and cancelBadgedSends
by introducing the inline function restart_thread_if_no_fault

Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2024-10-21 10:35:59 +11:00
Michael McInerney
7aac8a3053 mcs: use sc_active in commitTime
Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2024-10-17 20:01:08 +11:00
Gerwin Klein
8f88c958fc utils: safer str_to_long
Make str_to_long more defensive against malformed content, since this
function runs on user (cmd line) input on x86. The input is from boot
time, i.e. trusted, but the function should still be memory safe.

This change does not fix overflow issues which may still lead to
undefined behaviour.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-10-15 14:28:59 +11:00
Gerwin Klein
ff3e7ff93e aarch32: remove unused functions
getKernelStack() is never called, and readHTPIDRO() was only called in
getKernelStack(). readTPIDRPRW() is only used in hyp configurations.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-10-14 17:45:42 +11:00
Alwin Joshy
9080b6844b invocations_all.json: define remove_prefix()
We relied on str.removeprefix(), which is only available in
python >= 3.9. To make this script more portable, we add our
own implementation.

Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>
2024-10-07 16:55:54 +11:00
Alwin Joshy
ca0edeaeab invocations_all.json: make paths explicit
Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>
2024-10-07 16:55:54 +11:00
Alwin Joshy
bd1c392409 Export invocation numbers to JSON file
Co-authored-by: Ivan Velickovic <i.velickovic@unsw.edu.au>
Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>

tmp
2024-10-04 09:06:02 +01:00
Ivan Velickovic
85aa104eb4 Fix TCB size on RISC-V 32-bit when FPU is enabled
This configuration is not in CI (hence why it lead to
a build error in the first place) so I just tested
it locally via sel4test with:

```
../init-build.sh -DPLATFORM=qemu-riscv-virt \
                 -DMCS=1 -DKernelRiscvExtD=1 \
                 -DKernelRiscvExtF=1 -DRISCV32=1
```

and it passed.

Signed-off-by: Ivan Velickovic <i.velickovic@unsw.edu.au>
2024-09-16 12:31:52 +01:00
Wanja Zaeske
05858be490 feat: add riscv-none-elf- as valid RISCV prefix
Fixes #1309

Signed-off-by: Wanja Zaeske <wanja.zaeske@dlr.de>
2024-08-14 15:33:19 +02:00
Ivan Velickovic
534ea259d3 Print virtual address already mapped in user error (#1304)
Print virtual address already mapped in user error

Co-authored-by: Axel Heider <axel-h@users.noreply.github.com>
Signed-off-by: Ivan Velickovic <i.velickovic@unsw.edu.au>
2024-08-13 20:29:39 +02:00
Michael McInerney
c679fe77d6 mcs: use local variable in postpone
This eases verification by using a local variable
which remains unchanged during execution of the
function.

This preserves semantics since tcbSchedDequeue
will not modify the scTcb field of the given sc.

Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2024-07-19 19:13:48 +10:00
Alwin Joshy
1253115999 hw debug api: aarch64 port
Adding support for the hardware debug API to
aarch64.

Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>
2024-07-18 16:09:52 +10:00
Alwin Joshy
b3974732b9 hw debug api: modify single stepping checks
On aarch32, single stepping is configured by setting an instruction
breakpoint to mismatch mode. The way that it is checked whether a
given breakpoint is being used as a normal breakpoint or for
single-stepping is by checking if it has been configured to mismatch.
This works because the HW debug API does not currently provide a way
to otherwise configure mismatch breakpoints, but seems like an
unsatisfactory solution. Whether single-stepping is enabled, and
the breakpoint that is being used for it is already stored in the
TCB of a thread, and this commit changes checks related to
single-stepping to use this information instead.

Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>
2024-07-18 16:09:52 +10:00
Alwin Joshy
28ffc62f74 aarch32: change dbg register fields
Changing the debug register fields to what they are referred to
as in the ARMv7 and ARMv8 manuals. Mostly a cosmetic change,
but improves clarity.

Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>
2024-07-18 16:09:52 +10:00
Alwin Joshy
c35930f565 change files to allow compilation
Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>
2024-07-18 16:09:52 +10:00
Indan Zupancic
e86bd7542c Split arm/machine/debug.c
Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>
2024-07-18 16:09:52 +10:00
Indan Zupancic
ad6a956103 Prepare Split arm/machine/debug.c
Signed-off-by: Alwin Joshy <joshyalwin@gmail.com>
2024-07-18 16:09:52 +10:00
Axel Heider
3c2c5ba18a risc-v: remove special handling for restoring tp
This is most likely an artifact from the change of the IPC buffer
handling before v11.0.0, where a thread-local register (tp on RISC-V)
was reserved by the kernel for storing the pointer to the thread's
IPC buffer. Architectures such as aarch64 would set the register
inside Arch_switchToThread() and then not touch the register in
restore_user_context(). When the RISC-V port was up-streamed, it
didn't restore the register with the other registers, but also
didn't restore it in Arch_switchToThread() and so ended up restoring
it right at the end of the restore process.

Co-authored-by: Kent McLeod <kent@kry10.com>
Signed-off-by: Axel Heider <axel.heider@codasip.com>
2024-07-18 11:55:55 +10:00
Axel Heider
11eb510ec3 cmake/QEMU: ensure output folder exists
Signed-off-by: Axel Heider <axel.heider@codasip.com>
2024-07-18 10:16:12 +10:00
Axel Heider
9e2e3a3d1a cmake: fix style issues
Signed-off-by: Axel Heider <axel.heider@codasip.com>
2024-07-18 10:16:12 +10:00
Michael McInerney
6b6bb12501 mcs: remove parameter from schedContext_unbindTCB
This removes the tcb parameter from schedContext_unbindTCB, which
is unnecessary, since it is always the scTcb of the given sc.

Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2024-07-17 09:11:51 +10:00
Michael McInerney
220ef4f94e mcs: refactor awaken
This refactors awaken, providing an inline function for the
while loop condition, and modifying tcbReleaseDequeue to now
perform the entire loop body.

Since tcbReleaseDequeue will perform tcbReleaseRemove on the
head of the release queue, the variable ksReprogram will be set
to true within tcbReleaseRemove, and therefore, we do not need
to set this variable separately within the loop body of awaken.

Signed-off-by: Michael McInerney <michael.mcinerney@proofcraft.systems>
2024-07-16 18:01:44 +10:00
Gerwin Klein
619a310a6e sel4-deps: tighten deps; update instructions
- require python >= 3
- require pyyaml < 6, because cmake-format breaks with pyyaml >= 6
- update upload instructions
- provide long-form release description of PyPi
- bump version, because the < 6 requirement might technically break
  compatibility

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-07-11 10:53:24 +10:00
Gerwin Klein
9567675c2b sel4-deps: update maintainer address
Use the TS pypi meta address for the maintainer.

Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
2024-07-11 10:00:32 +10:00