forked from Imagelibrary/seL4
aarch64,cortex-a53,hyp: Reduce seL4_UserTop value
This ensures that no frames can be mapped that would overwrite the currently stored VMID for the vspace. Signed-off-by: Kent McLeod <kent@kry10.com>
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@@ -28,6 +28,10 @@ Upcoming release: BREAKING
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* aarch32: Moved TPIDRURO (PL0 Read-Only Thread ID register) to TCB register context from VCPU registers. This means
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changes to this register from user level have to go via seL4_TCB_Write Registers instead of seL4_ARM_VCPU_WriteRegs.
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* aarch64,cortex-a53,hyp: Reduce seL4_UserTop when on a cortex-a53 platform and KernelArmHypervisorSupport is set.
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This is because the kernel uses the last slot in the top level VSpace object for storing the assigned VMID and so
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any addresses that are addressed by the final slot are not accessible.
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This would apply to any CPU that have 40bit stage 2 translation input address.
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## Upgrade Notes
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---
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@@ -260,6 +260,8 @@ SEL4_SIZE_SANITY(seL4_PUDEntryBits, seL4_PUDIndexBits, seL4_PUDBits);
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#define seL4_IPCBufferSizeBits 10
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#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
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/* 1 slot at the end of the vspace is used to hold the VMID assigned to the vspace */
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#define seL4_VSpaceReservedSlots 1
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/* The userspace occupies the range 0x0 to 0xfffffffffff.
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* The stage-1 translation is disabled, and the stage-2
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* translation input addree size is constrained by the
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@@ -271,7 +273,10 @@ SEL4_SIZE_SANITY(seL4_PUDEntryBits, seL4_PUDIndexBits, seL4_PUDBits);
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#if defined(CONFIG_ARM_PA_SIZE_BITS_44)
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#define seL4_UserTop 0x00000fffffffffff
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#elif defined(CONFIG_ARM_PA_SIZE_BITS_40)
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#define seL4_UserTop 0x000000ffffffffff
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/* Currently other definitions of seL4_UserTop already have free slots at the end and don't need to subtract for seL4_VSpaceReservedSlots.
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* Each slot used requires subtracting 1GiB from the top address.
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*/
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#define seL4_UserTop (0x000000ffffffffff - seL4_VSpaceReservedSlots * 0x40000000)
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#else
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#error "Unknown physical address width"
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#endif
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