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Aarch64: Align FPU vregs

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Aligning saves one cycle per LDP/STP instruction.

Signed-off-by: Indan Zupancic <indan@nul.nu>
This commit is contained in:
Indan Zupancic
2024-09-06 19:35:56 +01:00
committed by Gerwin Klein
parent db233b156d
commit 35a7fecbff
1 changed files with 6 additions and 0 deletions
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6
include/arch/arm/arch/64/mode/machine/registerset.h
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@@ -274,6 +274,7 @@ struct user_context {
user_breakpoint_state_t breakpointState;
#endif /* ARM_BASE_CP14_SAVE_AND_RESTORE */
#ifdef CONFIG_HAVE_FPU
word_t _padding;
user_fpu_state_t fpuState;
#endif /* CONFIG_HAVE_FPU */
};
@@ -282,6 +283,11 @@ typedef struct user_context user_context_t;
unverified_compile_assert(registers_are_first_member_of_user_context,
OFFSETOF(user_context_t, registers) == 0)
#ifdef CONFIG_HAVE_FPU
/* Aligning saves one cycle per LDP/STP instruction: */
unverified_compile_assert(vregs_are_16_bytes_aligned,
OFFSETOF(user_context_t, fpuState) % 16 == 0)
#endif
#ifdef ARM_BASE_CP14_SAVE_AND_RESTORE
void Arch_initBreakpointContext(user_context_t *context);