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aarch64: keep EL2 docs near hypervisor config

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Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
This commit is contained in:
Julia Vassiliki
2025-10-28 10:38:55 +11:00
committed by Indan Zupancic
parent 8d3313ac25
commit 0f058d05db
1 changed files with 46 additions and 42 deletions
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88
include/arch/arm/arch/64/mode/hardware.h
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@@ -11,47 +11,7 @@
#include <arch/machine/hardware.h>
#include <sel4/plat/api/constants.h>
/* EL2 kernel address map:
*
* The EL2 mode kernel uses TTBR0_EL2 which covers the range of
* 0x0 - 0x0000ffffffffffff (48 bits of vaddrspace).
*
* The CPU on the TX1 only allows for 48-bits of addressable virtual memory.
* Within the seL4 EL2 kernel's separate vaddrspace, it uses
* the 512 GiB at the top of that 48 bits of addressable
* virtual memory.
*
* In EL2 there is no canonical-high portion of the address space since
* address tagging is not supported in EL2. Therefore the kernel is linked
* to the canonical lower portion of the address space (all the unused top bits
* are set to 0, not 1).
*
* The memory map used by the EL2 kernel's separate address space
* ends up looking something like this:
*
* +-----------------------------------+ <- 0xFFFFFFFF_FFFFFFFF
* | Canonical high portion - unusable |
* | virtual addrs |
* +-----------------------------------+ <- PPTR_TOP: 256TiB mark (top of 48 bits)
* | seL4 EL2 kernel | ^
* | | |
* | | 512GiB
* | | of EL2 kernel windowing
* | | into memory.
* | | |
* | | v
* +-----------------------------------+ <- PPTR_BASE: 256TiB minus 512GiB.
* | Unused virtual addresses within | ^
* | the EL2 kernel's | |
* | separate vaddrspace. | Rest of the
* | | EL2 kernel
* | | vaddrspace, unused,
* | | which is the rest of
* | | the lower 256 TiB.
* | | |
* | | v
* +-----------------------------------+ <- 0x0
*
/*
* !defined(CONFIG_ARM_HYPERVISOR_SUPPORT)
*
* 2^64 +-------------------+
@@ -108,9 +68,53 @@
* | |
* 2^64 - 2^21 +-------------------+ KDEV_BASE
*
*
*/
/*
* defined(CONFIG_ARM_HYPERVISOR_SUPPORT)
*
* EL2 kernel address map:
*
* The EL2 mode kernel uses TTBR0_EL2 which covers the range of
* 0x0 - 0x0000ffffffffffff (48 bits of vaddrspace).
*
* The CPU on the TX1 only allows for 48-bits of addressable virtual memory.
* Within the seL4 EL2 kernel's separate vaddrspace, it uses
* the 512 GiB at the top of that 48 bits of addressable
* virtual memory.
*
* In EL2 there is no canonical-high portion of the address space since
* address tagging is not supported in EL2. Therefore the kernel is linked
* to the canonical lower portion of the address space (all the unused top bits
* are set to 0, not 1).
*
* The memory map used by the EL2 kernel's separate address space
* ends up looking something like this:
*
* +-----------------------------------+ <- 0xFFFFFFFF_FFFFFFFF
* | Canonical high portion - unusable |
* | virtual addrs |
* +-----------------------------------+ <- PPTR_TOP: 256TiB mark (top of 48 bits)
* | seL4 EL2 kernel | ^
* | | |
* | | 512GiB
* | | of EL2 kernel windowing
* | | into memory.
* | | |
* | | v
* +-----------------------------------+ <- PPTR_BASE: 256TiB minus 512GiB.
* | Unused virtual addresses within | ^
* | the EL2 kernel's | |
* | separate vaddrspace. | Rest of the
* | | EL2 kernel
* | | vaddrspace, unused,
* | | which is the rest of
* | | the lower 256 TiB.
* | | |
* | | v
* +-----------------------------------+ <- 0x0
*
*
* 2^64 +-------------------+
* | |
* | Unaddressable |