forked from Imagelibrary/rtems
ab8817ca03
Add directives to get and set the priority of an interrupt vector. Implement the directives for the following BSP families: * arm/lpc24xx * arm/lpc32xx * powerpc/mpc55xxevb * powerpc/qoriq Implement the directives for the following interrupt controllers: * GICv2 and GICv3 (arm and aarch64) * NVIC (arm) * PLIC (riscv) Update #5002.
407 lines
12 KiB
C
407 lines
12 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup DevIRQGIC
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*
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* @brief This header file provides interfaces of the ARM Generic Interrupt
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* Controller (GIC) support specific to the GICv3.
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*/
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/*
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* Copyright (C) 2022 embedded brains GmbH & Co. KG
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* Copyright (C) 2019 On-Line Applications Research Corporation (OAR)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RTEMS_DEV_IRQ_ARM_GICV3_H
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#define _RTEMS_DEV_IRQ_ARM_GICV3_H
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#include <dev/irq/arm-gic.h>
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#include <dev/irq/arm-gic-arch.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @addtogroup DevIRQGIC
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*
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* @{
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*/
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#define PRIORITY_DEFAULT 127
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#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
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#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
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#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
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#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
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#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
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#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
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#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
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#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
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#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
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#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)
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#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)
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#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)
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#define ICC_SGIR_IRM BSP_BIT32(40)
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#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)
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#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)
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#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
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#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)
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#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)
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#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)
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#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)
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#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)
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#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
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#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)
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#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)
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#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)
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#ifdef ARM_MULTILIB_ARCH_V4
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/* cpuif->iccicr */
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#define ICC_CTLR "p15, 0, %0, c12, c12, 4"
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/* cpuif->iccpmr */
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#define ICC_PMR "p15, 0, %0, c4, c6, 0"
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/* cpuif->iccbpr */
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#define ICC_BPR0 "p15, 0, %0, c12, c8, 3"
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#define ICC_BPR1 "p15, 0, %0, c12, c12, 3"
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/* cpuif->icciar */
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#define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
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#define ICC_IAR1 "p15, 0, %0, c12, c12, 0"
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/* cpuif->icceoir */
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#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1"
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#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1"
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#define ICC_SRE "p15, 0, %0, c12, c12, 5"
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#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
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#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
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#define MPIDR "p15, 0, %0, c0, c0, 5"
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#define READ_SR(SR_NAME) \
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({ \
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uint32_t value; \
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__asm__ volatile("mrc " SR_NAME : "=r" (value) ); \
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value; \
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})
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#define WRITE_SR(SR_NAME, VALUE) \
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__asm__ volatile("mcr " SR_NAME " \n" : : "r" (VALUE) );
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#define ICC_SGI1 "p15, 0, %Q0, %R0, c12"
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#define WRITE64_SR(SR_NAME, VALUE) \
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__asm__ volatile("mcrr " SR_NAME " \n" : : "r" (VALUE) );
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#else /* ARM_MULTILIB_ARCH_V4 */
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/* AArch64 GICv3 registers are not named in GCC */
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#define ICC_IGRPEN0_EL1 "S3_0_C12_C12_6, %0"
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#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7, %0"
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#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
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#define ICC_IGRPEN0 ICC_IGRPEN0_EL1
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#define ICC_IGRPEN1 ICC_IGRPEN1_EL1
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#define ICC_PMR "S3_0_C4_C6_0, %0"
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#define ICC_EOIR1 "S3_0_C12_C12_1, %0"
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#define ICC_SRE "S3_0_C12_C12_5, %0"
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#define ICC_BPR0 "S3_0_C12_C8_3, %0"
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#define ICC_BPR1 "S3_0_C12_C12_3, %0"
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#define ICC_CTLR "S3_0_C12_C12_4, %0"
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#define ICC_IAR1 "%0, S3_0_C12_C12_0"
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#define MPIDR "%0, mpidr_el1"
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#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)
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#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)
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#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
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#define ICC_SGI1 "S3_0_C12_C11_5, %0"
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#define WRITE64_SR(SR_NAME, VALUE) \
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__asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) );
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#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)
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#define READ_SR(SR_NAME) \
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({ \
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uint64_t value; \
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__asm__ volatile("mrs " SR_NAME : "=&r" (value) ); \
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value; \
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})
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#endif /* ARM_MULTILIB_ARCH_V4 */
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static inline volatile gic_redist *gicv3_get_redist(uint32_t cpu_index)
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{
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return (volatile gic_redist *)
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((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000);
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}
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static inline volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
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{
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return (volatile gic_sgi_ppi *)
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((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000);
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}
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static inline void gicv3_sgi_ppi_enable(
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rtems_vector_number vector,
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uint32_t cpu_index
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)
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{
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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/* Set G1NS */
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sgi_ppi->icspigrpr[0] |= 1U << vector;
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sgi_ppi->icspigrpmodr[0] &= ~(1U << vector);
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/* Set enable */
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sgi_ppi->icspiser[0] = 1U << vector;
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}
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static inline void gicv3_sgi_ppi_disable(
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rtems_vector_number vector,
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uint32_t cpu_index
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)
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{
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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sgi_ppi->icspicer[0] = 1U << vector;
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}
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static inline bool gicv3_sgi_ppi_is_enabled(
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rtems_vector_number vector,
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uint32_t cpu_index
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)
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{
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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return (sgi_ppi->icspiser[0] & (1U << vector)) != 0;
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}
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static inline void gicv3_sgi_ppi_set_priority(
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rtems_vector_number vector,
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uint8_t priority,
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uint32_t cpu_index
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)
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{
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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sgi_ppi->icspiprior[vector] = priority;
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}
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static inline uint8_t gicv3_sgi_ppi_get_priority(
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rtems_vector_number vector,
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uint32_t cpu_index
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)
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{
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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return sgi_ppi->icspiprior[vector];
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}
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static inline bool gicv3_sgi_ppi_is_pending(
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rtems_vector_number vector,
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uint32_t cpu_index
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)
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{
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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return (sgi_ppi->icspispendr[0] & (1U << vector)) != 0;
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}
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static inline void gicv3_ppi_set_pending(
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rtems_vector_number vector,
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uint32_t cpu_index
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)
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{
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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sgi_ppi->icspispendr[0] = 1U << vector;
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}
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static inline void gicv3_ppi_clear_pending(
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rtems_vector_number vector,
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uint32_t cpu_index
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)
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{
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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sgi_ppi->icspicpendr[0] = 1U << vector;
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}
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static inline void gicv3_trigger_sgi(
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rtems_vector_number vector,
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uint32_t targets
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)
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{
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#ifndef ARM_MULTILIB_ARCH_V4
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uint64_t mpidr;
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#else
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uint32_t mpidr;
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#endif
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mpidr = READ_SR(MPIDR);
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uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
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| ICC_SGIR_INTID(vector)
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| ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
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| ICC_SGIR_CPU_TARGET_LIST(targets);
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#ifndef ARM_MULTILIB_ARCH_V4
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value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
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#endif
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WRITE64_SR(ICC_SGI1, value);
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}
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static inline uint32_t gicv3_get_id_count(volatile gic_dist *dist)
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{
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uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr);
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id_count = 32 * (id_count + 1);
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id_count = id_count <= 1020 ? id_count : 1020;
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return id_count;
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}
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static void gicv3_init_dist(volatile gic_dist *dist)
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{
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uint32_t id_count = gicv3_get_id_count(dist);
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uint32_t id;
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dist->icddcr = GIC_DIST_ICDDCR_ARE_NS | GIC_DIST_ICDDCR_ARE_S
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| GIC_DIST_ICDDCR_ENABLE_GRP1S | GIC_DIST_ICDDCR_ENABLE_GRP1NS
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| GIC_DIST_ICDDCR_ENABLE_GRP0;
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for (id = 0; id < id_count; id += 32) {
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/* Disable all interrupts */
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dist->icdicer[id / 32] = 0xffffffff;
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/* Set G1NS */
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dist->icdigr[id / 32] = 0xffffffff;
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dist->icdigmr[id / 32] = 0;
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}
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for (id = 0; id < id_count; ++id) {
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gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
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}
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for (id = 32; id < id_count; ++id) {
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gic_id_set_targets(dist, id, 0x01);
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}
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}
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static void gicv3_init_cpu_interface(uint32_t cpu_index)
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{
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/* Initialize Interrupt Controller System Register Enable Register */
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#ifdef BSP_ARM_GIC_ICC_SRE
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WRITE_SR(ICC_SRE, BSP_ARM_GIC_ICC_SRE);
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#endif
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/* Initialize Interrupt Controller Interrupt Priority Mask Register */
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#ifdef BSP_ARM_GIC_ICC_PMR
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WRITE_SR(ICC_PMR, BSP_ARM_GIC_ICC_PMR);
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#endif
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/* Initialize Interrupt Controller Binary Point Register 0 */
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#ifdef BSP_ARM_GIC_ICC_BPR0
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WRITE_SR(ICC_BPR0, BSP_ARM_GIC_ICC_BPR0);
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#endif
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/* Initialize Interrupt Controller Binary Point Register 1 */
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#ifdef BSP_ARM_GIC_ICC_BPR1
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WRITE_SR(ICC_BPR1, BSP_ARM_GIC_ICC_BPR1);
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#endif
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volatile gic_redist *redist = gicv3_get_redist(cpu_index);
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uint32_t waker = redist->icrwaker;
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uint32_t waker_mask = GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP;
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waker &= ~waker_mask;
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redist->icrwaker = waker;
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volatile gic_sgi_ppi *sgi_ppi = gicv3_get_sgi_ppi(cpu_index);
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/* Set G1NS */
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sgi_ppi->icspigrpr[0] = 0xffffffff;
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sgi_ppi->icspigrpmodr[0] = 0;
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for (int id = 0; id < 32; id++) {
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sgi_ppi->icspiprior[id] = PRIORITY_DEFAULT;
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}
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/* Initialize Interrupt Controller Interrupt Group Enable 0 Register */
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#ifdef BSP_ARM_GIC_ICC_IGRPEN0
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WRITE_SR(ICC_IGRPEN0, BSP_ARM_GIC_ICC_IGRPEN0);
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#endif
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/* Initialize Interrupt Controller Interrupt Group Enable 1 Register */
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#ifdef BSP_ARM_GIC_ICC_IGRPEN1
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WRITE_SR(ICC_IGRPEN1, BSP_ARM_GIC_ICC_IGRPEN1);
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#endif
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/* Initialize Interrupt Controller Control Register */
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#ifdef BSP_ARM_GIC_ICC_CTRL
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WRITE_SR(ICC_CTLR, BSP_ARM_GIC_ICC_CTRL);
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#endif
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}
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static inline void gicv3_get_attributes(
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rtems_vector_number vector,
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rtems_interrupt_attributes *attributes
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)
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{
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attributes->is_maskable = true;
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attributes->maybe_enable = true;
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attributes->maybe_disable = true;
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attributes->can_raise = true;
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attributes->can_get_priority = true;
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attributes->can_set_priority = true;
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attributes->maximum_priority = 255;
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if ( vector <= ARM_GIC_IRQ_SGI_LAST ) {
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/*
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* It is implementation-defined whether implemented SGIs are permanently
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* enabled, or can be enabled and disabled by writes to GICD_ISENABLER0 and
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* GICD_ICENABLER0.
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*/
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attributes->can_raise_on = true;
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attributes->cleared_by_acknowledge = true;
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attributes->trigger_signal = RTEMS_INTERRUPT_NO_SIGNAL;
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} else {
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attributes->can_disable = true;
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attributes->can_clear = true;
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attributes->trigger_signal = RTEMS_INTERRUPT_UNSPECIFIED_SIGNAL;
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if ( vector > ARM_GIC_IRQ_PPI_LAST ) {
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/* SPI */
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attributes->can_get_affinity = true;
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attributes->can_set_affinity = true;
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}
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}
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}
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTEMS_DEV_IRQ_ARM_GICV3_H */
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