forked from Imagelibrary/rtems
285 lines
11 KiB
C
285 lines
11 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/**
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******************************************************************************
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* @file stm32h747i_eval_qspi.h
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* @author MCD Application Team
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* @brief This file contains the common defines and functions prototypes for
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* the stm32h747i_eval_qspi.c driver.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/*
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* RTEMS committer clarification comment on license above:
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*
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* This file comes from STM32CubeH7 project and is located here:
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* https://github.com/STMicroelectronics/STM32CubeH7/blob/master/Drivers/BSP/STM32H747I-EVAL/stm32h747i_eval_qspi.h
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*
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* The file root directory is:
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* https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Drivers/BSP/STM32H747I-EVAL
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*
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* This directory contains LICENSE.md file with a following license text:
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*
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* Copyright 2019 STMicroelectronics.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H747I_EVAL_QSPI_H
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#define STM32H747I_EVAL_QSPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h747i_eval_conf.h"
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#include "stm32h747i_eval_errno.h"
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#include "../Components/mt25tl01g/mt25tl01g.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup STM32H747I_EVAL
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* @{
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*/
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/** @addtogroup STM32H747I_EVAL_QSPI
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup STM32H747I_EVAL_QSPI_Exported_Types QSPI Exported Types
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* @{
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*/
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#define BSP_QSPI_Info_t MT25TL01G_Info_t
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#define BSP_QSPI_Interface_t MT25TL01G_Interface_t
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#define BSP_QSPI_Transfer_t MT25TL01G_Transfer_t
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#define BSP_QSPI_DualFlash_t MT25TL01G_DualFlash_t
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#define BSP_QSPI_ODS_t MT25TL01G_ODS_t
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typedef enum
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{
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BSP_QSPI_ERASE_8K = MT25TL01G_ERASE_4K , /*!< 8K size Sector erase = 2 x 4K as Dual flash mode is used for this board */
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BSP_QSPI_ERASE_64K = MT25TL01G_ERASE_32K , /*!< 64K size Sector erase = 2 x 32K as Dual flash mode is used for this board */
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BSP_QSPI_ERASE_128K = MT25TL01G_ERASE_64K , /*!< 128K size Sector erase = 2 x 64K as Dual mode is used for this board */
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BSP_QSPI_ERASE_CHIP = MT25TL01G_ERASE_CHIP /*!< Whole chip erase */
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} BSP_QSPI_Erase_t;
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typedef enum
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{
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QSPI_ACCESS_NONE = 0, /*!< Instance not initialized, */
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QSPI_ACCESS_INDIRECT, /*!< Instance use indirect mode access */
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QSPI_ACCESS_MMP /*!< Instance use Memory Mapped Mode read */
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} BSP_QSPI_Access_t;
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typedef struct
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{
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BSP_QSPI_Access_t IsInitialized; /*!< Instance access Flash method */
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BSP_QSPI_Interface_t InterfaceMode; /*!< Flash Interface mode of Instance */
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BSP_QSPI_Transfer_t TransferRate; /*!< Flash Transfer mode of Instance */
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uint32_t DualFlashMode; /*!< Flash dual mode */
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uint32_t IsMspCallbacksValid;
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} BSP_QSPI_Ctx_t;
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typedef struct
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{
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BSP_QSPI_Interface_t InterfaceMode; /*!< Current Flash Interface mode */
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BSP_QSPI_Transfer_t TransferRate; /*!< Current Flash Transfer mode */
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BSP_QSPI_DualFlash_t DualFlashMode; /*!< Dual Flash mode */
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} BSP_QSPI_Init_t;
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typedef struct
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{
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uint32_t FlashSize;
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uint32_t ClockPrescaler;
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uint32_t SampleShifting;
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uint32_t DualFlashMode;
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}MX_QSPI_Init_t;
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#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
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typedef struct
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{
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void(*pMspInitCb)(pQSPI_CallbackTypeDef);
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void(*pMspDeInitCb)(pQSPI_CallbackTypeDef);
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}BSP_QSPI_Cb_t;
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#endif /* (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) */
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup STM32H747I_EVAL_QSPI_Exported_Constants QSPI Exported Constants
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* @{
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*/
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/* QSPI instances number */
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#define QSPI_INSTANCES_NUMBER 1U
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/* Definition for QSPI modes */
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#define BSP_QSPI_SPI_MODE (BSP_QSPI_Interface_t)MT25TL01G_SPI_MODE /* 1 Cmd Line, 1 Address Line and 1 Data Line */
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#define BSP_QSPI_SPI_1I2O_MODE (BSP_QSPI_Interface_t)MT25TL01G_SPI_1I2O_MODE /* 1 Cmd Line, 1 Address Line and 2 Data Lines */
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#define BSP_QSPI_SPI_2IO_MODE (BSP_QSPI_Interface_t)MT25TL01G_SPI_2IO_MODE /* 1 Cmd Line, 2 Address Lines and 2 Data Lines */
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#define BSP_QSPI_SPI_1I4O_MODE (BSP_QSPI_Interface_t)MT25TL01G_SPI_1I4O_MODE /* 1 Cmd Line, 1 Address Line and 4 Data Lines */
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#define BSP_QSPI_SPI_4IO_MODE (BSP_QSPI_Interface_t)MT25TL01G_SPI_4IO_MODE /* 1 Cmd Line, 4 Address Lines and 4 Data Lines */
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#define BSP_QSPI_DPI_MODE (BSP_QSPI_Interface_t)MT25TL01G_DPI_MODE /* 2 Cmd Lines, 2 Address Lines and 2 Data Lines */
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#define BSP_QSPI_QPI_MODE (BSP_QSPI_Interface_t)MT25TL01G_QPI_MODE /* 4 Cmd Lines, 4 Address Lines and 4 Data Lines */
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/* Definition for QSPI transfer rates */
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#define BSP_QSPI_STR_TRANSFER (BSP_QSPI_Transfer_t)MT25TL01G_STR_TRANSFER /* Single Transfer Rate */
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#define BSP_QSPI_DTR_TRANSFER (BSP_QSPI_Transfer_t)MT25TL01G_DTR_TRANSFER /* Double Transfer Rate */
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/* Definition for QSPI dual flash mode */
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#define BSP_QSPI_DUALFLASH_DISABLE (BSP_QSPI_DualFlash_t)MT25TL01G_DUALFLASH_DISABLE /* Dual flash mode enabled */
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/* Definition for QSPI Flash ID */
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#define BSP_QSPI_FLASH_ID QSPI_FLASH_ID_1
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/* QSPI block sizes for dual flash */
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#define BSP_QSPI_BLOCK_8K MT25TL01G_SECTOR_4K
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#define BSP_QSPI_BLOCK_64K MT25TL01G_BLOCK_32K
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#define BSP_QSPI_BLOCK_128K MT25TL01G_BLOCK_64K
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/* Definition for QSPI clock resources */
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#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
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#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
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#define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define QSPI_BK1_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define QSPI_BK1_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_BK1_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_BK1_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_BK1_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_BK2_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
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#define QSPI_BK2_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()
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#define QSPI_BK2_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOH_CLK_ENABLE()
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#define QSPI_BK2_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define QSPI_BK2_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
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#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
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/* Definition for QSPI Pins */
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#define QSPI_CLK_PIN GPIO_PIN_2
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#define QSPI_CLK_GPIO_PORT GPIOB
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/* Bank 1 */
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#define QSPI_BK1_CS_PIN GPIO_PIN_6
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#define QSPI_BK1_CS_GPIO_PORT GPIOG
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#define QSPI_BK1_D0_PIN GPIO_PIN_8
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#define QSPI_BK1_D0_GPIO_PORT GPIOF
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#define QSPI_BK1_D1_PIN GPIO_PIN_9
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#define QSPI_BK1_D1_GPIO_PORT GPIOF
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#define QSPI_BK1_D2_PIN GPIO_PIN_7
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#define QSPI_BK1_D2_GPIO_PORT GPIOF
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#define QSPI_BK1_D3_PIN GPIO_PIN_6
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#define QSPI_BK1_D3_GPIO_PORT GPIOF
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/* Bank 2 */
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#define QSPI_BK2_CS_PIN GPIO_PIN_11
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#define QSPI_BK2_CS_GPIO_PORT GPIOC
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#define QSPI_BK2_D0_PIN GPIO_PIN_2
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#define QSPI_BK2_D0_GPIO_PORT GPIOH
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#define QSPI_BK2_D1_PIN GPIO_PIN_3
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#define QSPI_BK2_D1_GPIO_PORT GPIOH
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#define QSPI_BK2_D2_PIN GPIO_PIN_9
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#define QSPI_BK2_D2_GPIO_PORT GPIOG
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#define QSPI_BK2_D3_PIN GPIO_PIN_14
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#define QSPI_BK2_D3_GPIO_PORT GPIOG
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/* MT25TL01G Micron memory */
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/* Size of the flash */
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#define QSPI_FLASH_SIZE 26 /* Address bus width to access whole memory space */
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#define QSPI_PAGE_SIZE 256
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/* QSPI Base Address */
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#define QSPI_BASE_ADDRESS 0x90000000
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/**
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* @}
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*/
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/** @addtogroup STM32H747I_EVAL_QSPI_Exported_Variables
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* @{
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*/
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extern QSPI_HandleTypeDef hqspi;
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extern BSP_QSPI_Ctx_t QSPI_Ctx[];
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup STM32H747I_EVAL_QSPI_Exported_Functions
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* @{
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*/
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int32_t BSP_QSPI_Init(uint32_t Instance, BSP_QSPI_Init_t *Init);
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int32_t BSP_QSPI_DeInit(uint32_t Instance);
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#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
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int32_t BSP_QSPI_RegisterMspCallbacks (uint32_t Instance, BSP_QSPI_Cb_t *CallBacks);
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int32_t BSP_QSPI_RegisterDefaultMspCallbacks (uint32_t Instance);
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#endif /* (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) */
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int32_t BSP_QSPI_Read(uint32_t Instance, uint8_t *pData, uint32_t ReadAddr, uint32_t Size);
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int32_t BSP_QSPI_Write(uint32_t Instance, uint8_t *pData, uint32_t WriteAddr, uint32_t Size);
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int32_t BSP_QSPI_EraseBlock(uint32_t Instance, uint32_t BlockAddress, BSP_QSPI_Erase_t BlockSize);
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int32_t BSP_QSPI_EraseChip(uint32_t Instance);
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int32_t BSP_QSPI_GetStatus(uint32_t Instance);
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int32_t BSP_QSPI_GetInfo(uint32_t Instance, BSP_QSPI_Info_t *pInfo);
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int32_t BSP_QSPI_EnableMemoryMappedMode(uint32_t Instance);
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int32_t BSP_QSPI_DisableMemoryMappedMode(uint32_t Instance);
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int32_t BSP_QSPI_ReadID(uint32_t Instance, uint8_t *Id);
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int32_t BSP_QSPI_ConfigFlash(uint32_t Instance, BSP_QSPI_Interface_t Mode, BSP_QSPI_Transfer_t Rate);
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/* These functions can be modified in case the current settings
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need to be changed for specific application needs */
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HAL_StatusTypeDef MX_QSPI_Init(QSPI_HandleTypeDef *hQspi, MX_QSPI_Init_t *Config);
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32H747I_EVAL_QSPI_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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