forked from Imagelibrary/rtems
19f12d2dca
If the Double Trap Extension is implemented, the MDT bit of the mstatus (or mstatush in RV32) register will be set when a trap is to be taken. The MIE (Machine Interrupt Enable) bit can only be set to 1 if the MDT bit is zero. Thus, we need to clear MDT first if we want to enable interrupts when dispatching a thread. MDT is also cleared in register a1 before restoring the interrupt frame as writing 1 to MDT will cause MIE to be set to 0. In RV64 this happens regardless of the value written to MIE in the same write. In RV32, MDT is in the mstatush so we do not need to clear during restore as this register is not restored. With this change all 60 SMP tests pass (compared to 20/60 before the fix). The tests have been run on hardware using two RV64 CPUs that implement the double trap extension. Update #5274
Real-Time Executive for Multiprocessing Systems
RTEMS is a real-time executive (kernel) which provides a high performance environment for embedded applications with the following features:
- Standards based user interfaces.
- Multitasking capabilities.
- Homogeneous and heterogeneous multiprocessor systems.
- Event-driven, priority-based, preemptive scheduling.
- Optional rate monotonic scheduling.
- Intertask communication and synchronisation.
- Priority inheritance.
- Responsive interrupt management.
- Dynamic memory allocation.
- High level of user configurability.
- Open source with a friendly user license.
Project git repositories are located at:
Online documentation is available at:
RTEMS Doxygen for CPUKit:
RTEMS POSIX 1003.1 Compliance Guide:
RTEMS Mailing Lists for general purpose use the users list and for developers use the devel list.
The version number for this software is indicated in the VERSION file.