Upgrade to 4.9.6

PR 1839/filesystem
	* libcsupport/include/rtems/libio_.h, libcsupport/src/fchdir.c,
	libcsupport/src/fdatasync.c, libcsupport/src/fpathconf.c,
	libcsupport/src/fsync.c, libcsupport/src/read.c,
	libcsupport/src/readv.c, libcsupport/src/write.c,
	libcsupport/src/writev.c: Some calls did not return proper status for
	permission errors or incorrectly permissions at all.

.cvsignore

@@ -0,0 +1,17 @@
+aclocal.m4
+autom4te*.cache
+compile
+config.cache
+config.guess
+config.log
+config.status
+config.sub
+configure
+depcomp
+install-sh
+install.sh
+Makefile
+Makefile.in
+mdate-sh
+missing
+texinfo.tex

.gitignore

@@ -1,6 +0,0 @@
-aclocal.m4
-autom4te.cache
-configure
-config.h.in
-Makefile.in
-doc

COPYING

@@ -0,0 +1,343 @@
+#
+# $RTEMS$
+#
+
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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+
+			    Preamble
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+
+	Appendix: How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
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+
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+
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+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.

INSTALL

@@ -1,4 +1,51 @@
+#
+#  $Id$
+#
+
 Building RTEMS
 ==============
-See the documentation referred to in the README.
+See the file README.configure.
+
+
+UNCOMPRESSING .tgz FILES
+===========================
+Many of the files found in this directory and its subdirectories 
+are gzip'ed, tar archive files.  These files have the ".tgz"
+extension.  They were compressed with gzip version 1.2.4.  
+
+Use a command sequence similar to the following to uncompress each
+file:
+
+   gzcat FILE.tgz | tar xvof -
+
+where FILE.tgz is the file to be installed.  This procedure will
+extract the files in the archive into the current directory.
+All of the .tgz files associated with this release RTEMS will
+place their contents in a subdirectory rtems-<release> in the current
+directory.
+
+If you are unsure of what is in an RTEMS archive file, then use
+the following command sequence to get a listing of the contents:
+
+   gzcat FILE.tgz | tar tvf -
+
+NOTES:  
+
+(1) The "-o" option to tar is included on the tar command line
+    so that the user extracting the tar archive will own the extracted
+    files.
+
+(2) gzcat is sometimes installed as zcat.  Be warned that on many
+    (most) UNIX machines, zcat is associated with compress (.Z files).
+
+(3) If you do not have gzip 1.2.4, it is available from numerous sites
+    including this one.  Other sites include ftp.gnu.org and ftp.cdrom.com.
+    
+(4) The GNU archive files included in this distribution are packaged
+    exactly like they are on official GNU ftp sites.  When extracting
+    GNU archives, they will not extract under a rtems-<version> 
+    directory.  They will extract themselves under a directory which
+    is the name and version of the tool in question.  For example,
+    gcc-2.5.8.tgz will extract its contents into the subdirectory 
+    gcc-2.5.8.
 

LICENSE

@@ -1,3 +1,6 @@
+#
+#  $Id$
+# 
                       LICENSE INFORMATION
 
 RTEMS is free software; you can redistribute it and/or modify it under

LICENSE.BSD-2-Clause

@@ -1,51 +0,0 @@
-https://spdx.org/licenses/BSD-2-Clause.html
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-
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-
-The <FIRST NAME> is your first name (also known as given name), the
-<MIDDLE NAMES> are your optional middle names, the <LAST NAME> is your last
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LICENSE.CC-BY-SA-4.0

@@ -1,428 +0,0 @@
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-     public may access the material from a place and at a time
-     individually chosen by them.
-
-  l. Sui Generis Database Rights means rights other than copyright
-     resulting from Directive 96/9/EC of the European Parliament and of
-     the Council of 11 March 1996 on the legal protection of databases,
-     as amended and/or succeeded, as well as other essentially
-     equivalent rights anywhere in the world.
-
-  m. You means the individual or entity exercising the Licensed Rights
-     under this Public License. Your has a corresponding meaning.
-
-
-Section 2 -- Scope.
-
-  a. License grant.
-
-       1. Subject to the terms and conditions of this Public License,
-          the Licensor hereby grants You a worldwide, royalty-free,
-          non-sublicensable, non-exclusive, irrevocable license to
-          exercise the Licensed Rights in the Licensed Material to:
-
-            a. reproduce and Share the Licensed Material, in whole or
-               in part; and
-
-            b. produce, reproduce, and Share Adapted Material.
-
-       2. Exceptions and Limitations. For the avoidance of doubt, where
-          Exceptions and Limitations apply to Your use, this Public
-          License does not apply, and You do not need to comply with
-          its terms and conditions.
-
-       3. Term. The term of this Public License is specified in Section
-          6(a).
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-       4. Media and formats; technical modifications allowed. The
-          Licensor authorizes You to exercise the Licensed Rights in
-          all media and formats whether now known or hereafter created,
-          and to make technical modifications necessary to do so. The
-          Licensor waives and/or agrees not to assert any right or
-          authority to forbid You from making technical modifications
-          necessary to exercise the Licensed Rights, including
-          technical modifications necessary to circumvent Effective
-          Technological Measures. For purposes of this Public License,
-          simply making modifications authorized by this Section 2(a)
-          (4) never produces Adapted Material.
-
-       5. Downstream recipients.
-
-            a. Offer from the Licensor -- Licensed Material. Every
-               recipient of the Licensed Material automatically
-               receives an offer from the Licensor to exercise the
-               Licensed Rights under the terms and conditions of this
-               Public License.
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-            b. Additional offer from the Licensor -- Adapted Material.
-               Every recipient of Adapted Material from You
-               automatically receives an offer from the Licensor to
-               exercise the Licensed Rights in the Adapted Material
-               under the conditions of the Adapter's License You apply.
-
-            c. No downstream restrictions. You may not offer or impose
-               any additional or different terms or conditions on, or
-               apply any Effective Technological Measures to, the
-               Licensed Material if doing so restricts exercise of the
-               Licensed Rights by any recipient of the Licensed
-               Material.
-
-       6. No endorsement. Nothing in this Public License constitutes or
-          may be construed as permission to assert or imply that You
-          are, or that Your use of the Licensed Material is, connected
-          with, or sponsored, endorsed, or granted official status by,
-          the Licensor or others designated to receive attribution as
-          provided in Section 3(a)(1)(A)(i).
-
-  b. Other rights.
-
-       1. Moral rights, such as the right of integrity, are not
-          licensed under this Public License, nor are publicity,
-          privacy, and/or other similar personality rights; however, to
-          the extent possible, the Licensor waives and/or agrees not to
-          assert any such rights held by the Licensor to the limited
-          extent necessary to allow You to exercise the Licensed
-          Rights, but not otherwise.
-
-       2. Patent and trademark rights are not licensed under this
-          Public License.
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-       3. To the extent possible, the Licensor waives any right to
-          collect royalties from You for the exercise of the Licensed
-          Rights, whether directly or through a collecting society
-          under any voluntary or waivable statutory or compulsory
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-Section 3 -- License Conditions.
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-Your exercise of the Licensed Rights is expressly made subject to the
-following conditions.
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-  a. Attribution.
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-       1. If You Share the Licensed Material (including in modified
-          form), You must:
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-               with the Licensed Material:
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-                    Material and any others designated to receive
-                    attribution, in any reasonable manner requested by
-                    the Licensor (including by pseudonym if
-                    designated);
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-                ii. a copyright notice;
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-               iii. a notice that refers to this Public License;
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-                iv. a notice that refers to the disclaimer of
-                    warranties;
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-                 v. a URI or hyperlink to the Licensed Material to the
-                    extent reasonably practicable;
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-               retain an indication of any previous modifications; and
-
-            c. indicate the Licensed Material is licensed under this
-               Public License, and include the text of, or the URI or
-               hyperlink to, this Public License.
-
-       2. You may satisfy the conditions in Section 3(a)(1) in any
-          reasonable manner based on the medium, means, and context in
-          which You Share the Licensed Material. For example, it may be
-          reasonable to satisfy the conditions by providing a URI or
-          hyperlink to a resource that includes the required
-          information.
-
-       3. If requested by the Licensor, You must remove any of the
-          information required by Section 3(a)(1)(A) to the extent
-          reasonably practicable.
-
-  b. ShareAlike.
-
-     In addition to the conditions in Section 3(a), if You Share
-     Adapted Material You produce, the following conditions also apply.
-
-       1. The Adapter's License You apply must be a Creative Commons
-          license with the same License Elements, this version or
-          later, or a BY-SA Compatible License.
-
-       2. You must include the text of, or the URI or hyperlink to, the
-          Adapter's License You apply. You may satisfy this condition
-          in any reasonable manner based on the medium, means, and
-          context in which You Share Adapted Material.
-
-       3. You may not offer or impose any additional or different terms
-          or conditions on, or apply any Effective Technological
-          Measures to, Adapted Material that restrict exercise of the
-          rights granted under the Adapter's License You apply.
-
-
-Section 4 -- Sui Generis Database Rights.
-
-Where the Licensed Rights include Sui Generis Database Rights that
-apply to Your use of the Licensed Material:
-
-  a. for the avoidance of doubt, Section 2(a)(1) grants You the right
-     to extract, reuse, reproduce, and Share all or a substantial
-     portion of the contents of the database;
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-  b. if You include all or a substantial portion of the database
-     contents in a database in which You have Sui Generis Database
-     Rights, then the database in which You have Sui Generis Database
-     Rights (but not its individual contents) is Adapted Material,
-
-     including for purposes of Section 3(b); and
-  c. You must comply with the conditions in Section 3(a) if You Share
-     all or a substantial portion of the contents of the database.
-
-For the avoidance of doubt, this Section 4 supplements and does not
-replace Your obligations under this Public License where the Licensed
-Rights include other Copyright and Similar Rights.
-
-
-Section 5 -- Disclaimer of Warranties and Limitation of Liability.
-
-  a. UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE
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-     ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT
-     KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT
-     ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.
-
-  b. TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE
-     TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION,
-     NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT,
-     INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES,
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-     IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.
-
-  c. The disclaimer of warranties and limitation of liability provided
-     above shall be interpreted in a manner that, to the extent
-     possible, most closely approximates an absolute disclaimer and
-     waiver of all liability.
-
-
-Section 6 -- Term and Termination.
-
-  a. This Public License applies for the term of the Copyright and
-     Similar Rights licensed here. However, if You fail to comply with
-     this Public License, then Your rights under this Public License
-     terminate automatically.
-
-  b. Where Your right to use the Licensed Material has terminated under
-     Section 6(a), it reinstates:
-
-       1. automatically as of the date the violation is cured, provided
-          it is cured within 30 days of Your discovery of the
-          violation; or
-
-       2. upon express reinstatement by the Licensor.
-
-     For the avoidance of doubt, this Section 6(b) does not affect any
-     right the Licensor may have to seek remedies for Your violations
-     of this Public License.
-
-  c. For the avoidance of doubt, the Licensor may also offer the
-     Licensed Material under separate terms or conditions or stop
-     distributing the Licensed Material at any time; however, doing so
-     will not terminate this Public License.
-
-  d. Sections 1, 5, 6, 7, and 8 survive termination of this Public
-     License.
-
-
-Section 7 -- Other Terms and Conditions.
-
-  a. The Licensor shall not be bound by any additional or different
-     terms or conditions communicated by You unless expressly agreed.
-
-  b. Any arrangements, understandings, or agreements regarding the
-     Licensed Material not stated herein are separate from and
-     independent of the terms and conditions of this Public License.
-
-
-Section 8 -- Interpretation.
-
-  a. For the avoidance of doubt, this Public License does not, and
-     shall not be interpreted to, reduce, limit, restrict, or impose
-     conditions on any use of the Licensed Material that could lawfully
-     be made without permission under this Public License.
-
-  b. To the extent possible, if any provision of this Public License is
-     deemed unenforceable, it shall be automatically reformed to the
-     minimum extent necessary to make it enforceable. If the provision
-     cannot be reformed, it shall be severed from this Public License
-     without affecting the enforceability of the remaining terms and
-     conditions.
-
-  c. No term or condition of this Public License will be waived and no
-     failure to comply consented to unless expressly agreed to by the
-     Licensor.
-
-  d. Nothing in this Public License constitutes or may be interpreted
-     as a limitation upon, or waiver of, any privileges and immunities
-     that apply to the Licensor or You, including from the legal
-     processes of any jurisdiction or authority.
-
-
-=======================================================================
-
-Creative Commons is not a party to its public
-licenses. Notwithstanding, Creative Commons may elect to apply one of
-its public licenses to material it publishes and in those instances
-will be considered the “Licensor.” The text of the Creative Commons
-public licenses is dedicated to the public domain under the CC0 Public
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-public licenses.
-
-Creative Commons may be contacted at creativecommons.org.
-

LICENSE.GPL-2.0

@@ -1,339 +0,0 @@
-                    GNU GENERAL PUBLIC LICENSE
-                       Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
-                            Preamble
-
-  The licenses for most software are designed to take away your
-freedom to share and change it.  By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
-software--to make sure the software is free for all its users.  This
-General Public License applies to most of the Free Software
-Foundation's software and to any other program whose authors commit to
-using it.  (Some other Free Software Foundation software is covered by
-the GNU Lesser General Public License instead.)  You can apply it to
-your programs, too.
-
-  When we speak of free software, we are referring to freedom, not
-price.  Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
-  To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if you
-distribute copies of the software, or if you modify it.
-
-  For example, if you distribute copies of such a program, whether
-gratis or for a fee, you must give the recipients all the rights that
-you have.  You must make sure that they, too, receive or can get the
-source code.  And you must show them these terms so they know their
-rights.
-
-  We protect your rights with two steps: (1) copyright the software, and
-(2) offer you this license which gives you legal permission to copy,
-distribute and/or modify the software.
-
-  Also, for each author's protection and ours, we want to make certain
-that everyone understands that there is no warranty for this free
-software.  If the software is modified by someone else and passed on, we
-want its recipients to know that what they have is not the original, so
-that any problems introduced by others will not reflect on the original
-authors' reputations.
-
-  Finally, any free program is threatened constantly by software
-patents.  We wish to avoid the danger that redistributors of a free
-program will individually obtain patent licenses, in effect making the
-program proprietary.  To prevent this, we have made it clear that any
-patent must be licensed for everyone's free use or not licensed at all.
-
-  The precise terms and conditions for copying, distribution and
-modification follow.
-
-                    GNU GENERAL PUBLIC LICENSE
-   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
-
-  0. This License applies to any program or other work which contains
-a notice placed by the copyright holder saying it may be distributed
-under the terms of this General Public License.  The "Program", below,
-refers to any such program or work, and a "work based on the Program"
-means either the Program or any derivative work under copyright law:
-that is to say, a work containing the Program or a portion of it,
-either verbatim or with modifications and/or translated into another
-language.  (Hereinafter, translation is included without limitation in
-the term "modification".)  Each licensee is addressed as "you".
-
-Activities other than copying, distribution and modification are not
-covered by this License; they are outside its scope.  The act of
-running the Program is not restricted, and the output from the Program
-is covered only if its contents constitute a work based on the
-Program (independent of having been made by running the Program).
-Whether that is true depends on what the Program does.
-
-  1. You may copy and distribute verbatim copies of the Program's
-source code as you receive it, in any medium, provided that you
-conspicuously and appropriately publish on each copy an appropriate
-copyright notice and disclaimer of warranty; keep intact all the
-notices that refer to this License and to the absence of any warranty;
-and give any other recipients of the Program a copy of this License
-along with the Program.
-
-You may charge a fee for the physical act of transferring a copy, and
-you may at your option offer warranty protection in exchange for a fee.
-
-  2. You may modify your copy or copies of the Program or any portion
-of it, thus forming a work based on the Program, and copy and
-distribute such modifications or work under the terms of Section 1
-above, provided that you also meet all of these conditions:
-
-    a) You must cause the modified files to carry prominent notices
-    stating that you changed the files and the date of any change.
-
-    b) You must cause any work that you distribute or publish, that in
-    whole or in part contains or is derived from the Program or any
-    part thereof, to be licensed as a whole at no charge to all third
-    parties under the terms of this License.
-
-    c) If the modified program normally reads commands interactively
-    when run, you must cause it, when started running for such
-    interactive use in the most ordinary way, to print or display an
-    announcement including an appropriate copyright notice and a
-    notice that there is no warranty (or else, saying that you provide
-    a warranty) and that users may redistribute the program under
-    these conditions, and telling the user how to view a copy of this
-    License.  (Exception: if the Program itself is interactive but
-    does not normally print such an announcement, your work based on
-    the Program is not required to print an announcement.)
-
-These requirements apply to the modified work as a whole.  If
-identifiable sections of that work are not derived from the Program,
-and can be reasonably considered independent and separate works in
-themselves, then this License, and its terms, do not apply to those
-sections when you distribute them as separate works.  But when you
-distribute the same sections as part of a whole which is a work based
-on the Program, the distribution of the whole must be on the terms of
-this License, whose permissions for other licensees extend to the
-entire whole, and thus to each and every part regardless of who wrote it.
-
-Thus, it is not the intent of this section to claim rights or contest
-your rights to work written entirely by you; rather, the intent is to
-exercise the right to control the distribution of derivative or
-collective works based on the Program.
-
-In addition, mere aggregation of another work not based on the Program
-with the Program (or with a work based on the Program) on a volume of
-a storage or distribution medium does not bring the other work under
-the scope of this License.
-
-  3. You may copy and distribute the Program (or a work based on it,
-under Section 2) in object code or executable form under the terms of
-Sections 1 and 2 above provided that you also do one of the following:
-
-    a) Accompany it with the complete corresponding machine-readable
-    source code, which must be distributed under the terms of Sections
-    1 and 2 above on a medium customarily used for software interchange; or,
-
-    b) Accompany it with a written offer, valid for at least three
-    years, to give any third party, for a charge no more than your
-    cost of physically performing source distribution, a complete
-    machine-readable copy of the corresponding source code, to be
-    distributed under the terms of Sections 1 and 2 above on a medium
-    customarily used for software interchange; or,
-
-    c) Accompany it with the information you received as to the offer
-    to distribute corresponding source code.  (This alternative is
-    allowed only for noncommercial distribution and only if you
-    received the program in object code or executable form with such
-    an offer, in accord with Subsection b above.)
-
-The source code for a work means the preferred form of the work for
-making modifications to it.  For an executable work, complete source
-code means all the source code for all modules it contains, plus any
-associated interface definition files, plus the scripts used to
-control compilation and installation of the executable.  However, as a
-special exception, the source code distributed need not include
-anything that is normally distributed (in either source or binary
-form) with the major components (compiler, kernel, and so on) of the
-operating system on which the executable runs, unless that component
-itself accompanies the executable.
-
-If distribution of executable or object code is made by offering
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-access to copy the source code from the same place counts as
-distribution of the source code, even though third parties are not
-compelled to copy the source along with the object code.
-
-  4. You may not copy, modify, sublicense, or distribute the Program
-except as expressly provided under this License.  Any attempt
-otherwise to copy, modify, sublicense or distribute the Program is
-void, and will automatically terminate your rights under this License.
-However, parties who have received copies, or rights, from you under
-this License will not have their licenses terminated so long as such
-parties remain in full compliance.
-
-  5. You are not required to accept this License, since you have not
-signed it.  However, nothing else grants you permission to modify or
-distribute the Program or its derivative works.  These actions are
-prohibited by law if you do not accept this License.  Therefore, by
-modifying or distributing the Program (or any work based on the
-Program), you indicate your acceptance of this License to do so, and
-all its terms and conditions for copying, distributing or modifying
-the Program or works based on it.
-
-  6. Each time you redistribute the Program (or any work based on the
-Program), the recipient automatically receives a license from the
-original licensor to copy, distribute or modify the Program subject to
-these terms and conditions.  You may not impose any further
-restrictions on the recipients' exercise of the rights granted herein.
-You are not responsible for enforcing compliance by third parties to
-this License.
-
-  7. If, as a consequence of a court judgment or allegation of patent
-infringement or for any other reason (not limited to patent issues),
-conditions are imposed on you (whether by court order, agreement or
-otherwise) that contradict the conditions of this License, they do not
-excuse you from the conditions of this License.  If you cannot
-distribute so as to satisfy simultaneously your obligations under this
-License and any other pertinent obligations, then as a consequence you
-may not distribute the Program at all.  For example, if a patent
-license would not permit royalty-free redistribution of the Program by
-all those who receive copies directly or indirectly through you, then
-the only way you could satisfy both it and this License would be to
-refrain entirely from distribution of the Program.
-
-If any portion of this section is held invalid or unenforceable under
-any particular circumstance, the balance of the section is intended to
-apply and the section as a whole is intended to apply in other
-circumstances.
-
-It is not the purpose of this section to induce you to infringe any
-patents or other property right claims or to contest validity of any
-such claims; this section has the sole purpose of protecting the
-integrity of the free software distribution system, which is
-implemented by public license practices.  Many people have made
-generous contributions to the wide range of software distributed
-through that system in reliance on consistent application of that
-system; it is up to the author/donor to decide if he or she is willing
-to distribute software through any other system and a licensee cannot
-impose that choice.
-
-This section is intended to make thoroughly clear what is believed to
-be a consequence of the rest of this License.
-
-  8. If the distribution and/or use of the Program is restricted in
-certain countries either by patents or by copyrighted interfaces, the
-original copyright holder who places the Program under this License
-may add an explicit geographical distribution limitation excluding
-those countries, so that distribution is permitted only in or among
-countries not thus excluded.  In such case, this License incorporates
-the limitation as if written in the body of this License.
-
-  9. The Free Software Foundation may publish revised and/or new versions
-of the General Public License from time to time.  Such new versions will
-be similar in spirit to the present version, but may differ in detail to
-address new problems or concerns.
-
-Each version is given a distinguishing version number.  If the Program
-specifies a version number of this License which applies to it and "any
-later version", you have the option of following the terms and conditions
-either of that version or of any later version published by the Free
-Software Foundation.  If the Program does not specify a version number of
-this License, you may choose any version ever published by the Free Software
-Foundation.
-
-  10. If you wish to incorporate parts of the Program into other free
-programs whose distribution conditions are different, write to the author
-to ask for permission.  For software which is copyrighted by the Free
-Software Foundation, write to the Free Software Foundation; we sometimes
-make exceptions for this.  Our decision will be guided by the two goals
-of preserving the free status of all derivatives of our free software and
-of promoting the sharing and reuse of software generally.
-
-                            NO WARRANTY
-
-  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
-FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
-OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
-PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
-OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
-TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
-PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
-REPAIR OR CORRECTION.
-
-  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
-REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
-INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
-OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
-TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
-YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
-PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES.
-
-                     END OF TERMS AND CONDITIONS
-
-            How to Apply These Terms to Your New Programs
-
-  If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
-  To do so, attach the following notices to the program.  It is safest
-to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
-    <one line to give the program's name and a brief idea of what it does.>
-    Copyright (C) <year>  <name of author>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License along
-    with this program; if not, write to the Free Software Foundation, Inc.,
-    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-
-Also add information on how to contact you by electronic and paper mail.
-
-If the program is interactive, make it output a short notice like this
-when it starts in an interactive mode:
-
-    Gnomovision version 69, Copyright (C) year name of author
-    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
-    This is free software, and you are welcome to redistribute it
-    under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License.  Of course, the commands you use may
-be called something other than `show w' and `show c'; they could even be
-mouse-clicks or menu items--whatever suits your program.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the program, if
-necessary.  Here is a sample; alter the names:
-
-  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
-  `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
-  <signature of Ty Coon>, 1 April 1989
-  Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs.  If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library.  If this is what you want to do, use the GNU Lesser General
-Public License instead of this License.

LICENSE.JFFS2

@@ -1,30 +0,0 @@
-The files in this directory and elsewhere which refer to this LICENCE
-file are part of JFFS2, the Journalling Flash File System v2.
-
-	Copyright © 2001-2007 Red Hat, Inc. and others
-
-JFFS2 is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2 or (at your option) any later 
-version.
-
-JFFS2 is distributed in the hope that it will be useful, but WITHOUT
-ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-for more details.
-
-You should have received a copy of the GNU General Public License along
-with JFFS2; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-
-As a special exception, if other files instantiate templates or use
-macros or inline functions from these files, or you compile these
-files and link them with other works to produce a work based on these
-files, these files do not by themselves cause the resulting work to be
-covered by the GNU General Public License. However the source code for
-these files must still be made available in accordance with section (3)
-of the GNU General Public License.
-
-This exception does not invalidate any other reasons why a work based on
-this file might be covered by the GNU General Public License.
-

LICENSE.NET

@@ -1,3 +1,7 @@
+#
+#  $Id$
+#
+
 The RTEMS TCP/IP stack is a port of the FreeBSD TCP/IP stack.  The following
 copyright and licensing information applies to this code.
 

LICENSE.RPCXDR

@@ -1,3 +1,7 @@
+#
+#  $Id$
+#
+
 The RTEMS RPC/XDR support is a port of the freely distributed
 Sun Microsystems implementation.  The following copyright and
 licensing information applies to this code.

LICENSE.WEBSERVER

@@ -0,0 +1,8 @@
+#
+#  $Id$
+#
+
+The source code in c/src/libnetworking/rtems_webserver is a port
+of the Go Ahead Software, Inc. WebServer.  Their copyright and 
+licensing terms apply.  See c/src/libnetworking/rtems_webserver/license.txt
+for details.

MAINTAINERS

@@ -1,65 +1,54 @@
+Note
+====
+
+This file contains information about people who are permitted to make
+changes to various parts of RTEMS and its associated components and
+add-ons.
+
+Please do not contact the people in this file directly to report
+problems with RTEMS.
+
+For general information about RTEMS, please visit:
+
+  http://www.rtems.com
+
+To report problems in RTEMS, please visit:
+
+  http://www.rtems.com/bugs.html
+
 Maintainers
 ===========
-This file contains information about people who are permitted to make
-changes to RTEMS and its associated components and add-ons.  Please do
-not contact the people in this file directly to report problems with RTEMS.
 
-For general information about RTEMS, please visit: http://www.rtems.org
+		Blanket Write Privileges (alphabetical order)
 
-To report problems in RTEMS, please visit: http://www.rtems.org/bugs.html
+Jennifer Averett				jennifer@oarcorp.com
+Ralf Corsepius					ralf.corsepius@rtems.org
+Chris Johns					chris.johns@rtems.com
+Eric Norum					eric.norum@rtems.com
+Joel Sherrill					joel.sherrill@oarcorp.com
 
-RTEMS is maintained by collection of volunteers.  RTEMS is a very
+		Various Component Maintainers
-broad and diverse project which requires expertise in many areas.
-This breadth of knowledge exceeds the capabilities of any
-single person. Each volunteer has areas of expertise where they
-are more comfortable but each is capable of making technical
-decisions across the entirety of RTEMS.
 
-Blanket Write Privileges are granted to experienced RTEMS developers
+Networking		NAME-TBD		EMAIL-TBD
-who can be trusted to distinguish between changes which require
-others to review, require a problem report, or can be safely committed
-with limited review.
 
-Write After Approval is granted to experienced but also trusted
+			CPU Port Maintainers	(CPU alphabetical order)
-RTEMS developers.  These developers may be less familiar with
-the breadth of RTEMS.  Developers with write after approval need
-to submit their patches for review.  Once the patches have been approved by a
-developer with Blanket Write Privileges, the patches may be checked in.
-A BSP-specific patch may be checked in three work days after sending it to
-devel@rtems.org in case nobody explicitly rejected the patch.
 
-Localized Write Permission is for developers who have primary
+arm			Jay Monkman		jtm@lopingdog.com
-responsibility for a port and all associated BSPs, a BSP, or other
+avr			Ralf Corsepius		ralf.corsepius@rtems.org
-specific aspects of RTEMS.  These folks are allowed to make changes to
+h8300			NAME-TBD		EMAIL-TBD
-areas they maintain and related documentation, web pages, and test cases
+i386			NAME-TBD		EMAIL-TBD
-without approval from anyone else, and approve other people's changes
+m68k			NAME-TBD		EMAIL-TBD
-in those areas. They must get approval for changes elsewhere in RTEMS.
+mips			NAME-TBD		EMAIL-TBD
+no_cpu			NAME-TBD		EMAIL-TBD
+or32			NAME-TBD		EMAIL-TBD
+powerpc			NAME-TBD		EMAIL-TBD
+sh			NAME-TBD		EMAIL-TBD
+sparc			NAME-TBD		EMAIL-TBD
+unix			NAME-TBD		EMAIL-TBD
 
-Blanket Write Privileges
+		    BSP Maintainers		(CPU/BSP alphabetical order)
-========================
-Jennifer Averett           jennifer.averett@OARcorp.com
-Thomas Doefler             Thomas.Doerfler@embedded-brains.de
-Sebastian Huber            sebastian.huber@embedded-brains.de
-Chris Johns                chrisj@rtems.org
-Joel Sherrill              joel.sherrill@OARcorp.com
-Gedare Bloom               gedare@rtems.org
 
-Write After Approval
+CPU/BSP			NAME-TBD		EMAIL-TBD
-====================
+arm/edb7312  		Jay Monkman		jtm@lopingdog.com
-Daniel Hellstrom           daniel@gaisler.com
+arm/gp32		Philippe Simons		loki_666@fastmail.fm
-Ben Gras                   beng@rtems.org
-Pavel Pisa                 ppisa@pikron.com
-Christian Mauderer         christian.mauderer@embedded-brains.de
-Hesham Almatary            heshamelmatary@gmail.com
-Amaan Cheval               amaan@rtems.org
-Vijay Kumar Banerjee       vijay@rtems.org
-
-Localized Write Permission
-==========================
-sparc                      Daniel Hellstrom (daniel@gaisler.com)
-beagle                     Ben Gras (beng@rtems.org)
-tms570                     Pavel Pisa (pisa@cmp.felk.cvut.cz)
-raspberrypi                Pavel Pisa (pisa@cmp.felk.cvut.cz)
-x86_64                     Amaan Cheval (amaan@rtems.org)
-beagle                     Vijay Kumar Banerjee (vijay@rtems.org)
 

Makefile.am

@@ -1,17 +1,23 @@
 #
 # top level directory for RTEMS build tree
 #
+##
+## $Id$
+##
 
 ACLOCAL_AMFLAGS = -I aclocal
 
-SUBDIRS = $(build_SUBDIRS) $(host_SUBDIRS) $(target_SUBDIRS)
+SUBDIRS = make $(build_SUBDIRS) $(host_SUBDIRS) $(target_SUBDIRS)
 DIST_SUBDIRS = $(SUBDIRS)
 
 noinst_SCRIPTS = bootstrap
 
+EXTRA_DIST = README.configure SUPPORT VERSION LICENSE $(noinst_SCRIPTS)
+EXTRA_DIST += config-ml.in
+EXTRA_DIST += ampolish3
 
 dist-hook:
-	@files=`(cd $(srcdir); find cpukit c testsuites \
+	@files=`(cd $(srcdir); find doc cpukit c testsuites tools \
 	   -name configure.ac -print | sed 's,/configure.ac,,' | sort)`; \
 	for i in $$files; do \
 	  if test -f $(distdir)/$$i/configure.ac; then : ; \
@@ -34,22 +40,5 @@ dist-hook:
 	  f=`echo $$a | sed 's,\.in$$,,'`; \
 	  if test -f $$f; then echo "rm $$f"; rm $$f; fi; done
 
-rtems_makedir = $(prefix)/make
-
-dist_rtems_make_DATA = 
-dist_rtems_make_DATA += make/main.cfg
-dist_rtems_make_DATA += make/leaf.cfg
-
-rtems_make_Templatesdir = $(pkgdatadir)/make/Templates
-
-dist_rtems_make_Templates_DATA =
-dist_rtems_make_Templates_DATA += make/Templates/Makefile.dir
-dist_rtems_make_Templates_DATA += make/Templates/Makefile.leaf
-dist_rtems_make_Templates_DATA += make/Templates/Makefile.lib
-
-rtems_make_customdir = $(rtems_makedir)/custom
-
-dist_rtems_make_custom_DATA = make/custom/default.cfg
-
 include $(top_srcdir)/automake/subdirs.am
 include $(top_srcdir)/automake/host.am

Makefile.maint

@@ -31,7 +31,7 @@ TAG_SUFFIX = -test1
 
 rtems_version := $(shell cat VERSION | sed -n '/.* Version /{s/^.*Version[ ]*\([0-9\.]\+\)/\1/p};')
 rtems_tag     := $(shell echo "rtems-$(rtems_version)" | tr . -)
-rtems_api     := 4.10
+rtems_api     := 4.9
 PATH          := /opt/rtems-$(rtems_api)/bin:$(PATH)
 
 # -----------------
@@ -54,6 +54,15 @@ rtems-$(rtems_version)/stamp.export.$(rtems_tag)$(TAG_SUFFIX):
 rtems-$(rtems_version)$(TAG_SUFFIX).tar.bz2: rtems-$(rtems_version)/stamp.autofiles \
 	  rtems-$(rtems_version)/excludes \
 	  rtems-$(rtems_version)/TOOL_VERSIONS
+	cd rtems-$(rtems_version) ; \
+	  touch doc/ada_user/ada_user.texi doc/bsp_howto/bsp_howto.texi \
+	    doc/cpu_supplement/cpu_supplement.texi \
+	    doc/develenv/develenv.texi doc/filesystem/filesystem.texi \
+	    doc/itron3.0/itron.texi doc/networking/networking.texi \
+	    doc/new_chapters/new_chapters.texi doc/porting/porting.texi \
+	    doc/posix1003.1/posix1003_1.texi doc/posix_users/posix_users.texi \
+	    doc/relnotes/relnotes.texi doc/started/started.texi \
+	    doc/user/c_user.texi
 	tar -cj -X rtems-$(rtems_version)/excludes \
 	  -f rtems-$(rtems_version)$(TAG_SUFFIX).tar.bz2 rtems-$(rtems_version)
 
@@ -122,23 +131,6 @@ new-revision:
 	  $(VERSION_FILES); \
 	sed -i -e "s,\(^RTEMS Version\).*,\1 $$version," VERSION
 
-# -----------------
-# Create a new branch
-# increments the 2nd digit of the version number
-# set the 3rd digit of the version number to 99
-# set the 4rd digit of the version number to 0
-# Example: 4.6.34.4 -> 4.7.99.0
-new-branch:
-	v=$$(echo $(rtems_version) | sed 's,^\([0-9]\+\).*,\1,'); \
-	r=$$(echo $(rtems_version) | sed 's,^[0-9]\+\.\([0-9]\+\).*,\1,'); \
-	r=$$(($$r + 1)); version="$$v.$$r.99.0"; \
-	api="$$v.$$(($$r + 1))"; \
-	echo "New branch release: $$version"; \
-	sed -i -e "s|\[_RTEMS_VERSION\],\[.*\]|\[_RTEMS_VERSION\],\[$$version\]|" \
-	  -e "s|\[_RTEMS_API\],\[.*\]|\[_RTEMS_API\],\[$$api\]|" \
-	  $(VERSION_FILES); \
-	sed -i -e "s,\(^RTEMS Version\).*,\1 $$version," VERSION
-
 VERSION_FILES += aclocal/version.m4
 VERSION_FILES += cpukit/aclocal/version.m4
 VERSION_FILES += c/src/aclocal/version.m4
@@ -150,4 +142,4 @@ commit:
 	$(CVS_RUN) commit -m "Upgrade to $(rtems_version)" \
 	  $(VERSION_FILES) VERSION
 
-.PHONY: commit new-minor new-revision new-branch tag tarball
+.PHONY: commit new-minor new-revision tag tarball

README

@@ -1,57 +1,97 @@
-Real-Time Executive for Multiprocessing Systems (RTEMS)
+#
--------------------------------------------------------
+#  $Id$
+#
 
-RTEMS, Real-Time Executive for Multiprocessor Systems, is a real-time executive
+Building RTEMS
-(kernel) which provides a high performance environment for embedded
+==============
-applications with the following features:
+See the file README.configure.
 
- - standards based user interfaces
+Directory Overview
- - multitasking capabilities
+==================
- - homogeneous and heterogeneous multiprocessor systems
- - event-driven, priority-based, preemptive scheduling
- - optional rate monotonic scheduling
- - intertask communication and synchronization
- - priority inheritance
- - responsive interrupt management
- - dynamic memory allocation
- - high level of user configurability
- - open source with a friendly user license
 
-Project git repositories are located at https://git.rtems.org/
+This is the top level of the RTEMS directory structure.  The following 
+is a description of the files and directories in this directory:
 
- RTEMS Kernel:        : https://git.rtems.org/rtems/
+  INSTALL
- RTEMS Source Builder : https://git.rtems.org/rtems-source-builder/
+    Rudimentary installation instructions.  For more detailed
- RTEMS Tools          : https://git.rtems.org/rtems-tools/
+    information please see the Release Notes.  The Postscript 
- RTEMS Documentation  : https://git.rtems.org/rtems-docs/
+    version of this manual can be found in the file
- RTEMS FreeBSD        : https://git.rtems.org/rtems-libbsd/
+    c_or_ada/doc/relnotes.tgz.
 
-Online documentation is available at https://docs.rtems.org/
+  LICENSE
+    Required legalese.
 
- RTEMS User Manual : https://docs.rtems.org/branches/master/user/index.html
+  README
- RTEMS RSB Manual  : https://docs.rtems.org/branches/master/rsb/index.html
+    This file.
- RTEMS Classic API : https://docs.rtems.org/branches/master/c-user/index.html
- RTEMS POSIX API   : https://docs.rtems.org/branches/master/posix-users/index.html
 
-RTEMS Doxygen for CPUKit : https://docs.rtems.org/doxygen/branches/master/
+  c
+    This directory contains the source code for the C 
+    implementation of RTEMS as well as the test suites, sample 
+    applications, Board Support Packages, Device Drivers, and 
+    support libraries.
 
-RTEMS POSIX 1003.1 Compliance Guide :
+  doc
- https://docs.rtems.org/branches/master/posix-compliance/index.html
+    This directory contains the PDL for the RTEMS executive.
 
- - Details the standards base functionality and profiles RTEMS supportsXo
+Ada versus C
+============
 
-RTEMS Developers Wiki : http://devel.rtems.org
+There are two implementations of RTEMS in this source tree -- 
+in Ada and in C.  These two implementations are functionally
+and structurally equivalent.  The C implementation follows
+the packaging conventions and hierarchical nature of the Ada 
+implementation.  In addition, a style has been followed which 
+allows one to easily find the corresponding Ada and C 
+implementations.  
 
- - Bug reporting, community knowledge and tutorials.
+File names in C and code placement was carefully designed to insure
+a close mapping to the Ada implementation.  The following file name 
+extensions are used:
 
-RTEMS Mailing Lists : https://lists.rtems.org/mailman/listinfo
+   .adb - Ada body
+   .ads - Ada specification
+   .adp - Ada body requiring preprocessing
+   .inc - include file for .adp files
 
- - The RTEMS Project maintains mailing lists which are used for most
+   .c   - C body (non-inlined routines)
-   discussions:
+   .inl - C body (inlined routines)
+   .h   - C specification
 
-   * For general-purpose questions related to using RTEMS, use the rtems-users
+In the executive source, XYZ.c and XYZ.inl correspond directly to a 
-     ml: https://lists.rtems.org/mailman/listinfo/users
+single XYZ.adb or XYZ.adp file.  A .h file corresponds directly to
+the .ads file.  There are only a handful of .inc files in the 
+Ada source and these are used to insure that the desired simple 
+inline textual expansion is performed.  This avoids scoping and
+calling convention side-effects in carefully constructed tests 
+which usually test context switch behavior.
 
-   * For questions and discussion related to development of RTEMS, use the
+In addition, in Ada code and data name references are always fully
-     rtems-devel ml: https://lists.rtems.org/mailman/listinfo/devel
+qualified as PACKAGE.NAME.  In C, this convention is followed 
+by having the package name as part of the name itself and using a
+capital letter to indicate the presence of a "." level.  So we have
+PACKAGE.NAME in Ada and _Package_Name in C.  The leading "_" in C
+is used to avoid naming conflicts between RTEMS and user variables.
+By using these conventions, one can easily compare the C and Ada
+implementations.
 
-The version number for this software is indicated in the VERSION file.
+The most noticeable difference between the C and Ada83 code is 
+the inability to easily obtain a "typed pointer" in Ada83.  
+Using the "&" operator in C yields a pointer with a specific type.
+The 'Address attribute is the closest feature in Ada83.  This
+returns a System.Address and this must be coerced via Unchecked_Conversion
+into an access type of the desired type.  It is easy to view 
+System.Address as similar to a "void *" in C, but this is not the case.
+A "void *" can be assigned to any other pointer type without an
+explicit conversion.  
+
+The solution adopted to this problem was to provide two routines for
+each access type in the Ada implementation -- one to convert from
+System.Address to the access type and another to go the opposite
+direction.  This results in code which accomplishes the same thing
+as the corresponding C but it is easier to get lost in the clutter
+of the apparent subprogram invocations than the "less bulky"
+C equivalent.
+
+A related difference is the types which are only in Ada which are used 
+for pointers to arrays.  These types do not exist and are not needed 
+in the C implementation.

README.cdn-X

@@ -0,0 +1,73 @@
+Building RTEMS Canadian Cross
+=============================
+
+RTEMS now contains experimental and yet incomplete support for building
+it Canadian Cross.
+
+1. Introduction
+---------------
+If you don't know what Canadian Cross Building means, you probably don't want
+to apply it and should consider stop reading here. 
+
+Interested readers might want to read Ian Lance Taylor's article at 
+http://www.airs.com/ian/configure for underlaying details and working 
+principles.
+
+
+2. RTEMS
+--------
+Example: Building RTEMS for sparc-rtems under i386-pc-linux-gnu to be hosted 
+on a i386-cygwin platform.
+
+2.1 Required tools
+------------------
+* A i386-pc-linux-gnu cross sparc-rtems toolchain.
+* A i386-pc-linux-gnu cross i386-cygwin toolchain.
+* A i386-pc-linux-gnu native toolchain.
+
+We further on assume these to be installed to these locations:
+/opt/rtems .. linux cross sparc-rtems toolchain
+/opt/cygwin .. linux cross i386-cygwin cross-toolchain
+/usr .. linux native toolchain and further tools. 
+
+2.2 Building sparc-rtems
+------------------------
+The first step is to build RTEMS for sparc-rtems under linux. 
+
+mkdir build
+cd build
+<path>/rtems/configure [options] \
+--target=sparc-rtems \
+--prefix=/opt/cygwin
+make
+make install
+
+This will build a standard sparc-rtems RTEMS and install it to the given 
+PREFIX.
+
+2.3 Building i386-cygwin host support
+-------------------------------------
+The next step is to build RTEMS host support for i386-cygwin.
+This basically means to cross-build the host tools contained in RTEMS.
+
+mkdir host
+cd host
+<path>/rtems/configure [options] \
+--target=sparc-rtems \
+--build=`<path>/rtems/config.guess` \
+--host=i386-cygwin \
+--prefix=/opt/cygwin
+make
+make install
+
+This will build RTEMS host-tools for i386-cygwin and install them to the given
+PREFIX.
+
+
+3. Known issues
+---------------
+
+* At present time, building RTEMS Canadian Cross is known to be immature, and
+to require additional work. Do not expect this to work.
+
+* The <toplevel>/make/ directory hierarchy is not treated correctly.

README.configure

@@ -0,0 +1,250 @@
+#
+#  $Id$
+#
+
+1. Autoconf support
+===================
+
+This version of RTEMS is configured with GNU autoconf. RTEMS can be
+configured and built either standalone or together with the compiler
+tools in the Cygnus one-tree structure. Using autoconf also means
+that RTEMS now can be built in a separate build directory.
+
+To re-generate auto*tool generated files (configure, Makefile.in etc),
+autoconf-2.59 and automake-1.8 are required.
+
+2. Installation
+===============
+
+2.1 Standalone build
+
+To configure RTEMS for a specific target, run configure in the build
+directory. In addition to the standard configure options, the following
+RTEMS-specific option are supported:
+
+      --disable-rtems-inlines
+      --disable-posix
+      --disable-itron
+      --disable-networking
+      --enable-cxx
+      --enable-bare-cpu-model=<MODEL>
+      --enable-bare-cpu-cflags=<FLAGS>
+      --enable-multiprocessing
+      --enable-rtemsbsp="bsp1 bsp2 ..."
+      --enable-tests
+      --enable-rdbg            (only valid for i386 and some PowerPC BSPs)
+      --enable-docs
+
+In addition, the following standard autoconf options are frequently
+used when configuring RTEMS installations:
+
+      --prefix=INSTALL_DIRECTORY
+
+By default, inline routines are used instead of macros where possible.
+Macros can be selected using the --disable-inlines option.  [NOTE:
+Some APIs may not support macro versions of their inline routines.]
+
+By default, the RTEMS POSIX 1003.1b interface is built for targets that support
+it. It can be disabled with the --disable-posix option.
+
+By default, the RTEMS uITRON interface is built for targets that support
+it. It can be disabled with the --disable-itron option.
+
+By default, the RTEMS networking support is built for targets which
+support it.  It can be specifically disabled for those targets
+with the --disable-networking option.
+
+By default, the RTEMS remote debugger server support is not built.
+It can be specifically enabled for the targets that support it.
+with the --enable-rdbg option. NB : the RTEMS networking support
+must be enabled to support the remote debugger server.
+
+By default, the RTEMS support of C++ is disabled.  It can be enabled
+with the --enable-cxx option. If the rtems++ C++ library is installed
+it will also be build.
+
+By default, the RTEMS test suites are NOT configured -- only the 
+sample tests are built.  --enable-tests will configure
+the RTEMS test suite. The default speeds up the build
+and configure process when the tests are not desired.
+
+By default, RTEMS is built using arguments and build rules which require a
+gcc supporting the -specs option, ie. a gcc >= 2.8.
+[The --disable-gcc28 option, which has been present in former releases, has
+been removed.]
+
+By default, multiprocessing is is not built.  It can be enabled
+for those BSPs supporting it by the --enable-multiprocessing option.
+
+By default, all bsps for a target are built. The bare BSP is not built
+unless directly specified. There are  two ways of changing this:
+
++ use the --enable-rtemsbsp option which will set the specified
+  bsps as the default bsps, or 
++ set the RTEMS_BSP variable during make (see below).
+
+The --enable-rtemsbsp= option configures RTEMS for a specific board
+within a target architecture.  Remember that the target specifies the
+CPU family while the BSP specifies the precise board you will be using. 
+The following targets are supported:
+
+      (none)	will build the host-based version on Linux, Solaris and HPUX.
+
+      arm-rtems4.9
+      h8300-rtems4.9
+      i386-rtems4.9
+      m68k-rtems4.9
+      mips-rtems4.9
+      no_cpu-rtems4.9
+      powerpc-rtems4.9
+      sh-rtems4.9
+      sparc-rtems4.9
+      bare                    see notes
+
+The cross-compiler is set to $(target)-gcc by default. This can be
+overridden by:
+
++ using the --program-prefix option to configure to specify the
+  string which will prepended to the tool names.  Be sure to include
+  a trailing "-".  For example, to use a m68k-coff toolset, use the
+  --program-prefix=m68k-coff- option.
+
+To build, run make in the build directory. To specify which bsps to build,
+add the RTEMS_BSP="bsp1 bsp2 .." to the make command.  Specifying multiple
+BSPs to build only works from the top level build directory.
+
+Installation is done under $(prefix)/rtems.
+
+As an example, to build and install the mvme136 and mvme162 bsps for m68k do:
+
+      (path_to_rtems_src)/configure --target=m68k-rtems
+
+      make RTEMS_BSP="mvme136 mvme162"
+      
+      make install RTEMS_BSP="mvme136 mvme162"
+
+The sample tests are built by 'make all' when configured with
+--enable-tests=samples.  Use --enable-tests=all to build the full
+test suite.
+
+Documentation is built separately from the source code.
+
+2.2 Target Dependent Notes
+
+bare:
+
+1.  See the README in the bare bsp source directory. This should
+    contain all info you need.
+2.  The bare bsp source contains a script to show how to build it.
+3.  The configure flags must be used to get the bare bsp to work.
+    The --enable-bare-cpu-model and --enable-bare-cpu-cflags are the
+    only pieces of information. The module is usually a gcc module
+    such as m68302 or mcpu32. The flags are passed directly to gcc.
+    Use "" if more than one option is specified.
+
+3. To use the installed RTEMS library
+=====================================
+
+To use the installed RTEMS bsps to build applications, the application
+makefile has to include a bsp-specific makefile that will define the
+RTEMS variables necessary to find include files and libraries. The
+bsp-specific makefile is installed at 
+
+      $(RTEMS_MAKEFILE_PATH)/Makefile.inc
+
+For the erc32 bsp installed at /usr/local/cross, the environment
+variable RTEMS_MAKEFILE_PATH would be set as follows to the
+following:
+
+/usr/local/cross/sparc-rtems/rtems/erc32/Makefile.inc
+
+4. Supported target bsps
+========================
+
+The following bsps are supported:
+
+host-based	: posix (on Linux, FreeBSD, Cygwin, Solaris, and HPUX)
+
+arm             : csb336 csb337 edb7312 gba gp32 nds rtl22x rtl22xx_t
+                  smdk2410
+
+avr:            : none
+
+bfin            : eZKit533 bf537Stamp
+
+h8300           : h8sim
+
+i386		: i386ex pc386 pc386dx pc486 pc586 pc686 pck6 ts_386ex
+		NOTE: The "pc386" BSP can be compiled to support a 
+		      variety of PC configurations including PC-104
+		      based solutions.
+
+m68k		: av5282 csb360 gen68302 gen68360 gen68360_040 
+		genmcf548x idp mcf5206elite mcf52235 mcf5235 mcf5239
+		m5484FireEngine mrm332 mvme136 mvme147s mvme162 mvme162lx
+		mvme167 ods68302 pgh360 sim68000 simcpu32 uC5282 
+
+no_cpu          : no_bsp  (porting example)
+
+mips            : csb350 genmongoosev hurricane jmr3904 rbtx4925 rbtx4938
+		p4600 p4650
+
+powerpc		: brs5l ep1a gen5200 gen83xx haleakala hsc_cm01 icecube
+		mbx821_001 mbx821_002 mbx821_002b mbx860_001b mbx860_002
+		mbx860_005b mcp750 mvme2100 mvme2307 mtx603e
+		mvme5500 mpc55xxevb mpc8260ads mpc8313erdb mpc8349eamds 
+		pghplus pm520_cr825 pm520_ze30 psim score603e ss555
+		tqm8xx_stk8xx virtex
+
+                  NOTE: The "motorola_powerpc" BSP is a single BSP which
+                  can be conditionally compiled to support most Motorola
+                  VMEbus, CompactPCI, and MTX boards.)
+
+                  NOTE: The mbx8xx, gen5200, gen83xx, and tqm8xx BSPs are
+		  designed to handle a variety of boards based on the same
+		  family of system on chips CPUs
+
+sh              : gensh1 gensh2 gensh4 shsim simsh4 simsh7045
+
+sparc 		: erc32 sis leon2 leon3
+
+any             : bare
+
+The following ports were considered obsoleted after the 4.6 releases
+and were removed: a29k, hppa, i960, mips64orion, and or32.
+
+
+5. Makefile structure
+=====================
+
+The makefiles have been re-organized. Most gnu-based bsps now use three
+main makefiles:
+    + custom/default.cfg,
+    + custom/bsp.cfg and
+    + compilers/gcc-target-default.cfg.
+
+Default.cfg sets the default values of certain common build options.
+
+Bsp.cfg set bsp-specific build options and can also override the
+default settings.
+
+Gcc-target-default.cfg contains the common gcc definitions.
+
+6. Adding a bsp
+===============
+
+Please refer to the BSP and Device Driver Guide.
+
+
+7. Tested configurations
+========================
+
+All BSPs have been built on GNU/Linux if the target architecture
+is supported in the FSF tools distribution. 
+
+8. Prerequisites
+================
+
+GNU make
+Bash.
+binutils, gcc, newlib and gdb versions matching those in the RPMs.

SUPPORT

@@ -0,0 +1,22 @@
+#
+#  $Id$
+#
+
+On-Line Applications Research Corporation (OAR) offers support,
+customization, and training for RTEMS.  Custom RTEMS development services
+includes porting RTEMS to new processors and the development of custom board
+support packages and device drivers.   In addition, OAR is available
+to assist in the development of your real-time embedded application.
+
+For more information, email Joel Sherrill joel.sherrill@OARcorp.com 
+or contact OAR at:
+
+On-Line Applications Research Corporation
+7047 Old Madison Pike Suite 320
+Huntsville AL 35806
+Voice: (205) 722-9985
+Fax:   (205 722-0985
+
+RTEMS maintenance and development is funded solely by RTEMS users.  
+The future of RTEMS depends on its user base.
+

VERSION

@@ -0,0 +1,7 @@
+#
+#  This file is automatically generated -- DO NOT EDIT!!!
+#
+#  $Id$
+#
+
+RTEMS Version 4.9.6

aclocal/bsp-alias.m4

@@ -1,16 +1,47 @@
+dnl
+dnl  $Id$
+dnl 
+
 dnl _RTEMS_BSP_ALIAS(BSP_ALIAS,RTEMS_BSP_FAMILY)
 dnl Internal subroutine to RTEMS_BSP_ALIAS
-AC_DEFUN([_RTEMS_BSP_ALIAS],[
+AC_DEFUN([_RTEMS_BSP_ALIAS],
-AC_REQUIRE([RTEMS_CANONICAL_TARGET_CPU])
+[# account for "aliased" bsps which share source code
-AC_REQUIRE([RTEMS_SOURCE_TOP])
+  case $1 in
-# account for "aliased" bsps which share source code
+    bare*)        $2=bare             ;; # EXP: bare-aliases
-      for bsp_cfgs in `ls "${RTEMS_SOURCE_ROOT}/bsps/${RTEMS_CPU}"/*/"config/$1.cfg" 2>/dev/null`; do
+
-        $2=`echo "$bsp_cfgs" | sed \
+    gen68360_040) $2=gen68360         ;; # m68k - 68360 in companion mode
-          -e "s,^${RTEMS_SOURCE_ROOT}/bsps/$RTEMS_CPU/,," \
+    pghplus)      $2=tqm8xx           ;; # powerpc - mpc8xx custom board
-          -e "s,/config/.*\.cfg$,,"`
+    tqm8xx_stk8xx) $2=tqm8xx          ;; # powerpc - tqm8xx on starter kit
-        break
+    pgh360)       $2=gen68360         ;; # m68k - 68360 custom board
-      done
+    m5484FireEngine) $2=genmcf548x    ;; # m68k - mcf548x eva board
-])
+    mbx8*)        $2=mbx8xx           ;; # MBX821/MBX860 board
+    mcp750)       $2=motorola_powerpc ;; # Motorola PPC board variant
+    mtx603e)      $2=motorola_powerpc ;; # Motorola PPC board variant
+    mvme162lx)    $2=mvme162          ;; # m68k - mvme162 board variant
+    mvme2100)     $2=motorola_powerpc ;; # Motorola PPC board variant
+    mvme2307)     $2=motorola_powerpc ;; # Motorola PPC board variant
+    p4600)        $2=p4000            ;; # mips - p4000 board w/IDT 4600
+    p4650)        $2=p4000            ;; # mips - p4000 board w/IDT 4650
+    pc386dx)      $2=pc386            ;; # i386 - PC w/o FPU
+    pc486)        $2=pc386            ;; # i386 - PC with i486DX
+    pc586)        $2=pc386            ;; # i386 - PC with Pentium
+    pc686)        $2=pc386            ;; # i386 - PC with PentiumPro
+    pck6)         $2=pc386            ;; # i386 - PC with K6
+    brs5l*)       $2=gen5200          ;; # MPC5200 based board
+    pm520*)       $2=gen5200          ;; # MPC5200 based board
+    icecube)      $2=gen5200          ;; # MPC5200 based board - LITE5200B
+    mpc55??evb)   $2=mpc55xxevb       ;; # MPC5566EVB based board
+    mpc8349eamds) $2=gen83xx          ;; # MPC8349 based board
+    hsc_cm01)     $2=gen83xx          ;; # MPC8349 based board
+    mpc8313erdb)  $2=gen83xx          ;; # MPC83XX based board
+    rtl22xx_t)    $2=rtl22xx          ;; # rtl22xx bsp in thumb mode
+    simcpu32)     $2=sim68000         ;; # BSVC CPU32 variant
+    simsh7032)    $2=shsim            ;; # SH7032 simulator
+    simsh7045)    $2=shsim            ;; # SH7045 simulator
+    sis)          $2=erc32            ;; # erc32 SIS simulator
+    *)            $2=$1;;
+  esac]
+)
 
 dnl RTEMS_BSP_ALIAS(BSP_ALIAS,RTEMS_BSP_FAMILY)
 dnl convert a bsp alias $1 into its bsp directory RTEMS_BSP_FAMILY

aclocal/canonical-target-name.m4

@@ -1,5 +1,9 @@
+dnl
+dnl $Id$
+dnl
+
 dnl canonicalize target cpu
-dnl NOTE: Most rtems targets do not fulfil autoconf's
+dnl NOTE: Most rtems targets do not fullfil autoconf's
 dnl target naming conventions "processor-vendor-os"
 dnl Therefore autoconf's AC_CANONICAL_TARGET will fail for them
 dnl and we have to fix it for rtems ourselves 
@@ -9,13 +13,23 @@ AC_DEFUN([RTEMS_CANONICAL_TARGET_CPU],
 AC_CANONICAL_TARGET
 AC_MSG_CHECKING(rtems target cpu)
 case "${target}" in
+  # hpux unix port should go here
+  i[[34567]]86-*linux*)		# unix "simulator" port
+	RTEMS_CPU=unix
+	;;
+  i[[34567]]86-*freebsd*) 	# unix "simulator" port
+	RTEMS_CPU=unix
+	;;
+  i[[34567]]86-pc-cygwin*) 	# Cygwin is just enough unix like :)
+	RTEMS_CPU=unix
+	;;
   no_cpu-*rtems*)
         RTEMS_CPU=no_cpu
 	;;
-  riscv*-*rtems*)
+  sparc-sun-solaris*)           # unix "simulator" port
-        RTEMS_CPU=riscv
+	RTEMS_CPU=unix
 	;;
-  *)
+  *) 
 	RTEMS_CPU=`echo $target | sed 's%^\([[^-]]*\)-\(.*\)$%\1%'`
 	;;
 esac

aclocal/check-bsps.m4

@@ -1,23 +1,43 @@
+dnl $Id$
+
 dnl Report all available bsps for a target within the source tree
 dnl
 dnl RTEMS_CHECK_BSPS(bsp_list)
 AC_DEFUN([RTEMS_CHECK_BSPS],
 [
 AC_REQUIRE([RTEMS_CANONICAL_TARGET_CPU])dnl sets RTEMS_CPU, target
-AC_REQUIRE([RTEMS_SOURCE_TOP])dnl sets RTEMS_SOURCE_ROOT
+AC_REQUIRE([RTEMS_TOP])dnl sets RTEMS_TOPdir
 
 AC_MSG_CHECKING([for available BSPs])
   $1=
-  for bsp_make in `echo "${RTEMS_SOURCE_ROOT}/bsps/${RTEMS_CPU}"/*/config 2>/dev/null`; do
+  for bsp_spec in `ls "$srcdir/$RTEMS_TOPdir/c/src/lib/libbsp/$RTEMS_CPU"/*/bsp_specs 2>/dev/null`; do
-    bsp_family=`echo "$bsp_make" | sed \
+    bsp_family=`echo "$bsp_spec" | sed \
-      -e "s,^${RTEMS_SOURCE_ROOT}/bsps/${RTEMS_CPU}/,," \
+        -e "s,^$srcdir/$RTEMS_TOPdir/c/src/lib/libbsp/$RTEMS_CPU/,," \
-      -e "s,/config$,,"`
+        -e "s,/bsp_specs$,,"`
-    for bsp_cfgs in `ls "${RTEMS_SOURCE_ROOT}/bsps/${RTEMS_CPU}/$bsp_family/config/"*.cfg 2>/dev/null`; do
+    case $bsp_family in
-      bsp_cfg=`echo "$bsp_cfgs" | sed \
+        # Now account for BSPs with build variants
-        -e "s,^${RTEMS_SOURCE_ROOT}/bsps/${RTEMS_CPU}/$bsp_family/config/,," \
+          gen68360)          bsps="gen68360 gen68360_040 pgh360";;
-        -e "s,\.cfg$,,"`
+          tqm8xx)            bsps="pghplus tqm8xx_stk8xx";;
-      $1="[$]$1 $bsp_cfg"
+          genmcf548x)        bsps="m5484FireEngine";;
-    done
+          p4000)             bsps="p4600 p4650";;
+          mvme162)           bsps="mvme162 mvme162lx";;
+          mbx8xx)            bsps="mbx821_001 mbx860_001b"
+                             bsps="$bsps mbx821_002 mbx821_002b"
+                             bsps="$bsps mbx860_002"
+                             bsps="$bsps mbx860_005b"
+                             ;;
+          gen5200)           bsps="pm520_cr825 pm520_ze30 brs5l icecube";;
+          mpc55xxevb)        bsps="mpc5566evb";;
+          gen83xx)           bsps="mpc8349eamds hsc_cm01 mpc8313erdb";;
+	  motorola_powerpc)  bsps="mvme2307 mcp750 mtx603e mvme2100";;
+	  pc386)             bsps="pc386 pc386dx pc486 pc586 pc686 pck6";;
+          erc32)             bsps="erc32 sis";;
+          rtl22xx)           bsps="rtl22xx rtl22xx_t)";;
+	  sim68000)          bsps="sim68000 simcpu32";;
+	  shsim)             bsps="simsh7032 simsh7045";;
+	  *) 		     bsps="$bsp_family";;
+    esac;
+    $1="[$]$1 $bsps"
   done
   AS_IF([test -z "[$]$1"],
     [AC_MSG_RESULT([none])],

aclocal/check-custom-bsp.m4

@@ -1,20 +1,24 @@
+dnl $Id$
+
 AC_DEFUN([_RTEMS_CHECK_CUSTOM_BSP],[
 AC_REQUIRE([RTEMS_CANONICAL_TARGET_CPU])dnl sets RTEMS_CPU, target
-AC_REQUIRE([RTEMS_SOURCE_TOP])dnl sets RTEMS_SOURCE_ROOT
+AC_REQUIRE([RTEMS_TOP])dnl sets RTEMS_TOPdir
   $2=
-  for i in \
+  AC_MSG_CHECKING([for $1])
-    `ls "${RTEMS_SOURCE_ROOT}/bsps/${RTEMS_CPU}"/*/config/$1 2>/dev/null`;
+  for i in "${srcdir}/${RTEMS_TOPdir}/bspkit/${RTEMS_CPU}"/*/cfg/"$1" \
+    "${srcdir}/${RTEMS_TOPdir}/make/custom/$1";
   do
     AS_IF([test -r $i],[
       $2="$i"
       break;
     ])
   done
+  AS_IF([test -n "[$]$2"],
+    [AC_MSG_RESULT([[$]$2])],
+    [AC_MSG_RESULT([no])])
 ])
 
 AC_DEFUN([RTEMS_CHECK_CUSTOM_BSP],[
+  AC_REQUIRE([RTEMS_TOP])
   _RTEMS_CHECK_CUSTOM_BSP([[$]$1.cfg],[BSP_FOUND])
-  AS_IF([test -z "$BSP_FOUND"],[
-    AC_MSG_ERROR([missing [$]$1.cfg])
-  ])
 ])

aclocal/check-tool.m4

@@ -1,9 +0,0 @@
-## Check for a cross tool, similar to AC_CHECK_TOOL, but do not fall back to
-## the un-prefixed version of PROG-TO-CHECK-FOR.
-dnl RTEMS_CHECK_TOOL(VARIABLE, PROG-TO-CHECK-FOR[, VALUE-IF-NOT-FOUND [, PATH]])
-AC_DEFUN([RTEMS_CHECK_TOOL],
-[
-  AS_IF([test "x$target_alias" != "x$host_alias"],
-    [rtems_tool_prefix=$target_alias-])
-  AC_CHECK_PROG($1, ${rtems_tool_prefix}$2, ${rtems_tool_prefix}$2, $3, $4)
-])

aclocal/enable-cxx.m4

@@ -1,11 +1,13 @@
+dnl $Id$
+
 AC_DEFUN([RTEMS_ENABLE_CXX],
 [
 AC_ARG_ENABLE(cxx,
 [AS_HELP_STRING([--enable-cxx],
-[enable C++ support])],
+[enable C++ support and build the rtems++ library])],
 [case "${enable_cxx}" in
   yes) RTEMS_HAS_CPLUSPLUS=yes ;;
   no) RTEMS_HAS_CPLUSPLUS=no   ;;
   *)  AC_MSG_ERROR(bad value ${enableval} for enable-cxx option) ;;
-esac], [RTEMS_HAS_CPLUSPLUS=yes])
+esac], [RTEMS_HAS_CPLUSPLUS=no])
 ])

aclocal/enable-drvmgr.m4

@@ -1,12 +0,0 @@
-AC_DEFUN([RTEMS_ENABLE_DRVMGR],
-[
-## AC_BEFORE([$0], [RTEMS_CHECK_DRVMGR_STARTUP])dnl
-
-AC_ARG_ENABLE(drvmgr,
-[AS_HELP_STRING([--enable-drvmgr],[enable Driver Manager at Startup])],
-[case "${enableval}" in 
-  yes) RTEMS_DRVMGR_STARTUP=yes ;;
-  no) RTEMS_DRVMGR_STARTUP=no ;;
-  *)  AC_MSG_ERROR(bad value ${enableval} for enable-drvmgr option) ;;
-esac],[RTEMS_DRVMGR_STARTUP=yes]) 
-])

aclocal/enable-itron.m4

@@ -0,0 +1,14 @@
+dnl $Id$
+
+AC_DEFUN([RTEMS_ENABLE_ITRON],
+[
+## AC_BEFORE([$0], [RTEMS_CHECK_ITRON_API])dnl
+
+AC_ARG_ENABLE(itron,
+[AS_HELP_STRING([--enable-itron],[enable itron interface])],
+[case "${enableval}" in 
+  yes) RTEMS_HAS_ITRON_API=yes ;;
+  no) RTEMS_HAS_ITRON_API=no ;;
+  *)  AC_MSG_ERROR(bad value ${enableval} for enable-itron option) ;;
+esac],[RTEMS_HAS_ITRON_API=yes]) 
+])

aclocal/enable-multiprocessing.m4

@@ -1,13 +1,12 @@
+dnl $Id$
+
 AC_DEFUN([RTEMS_ENABLE_MULTIPROCESSING],
 [
 AC_ARG_ENABLE(multiprocessing,
 [AS_HELP_STRING([--enable-multiprocessing],
-[enable multiprocessing interface; the multiprocessing interface is a
+[enable multiprocessing interface])],
-communication interface between different RTEMS instances and allows
+[case "${enable_multiprocessing}" in 
-synchronization of objects via message passing])],
+  yes) ;;
-[case "${enable_multiprocessing}" in
-  yes) test -z $enable_rtemsbsp && AC_MSG_ERROR([Multiprocessing requires BSPs to be provided, none have, see --enable-rtemsbsp])
-       ;;
   no) ;;
   *)  AC_MSG_ERROR(bad value ${enableval} for enable-multiprocessing option) ;;
 esac],[enable_multiprocessing=no])

aclocal/enable-networking.m4

@@ -1,3 +1,5 @@
+dnl $Id$
+
 AC_DEFUN([RTEMS_ENABLE_NETWORKING],
 [
 ## AC_BEFORE([$0], [RTEMS_CHECK_NETWORKING])dnl

aclocal/enable-paravirt.m4

@@ -1,13 +0,0 @@
-AC_DEFUN([RTEMS_ENABLE_PARAVIRT],
-[
-
-AC_ARG_ENABLE(paravirt,
-[AS_HELP_STRING([--enable-paravirt],[enable support for paravirtualization
-(default=no)])],
-
-[case "${enableval}" in 
-  yes) RTEMS_HAS_PARAVIRT=yes ;;
-  no) RTEMS_HAS_PARAVIRT=no ;;
-  *)  AC_MSG_ERROR(bad value ${enableval} for enable-paravirt option) ;;
-esac],[RTEMS_HAS_PARAVIRT=no]) 
-])

aclocal/enable-posix.m4

@@ -1,3 +1,5 @@
+dnl $Id$
+
 AC_DEFUN([RTEMS_ENABLE_POSIX],
 [
 ## AC_BEFORE([$0], [RTEMS_CHECK_POSIX_API])dnl
@@ -11,9 +13,19 @@ AC_ARG_ENABLE(posix,
 esac],[RTEMS_HAS_POSIX_API=yes]) 
 
 case "${host}" in
+  # hpux unix port should go here
+  i[[34567]]86-pc-linux*)         # unix "simulator" port
+	RTEMS_HAS_POSIX_API=no
+	;;
+  i[[34567]]86-*freebsd*) # unix "simulator" port
+	RTEMS_HAS_POSIX_API=no
+	;;
   no_cpu-*rtems*)
 	RTEMS_HAS_POSIX_API=no
 	;;
+  sparc-sun-solaris*)             # unix "simulator" port
+	RTEMS_HAS_POSIX_API=no
+	;;
   *) 
 	;;
 esac

aclocal/enable-rtems-debug.m4

@@ -1,3 +1,5 @@
+## $Id$
+
 AC_DEFUN([RTEMS_ENABLE_RTEMS_DEBUG],
 [
 AC_ARG_ENABLE(rtems-debug,

aclocal/enable-rtemsbsp.m4

@@ -1,3 +1,5 @@
+dnl $Id$
+
 dnl Override the set of BSPs to be built.
 dnl used by the toplevel configure script
 dnl RTEMS_ENABLE_RTEMSBSP(rtems_bsp_list)
@@ -6,49 +8,10 @@ AC_DEFUN([RTEMS_ENABLE_RTEMSBSP],
 AC_BEFORE([$0], [RTEMS_ENV_RTEMSBSP])
 AC_ARG_ENABLE(rtemsbsp,
 [AS_HELP_STRING([--enable-rtemsbsp="bsp1 bsp2 .."],
-[BSPs to include in build, required for SMP and MP builds])],
+[BSPs to include in build])],
 [case "${enable_rtemsbsp}" in
   yes ) enable_rtemsbsp="" ;;
   no ) enable_rtemsbsp="no" ;;
-  *) enable_rtemsbsp="$enable_rtemsbsp"
+  *) enable_rtemsbsp="$enable_rtemsbsp" ;;
-     srctop=${srcdir}
-     while test x${srctop} != x/
-     do
-       if test -d ${srctop}/cpukit -a -d ${srctop}/c/src/lib/libbsp; then
-         break
-       fi
-       srctop=$(dirname ${srctop})
-     done
-     if test x${srctop} = x/; then
-       AC_MSG_ERROR([Cannot find the top of source tree, please report to devel@rtems.org])
-     fi
-     target_arch=$(echo ${target_alias} | sed -e "s/\-.*//g")
-     libbsp=${srctop}/bsps
-     libbsp_e=$(echo ${libbsp} | sed -e 's/\//\\\//g')
-     cfg_list=$(LANG=C LC_COLLATE=C find ${libbsp} -mindepth 1 -name \*.cfg)
-     for bsp in ${enable_rtemsbsp};
-     do
-       found=no
-       for bsp_path in ${cfg_list};
-       do
-         cfg_bsp=$(echo ${bsp_path} | sed -e "s/.*\///" -e 's/\.cfg//')
-         if test x$bsp = x$cfg_bsp; then
-           cfg_arch=$(echo ${bsp_path} | sed -e "s/${libbsp_e}*\///" -e 's/\/.*//')
-           case ${target_arch} in
-             ${cfg_arch}* )
-               ;;
-             * )
-               AC_MSG_ERROR([BSP '$bsp' architecture does not match the --target architecture, run 'rtems-bsps' (in the top of the source tree) for a valid BSP list])
-               ;;
-           esac
-           found=yes
-           break
-         fi
-       done
-       if test $found = no; then
-         AC_MSG_ERROR([BSP '$bsp' not found, run 'rtems-bsps' (in the top of the source tree) for a valid BSP list])
-       fi
-     done
-     ;;
 esac],[enable_rtemsbsp=""])
 ])

aclocal/enable-smp.m4

@@ -1,18 +0,0 @@
-AC_DEFUN([RTEMS_ENABLE_SMP],
-[
-## AC_BEFORE([$0], [RTEMS_CHECK_SMP])dnl
-
-AC_ARG_ENABLE(smp,
-[AS_HELP_STRING([--enable-smp],[enable support for symmetric multiprocessing
-(SMP)])],
-[case "${enableval}" in
-  yes) test -z $enable_rtemsbsp && AC_MSG_ERROR([SMP requires BSPs to be provided, none have, see --enable-rtemsbsp])
-       case "${RTEMS_CPU}" in
-         arm|powerpc|riscv*|sparc|i386) RTEMS_HAS_SMP=yes ;;
-         *)          RTEMS_HAS_SMP=no ;;
-       esac
-       ;;
-  no) RTEMS_HAS_SMP=no ;;
-  *)  AC_MSG_ERROR(bad value ${enableval} for enable-smp option) ;;
-esac],[RTEMS_HAS_SMP=no])
-])

aclocal/enable-tests.m4

@@ -1,3 +1,5 @@
+dnl $Id$
+
 AC_DEFUN([RTEMS_ENABLE_TESTS],
 [
 AC_ARG_ENABLE(tests,

aclocal/path-ksh.m4

@@ -1,3 +1,5 @@
+dnl $Id$
+
 AC_DEFUN([RTEMS_PATH_KSH],
 [
 dnl NOTE: prefer bash over ksh over sh

aclocal/project-root.m4

@@ -1,17 +1,22 @@
+dnl
+dnl $Id$
+dnl 
+
 dnl
 dnl PROJECT_TOPdir     .. relative path to the top of the build-tree
 dnl PROJECT_ROOT       .. relative path to the top of the temporary
 dnl                       installation directory inside the build-tree
-dnl RTEMS_TOPdir       .. relative path of a subpackage's configure.ac to the
+dnl RTEMS_TOPdir       .. relative path of a subpackage's configure.in to the
-dnl                       toplevel configure.ac of the source-tree
+dnl                       toplevel configure.in of the source-tree
 dnl RTEMS_ROOT         .. path to the top of a bsp's build directory
-dnl                       [Applied by custom/*.cfg, deprecated otherwise]
+dnl                       [Applied by custom/*.cfg, depredicated otherwise]
 dnl
 
 AC_DEFUN([RTEMS_PROJECT_ROOT],
 [dnl
 AC_REQUIRE([RTEMS_TOP])
-BIN2C=rtems-bin2c
+
-AC_SUBST(BIN2C)
+PACKHEX="\$(PROJECT_TOPdir)/tools/build/packhex"
+AC_SUBST(PACKHEX)
 ])
 

aclocal/rpm.m4

@@ -2,19 +2,19 @@ AC_DEFUN([RTEMS_ENABLE_RPMPREFIX],[
 AC_ARG_ENABLE([rpmprefix],
 [  --enable-rpmprefix=<rpmprefix>      prefix rpms],
 [case $enable_rpmprefix in
-yes ) rpmprefix="rtems-"]_RTEMS_API["-";;
+yes ) rpmprefix="rtems-"]RTEMS_API["-";;
 no ) rpmprefix="%{nil}";;
 * ) AS_IF([test -z "$enable_rpmprefix"],
       [rpmprefix="%{nil}"],
       [rpmprefix="$enable_rpmprefix"]);;
 esac],
-[rpmprefix="rtems-"]_RTEMS_API["-"])
+[rpmprefix="rtems-"]RTEMS_API["-"])
 
 AC_ARG_ENABLE([osversions],
 [  --enable-osversions       whether to use version numbers in os-tripples],
 [case $enable_osversions in
-yes ) osversion=_RTEMS_API;;
+yes ) osversion=RTEMS_API;;
 * ) osversion=;;
 esac],
-[osversion=_RTEMS_API])
+[osversion=RTEMS_API])
 ])

aclocal/rtems-bsp-includes.m4

@@ -1,13 +0,0 @@
-dnl
-dnl RTEMS Include paths.
-dnl
-AC_DEFUN([RTEMS_BSP_INCLUDES],
-[
-AC_REQUIRE([RTEMS_SOURCE_TOP])
-AC_REQUIRE([RTEMS_BUILD_TOP])
-RTEMS_BSP_CPPFLAGS="-I${RTEMS_BUILD_ROOT}/lib/libbsp/\$(RTEMS_CPU)/\$(RTEMS_BSP_FAMILY)/include \
--I${RTEMS_SOURCE_ROOT}/bsps/include \
--I${RTEMS_SOURCE_ROOT}/bsps/\$(RTEMS_CPU)/include \
--I${RTEMS_SOURCE_ROOT}/bsps/\$(RTEMS_CPU)/\$(RTEMS_BSP_FAMILY)/include"
-AC_SUBST([RTEMS_BSP_CPPFLAGS])
-])

aclocal/rtems-build-top.m4

@@ -1,12 +0,0 @@
-dnl
-dnl RTEMS_BUILD_TOP($1)
-dnl
-AC_DEFUN([RTEMS_BUILD_TOP],
-[dnl
-#
-# This is a copy of the horrible hack in rtems-top.m4 and it is simpler to
-# copy it than attempt to clean this crap up.
-#
-RTEMS_BUILD_ROOT="${with_rtems_build_top}"
-AC_SUBST([RTEMS_BUILD_ROOT])
-])dnl

aclocal/rtems-includes.m4

@@ -1,23 +0,0 @@
-dnl
-dnl RTEMS Include paths.
-dnl
-AC_DEFUN([RTEMS_INCLUDES],
-[
-AC_REQUIRE([RTEMS_SOURCE_TOP])
-AC_REQUIRE([RTEMS_BUILD_TOP])
-
-# Was CFLAGS set?
-rtems_cv_CFLAGS_set="${CFLAGS+set}"
-
-RTEMS_INCLUDE_CPUKIT="-I${RTEMS_SOURCE_ROOT}/cpukit/include"
-RTEMS_INCLUDE_CPUKIT_ARCH="-I${RTEMS_SOURCE_ROOT}/cpukit/score/cpu/\$(RTEMS_CPU)/include"
-
-RTEMS_CPUKIT_INCLUDE="${RTEMS_INCLUDE_CPUKIT} ${RTEMS_INCLUDE_CPUKIT_ARCH}"
-RTEMS_BUILD_INCLUDE="-I\$(top_builddir) -I${RTEMS_BUILD_ROOT}/include"
-
-RTEMS_INCLUDE="${RTEMS_BUILD_INCLUDE} ${RTEMS_CPUKIT_INCLUDE}"
-
-RTEMS_CPPFLAGS="${RTEMS_INCLUDE}"
-
-AC_SUBST([RTEMS_CPPFLAGS])
-])

aclocal/rtems-source-top.m4

@@ -1,8 +0,0 @@
-dnl
-dnl RTEMS_SOURCE_TOP
-dnl
-AC_DEFUN([RTEMS_SOURCE_TOP],
-[dnl
-RTEMS_SOURCE_ROOT="${with_rtems_source_top}"
-AC_SUBST([RTEMS_SOURCE_ROOT])
-])dnl

aclocal/rtems-top.m4

@@ -1,10 +1,12 @@
+dnl $Id$
+
 # AC_DISABLE_OPTION_CHECKING is not available before 2.62
 AC_PREREQ(2.62)
 
 dnl
 dnl RTEMS_TOP($1)
 dnl 
-dnl $1 .. relative path from this configure.ac to the toplevel configure.ac
+dnl $1 .. relative path from this configure.in to the toplevel configure.in
 dnl
 AC_DEFUN([RTEMS_TOP],
 [dnl
@@ -14,7 +16,7 @@ AC_CONFIG_AUX_DIR([$1])
 AC_CHECK_PROGS(MAKE, gmake make)
 AC_BEFORE([$0], [AM_INIT_AUTOMAKE])dnl
 
-AC_PREFIX_DEFAULT([/opt/rtems-][_RTEMS_API])
+AC_PREFIX_DEFAULT([/opt/rtems-][RTEMS_API])
 
 RTEMS_TOPdir="$1";
 AC_SUBST(RTEMS_TOPdir)
@@ -29,6 +31,4 @@ AC_SUBST(PROJECT_ROOT)
 
 AC_MSG_CHECKING([for RTEMS Version])
 AC_MSG_RESULT([_RTEMS_VERSION])
-pkgdatadir="${datadir}"/rtems[]_RTEMS_API;
-AC_SUBST([pkgdatadir])
 ])dnl

aclocal/version.m4

@@ -1,4 +1,4 @@
 AC_DEFUN([RTEMS_VERSIONING],
-m4_define([_RTEMS_VERSION],[5.0.0]))
+m4_define([_RTEMS_VERSION],[4.9.6]))
 
-m4_define([_RTEMS_API],[5])
+m4_define([RTEMS_API],[4.9])

ampolish3

@@ -0,0 +1,276 @@
+#! /usr/bin/perl -w
+
+# $Id$
+
+# Copyright (C) 2005, 2006 Ralf Corsépius, Ulm, Germany
+#
+# Permission to use, copy, modify, and distribute this software
+# is freely granted, provided that this notice is preserved.
+
+# Helper script to generate pre/tmpinstall rules for RTEMS Makefile.am.
+#
+# Usage: ampolish3 Makefile.am > preinstall.am
+#
+# Reads a Makefile.am from stdin and writes corresponding 
+# pre/tmpinstall rules to stdout.
+
+sub replace($);
+sub print_dirstamp($$$);
+
+# Predefined directory mappings:
+#
+# final-installation directory => temp installation directory
+my %dirmap = (
+   '$(includedir)' 		=> '$(PROJECT_INCLUDE)',
+   '$(libdir)' 			=> '$(PROJECT_LIB)',
+   '$(project_libdir)' 		=> '$(PROJECT_LIB)',
+   '$(project_includedir)' 	=> '$(PROJECT_INCLUDE)'
+  );
+
+# Conventions on automake primaries:
+#
+# *_HEADERS -> preinstall
+# noinst*_HEADERS -> noinst
+# noinst_*_LIBRARIES -> noinst
+# project_*_LIBRARIES -> tmpinstall
+# *_LIBRARIES -> ignore (no preinstallation)
+# dist_project_*_DATA -> preinstall (bsp_specs,linkcmds)
+# project_*_DATA -> tmpinstall (*.o, *.a)
+# dist_*_DATA -> ignore (no preinstallation)
+# *SCRIPTS -> ignore (no preinstallation)
+# noinst_*_PROGRAMS -> noinst
+# project_*_PROGRAMS -> tmpinstall
+# *_PROGRAMS -> ignore (no preinstallation)
+
+## 1st pass: read in file
+my @buffer1 = () ;
+my %seen = ();
+my %predefs = ();
+
+{
+  my $mode = 0 ;
+  my $line = '';
+
+  while ( <> )
+  {
+    if ( $mode == 0 )
+    {
+      if ( /^([a-zA-Z0-9_]+\s*[\+]?[:=].*)\\$/o )
+      {
+        $line = "$1" ;
+        $mode = 1;
+      } else {
+        push @buffer1, $_ ;
+      }
+    } elsif ( $mode == 1 ) {
+      if ( /^(.*)\\$/o ) {
+        $line .= $1;
+      } else {
+        $line .= $_ ;
+        push @buffer1, $line ;
+        $line = '';
+        $mode = 0 ;
+      }
+    }
+  }
+}
+
+#foreach my $l ( @buffer1 ) { print STDERR "1:<$l>"; }
+
+# Filter out all Makefile code not relevant here
+my @buffer2 = ();
+foreach my $l ( @buffer1 ) {
+  if ( $l=~ /^\t.*$/o )
+  { #ignore: Production of a make rule.
+  } elsif ( $l =~ /^\s*([a-zA-Z0-9_]*dir)\s*\=\s*(.*)\s*$/o )
+  { # dirs
+    push @buffer2, "$l";
+    $dirmap{"\$\($1\)"} = replace($2);
+  } elsif ( $l =~ /^\s*noinst_(.*)\s*[\+]?\=(.*)$/o )
+  { 
+    #ignore: noinst_* are not relevant here.
+  } elsif ( $l =~ /^\s*(nodist_|dist_|)(project_|)([a-zA-Z0-9_]+)_(HEADERS|LIBRARIES|DATA|SCRIPTS|PROGRAMS)\s*([\+]?\=)\s*(.*)/o )
+  {
+    if ( ( "$5" eq '=' ) ) {
+      my $v = $dirmap{"\$\($3dir\)"};
+      if ( $v =~ /\$\(PROJECT_[^\)]+\)$/ )
+      {
+         $predefs{"$v"} = 1;
+      }
+    }
+    foreach my $f ( split(' ',$6) ) {
+      push @buffer2, "$1$2$3_$4 +=$f\n";
+    }
+  } elsif ( $l =~ /^\s*(if|else|endif)\s*.*$/o )
+  { # conditionals
+    push @buffer2, "$l";
+  }
+
+  # Check if Makefile.am already contains CLEANFILES or DISTCLEANFILES
+  if ( $l =~ /^\s*(CLEANFILES|DISTCLEANFILES|SUBDIRS)\s*\=.*$/o )
+  {
+    $predefs{"$1"} = 1;
+  }
+}
+
+if ( $predefs{"\$(PROJECT_INCLUDE)"} ){
+  unshift @buffer2, "includedir = \$(includedir)\n";
+}
+if ( $predefs{"\$(PROJECT_LIB)"} ){
+  unshift @buffer2, "libdir = \$(libdir)\n";
+}
+
+# foreach my $l ( @buffer2 ) { print STDERR "2:<$l>"; }
+
+my @buffer3 = ();
+
+foreach my $l ( @buffer2 ) {
+ if ( $l =~ /^\s*([a-zA-Z0-9_]*dir)\s*\=\s*(.*)\s*$/o )
+  { # dirs
+    my $v = $dirmap{"\$\($1\)"};
+    print_dirstamp(\@buffer3,$v,"PREINSTALL_DIRS");
+    $seen{"PREINSTALL_DIRS"} = 1;
+  } elsif ( $l =~ /^\s*(nodist_|dist_|)(project_|)([a-zA-Z0-9_]+)_HEADERS\s*\+\=(.*)/o )
+  { # preinstall
+    my $v = $dirmap{"\$\($3dir\)"};
+    my $f = $4;
+    my $x ; my $i = rindex($f,'/');
+    if ($i < 0) { $x="$f";
+    } else { $x = substr($f,$i+1);
+    }
+    push @buffer3,
+          "$v/$x: $f $v/\$(dirstamp)\n",
+          "\t\$(INSTALL_DATA) \$< $v/$x\n",
+          "PREINSTALL_FILES += $v/$x\n\n";
+    $seen{"PREINSTALL_FILES"} = 1;
+  } elsif ( $l =~ /^\s*(nodist_|dist_|)(project_)([a-zA-Z0-9_]+)_LIBRARIES\s*\+\=(.*)/o )
+  { # tmpinstall
+    my $v = $dirmap{"\$\($3dir\)"};
+    my $f = $4;
+    my $x ; my $i = rindex($f,'/');
+    if ($i < 0) { $x="$f";
+    } else { $x = substr($f,$i+1);
+    }
+    push @buffer3,
+          "$v/$x: $f $v/\$(dirstamp)\n",
+          "\t\$(INSTALL_DATA) \$< $v/$x\n",
+          "TMPINSTALL_FILES += $v/$x\n\n";
+    $seen{"TMPINSTALL_FILES"} = 1;
+  } elsif ( $l =~ /^\s*(nodist_|dist_|)([a-zA-Z0-9_]+)_LIBRARIES\s*\+\=(.*)/o )
+  { # ignore
+  } elsif ( $l =~ /^\s*(dist_)(project_)([a-zA-Z0-9_]+)_DATA\s*\+\=(.*)/o )
+  { # preinstall
+    my $v = $dirmap{"\$\($3dir\)"};
+    my $f = $4;
+    my $x ; my $i = rindex($f,'/');
+    if ($i < 0) { $x="$f";
+    } else { $x = substr($f,$i+1);
+    }
+    push @buffer3,
+          "$v/$x: $f $v/\$(dirstamp)\n",
+          "\t\$(INSTALL_DATA) \$< $v/$x\n",
+          "PREINSTALL_FILES += $v/$x\n\n";
+    $seen{"PREINSTALL_FILES"} = 1;
+  } elsif ( $l =~ /^\s*(nodist_|)(project_)([a-zA-Z0-9_]+)_DATA\s*\+\=(.*)/o )
+  { # tmpinstall
+    my $v = $dirmap{"\$\($3dir\)"};
+    my $f = $4;
+    my $x ; my $i = rindex($f,'/');
+    if ($i < 0) { $x="$f";
+    } else { $x = substr($f,$i+1);
+    }
+    push @buffer3,
+          "$v/$x: $f $v/\$(dirstamp)\n",
+          "\t\$(INSTALL_DATA) \$< $v/$x\n",
+          "TMPINSTALL_FILES += $v/$x\n\n";
+    $seen{"TMPINSTALL_FILES"} = 1;
+  } elsif ( $l =~ /^\s*(dist_|)([a-zA-Z0-9_]+)_DATA\s*\+\=(.*)/o )
+  { # ignore
+  } elsif ( $l =~ /^\s*(nodist_|dist_|)([a-zA-Z0-9_]+)_SCRIPTS\s*\+\=(.*)/o )
+  { # ignore
+  } elsif ( $l =~ /^\s*(nodist_|dist_|)(project_)([a-zA-Z0-9_]+)_PROGRAMS\s*\+\=(.*)/o )
+  { # tmpinstall
+    my $v = $dirmap{"\$\($3dir\)"};
+
+    my $f = $4;
+    my $x ; my $i = rindex($f,'/');
+    if ($i < 0) { $x="$f";
+    } else { $x = substr($f,$i+1);
+    }
+    push @buffer3,
+          "$v/$x: $f $v/\$(dirstamp)\n",
+          "\t\$(INSTALL_PROGRAM) \$< $v/$x\n",
+          "TMPINSTALL_FILES += $v/$x\n\n";
+    $seen{"TMPINSTALL_FILES"} = 1;
+  } elsif ( $l =~ /^\s*(nodist_|dist_|)([a-zA-Z0-9_]+)_PROGRAMS\s*\+\=(.*)/o )
+  { # ignore
+  } elsif ( $l =~ /^\s*(if|else|endif)\s*.*$/o )
+  { # conditionals
+    push @buffer3, "$l";
+  }
+}
+
+# foreach my $l ( @buffer3 ) { print STDERR "3:<$l>"; }
+
+my $output;
+$output .= "## Automatically generated by ampolish3 - Do not edit\n\n";
+$output .=  "if AMPOLISH3\n";
+$output .=  "\$(srcdir)/preinstall.am: Makefile.am\n";
+$output .= "\t\$(AMPOLISH3) \$(srcdir)/Makefile.am > \$(srcdir)/preinstall.am\n";
+$output .= "endif\n\n";
+
+foreach my $k ( keys %seen )
+{
+  if ( $k =~ /PREINSTALL_FILES/o ) {
+    $output .= "all-am: \$(PREINSTALL_FILES)\n\n";
+
+    $output .= "$k =\n";
+    $output .= "CLEANFILES ";
+    if ( $predefs{"CLEANFILES"} ) { $output .= "+"; }
+    $output .= "= \$($k)\n";
+    $predefs{"CLEANFILES"} = 1;
+  } elsif ( $k =~ /TMPINSTALL_FILES/o ) {
+
+    $output .= "all-local: \$(TMPINSTALL_FILES)\n\n";
+
+    $output .= "$k =\n";
+    $output .= "CLEANFILES ";
+    if ( $predefs{"CLEANFILES"} ) { $output .= "+"; }
+    $output .= "= \$($k)\n";
+    $predefs{"CLEANFILES"} = 1;
+  } elsif ( $k =~ /.*DIRS/o ) {
+    $output .= "$k =\n";
+    $output .= "DISTCLEANFILES ";
+    if ( $predefs{"DISTCLEANFILES"} ) { $output .= "+"; }
+    $output .= "= \$($k)\n";
+    $predefs{"DISTCLEANFILES"} = 1;
+  }
+  $output .= "\n";
+}
+
+# Pretty printing
+$output .= join ( '', @buffer3 );
+$output =~ s/\nelse\n+endif/\nendif/g;
+$output =~ s/\n\n+endif/\nendif/g;
+$output =~ s/\nif [a-zA-Z0-9_!]+\n+endif//g;
+print STDOUT $output;
+
+exit 0;
+
+sub replace($)
+{
+  my ($v) = @_;
+  foreach my $i ( keys %dirmap )
+  {
+    $v =~ s/\Q$i/$dirmap{$i}/g;
+  }
+  return $v;
+}
+
+sub print_dirstamp($$$)
+{
+  my ($obuf,$file,$inst) = @_ ;
+  push @{$obuf}, "$file/\$(dirstamp):\n\t\@\$\(MKDIR_P\) $file\n" ;
+  push @{$obuf}, "\t\@: \> $file/\$(dirstamp)\n" ;
+  push @{$obuf}, "$inst += $file/\$(dirstamp)\n\n" ;
+}

automake/host.am

@@ -1,5 +1,10 @@
+## $Id$
+
 ## NOTE: This is a temporary work-around to keep 
 ## RTEMS's non automake standard make targets working.
 ## Once automake is fully integrated these make targets 
 ## and this file will probably be removed
 
+preinstall-am: $(PREINSTALL_FILES)
+preinstall: preinstall-am
+.PHONY: preinstall preinstall-am

automake/local.am

@@ -0,0 +1,7 @@
+## $Id$
+
+preinstall-am: $(PREINSTALL_FILES)
+preinstall: preinstall-am
+.PHONY: preinstall preinstall-am
+
+PROJECT_TOOLS = $(PROJECT_RELEASE)/build-tools

automake/subdirs.am

@@ -1,3 +1,5 @@
+## $Id$
+
 ## Borrowed from automake-1.4 and adapted to RTEMS 
 
 ## NOTE: This is a temporary work-around to keep 
@@ -5,3 +7,26 @@
 ## Once automake is fully integrated these make targets 
 ## and this file will probably be removed
 
+preinstall-recursive:
+	@set fnord $(MAKEFLAGS); amf=$$2; \
+	dot_seen=no; \
+	target=`echo $@ | sed s/-recursive//`; \
+	list='$(SUBDIRS)'; for subdir in $$list; do \
+	  echo "Making $$target in $$subdir"; \
+	  if test "$$subdir" = "."; then \
+	    dot_seen=yes; \
+	    local_target="$$target-am"; \
+	  else \
+	    local_target="$$target"; \
+	  fi; \
+	  (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+## This trick allows "-k" to keep its natural meaning when running a
+## recursive rule.
+	   || case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
+	done; \
+	if test "$$dot_seen" = "no"; then \
+	  $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+	fi; test -z "$$fail"
+
+preinstall: preinstall-recursive
+.PHONY: preinstall-recursive

bootstrap

@@ -1,45 +1,73 @@
-#!/bin/sh
+#! /bin/sh
 #
 # helps bootstrapping, when checked out from CVS
 # requires GNU autoconf and GNU automake
 #
+# $Id$
+
 # this is not meant to be exported outside the source tree
-#
+
 # NOTE: Inspired by libtool's autogen script
-#
+
 # to be run from the toplevel directory of RTEMS'
 # source tree
 
 progname=`basename $0`
 top_srcdir=`dirname $0`
 
-LC_ALL=C
+verbose="";
-export LC_ALL
-
-verbose=""
 quiet="false"
-mode="autoreconf"
+mode="generate"
-force=0
 
 usage()
 {
   echo
-  echo "usage: ${progname} [-c|-h|-H] [-q][-v]"
+  echo "usage: ${progname} [-c|-p|-h] [-q][-v]"
   echo
   echo "options:"
   echo "	-c .. clean, remove all aclocal/autoconf/automake generated files"
   echo "	-h .. display this message and exit"
-  echo "	-H .. regenerate headers.am files"
+  echo "	-p .. regenerate preinstall.am files"
   echo "	-q .. quiet, don't display directories"
   echo "	-v .. verbose, pass -v to autotools"
   echo
-  exit 1
+  exit 1;
+}
+
+generate_bspdir_acinclude()
+{
+cat << EOF > acinclude.m4~
+# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY)
+AC_DEFUN([RTEMS_CHECK_BSPDIR],
+[
+  case "\$1" in
+EOF
+
+for i in */bsp_specs; do
+  d=`dirname $i`
+cat << EOF >> acinclude.m4~
+  $d )
+    AC_CONFIG_SUBDIRS([$d]);;
+EOF
+done
+cat << EOF >> acinclude.m4~
+  *)
+    AC_MSG_ERROR([Invalid BSP]);;
+  esac
+])
+EOF
+if cmp -s acinclude.m4 acinclude.m4~ 2>/dev/null; then
+  echo "acinclude.m4 is unchanged";
+else
+  cp acinclude.m4~ acinclude.m4
+fi
+rm -f acinclude.m4~
 }
 
 if test ! -f $top_srcdir/aclocal/version.m4; then
   echo "${progname}:"
   echo "	Installation problem: Can't find file aclocal/version.m4"
-  exit 1
+  exit 1;
 fi
 
 while test $# -gt 0; do
@@ -47,135 +75,35 @@ case $1 in
 -h|--he|--hel|--help)
   usage ;;
 -q|--qu|--qui|--quie|--quiet)
-  quiet="true"
+  quiet="true";
   shift;;
 -v|--ve|--ver|--verb|--verbo|--verbos|--verbose)
-  verbose="-v"
+  verbose="-v";
   shift;;
 -c|--cl|--cle|--clea|--clean)
-  mode="clean"
+  mode="clean";
   shift;;
--f|--fo|--for|--forc|--force)
+-p|--pr|--pre|--prei|--prein|--preins|--preinst)
-  force=`expr $force + 1`
+  mode="preinstall";
-  shift;;
--H|--headers)
-  mode="headers"
   shift;;
 -r|--re|--rec|--reco|--recon|--reconf)
-  mode="autoreconf"
+  mode="autoreconf";
   shift;;
--g|--ge|--gen|--gene|--gener|--genera|--generat|--generate)
+-*) echo "unknown option $1" ;
-  mode="generate"
-  shift;;
--*) echo "unknown option $1"
   usage ;;
-*) echo "invalid parameter $1"
+*) echo "invalid parameter $1" ;
   usage ;;
 esac
 done
 
 case $mode in
-headers)
+preinstall)
-  if test "." != "$top_srcdir"; then
+  confs=`find . -name Makefile.am -exec grep -l 'include .*/preinstall\.am' {} \;`
-    echo "To generate the headers.am you must call the script via \"./$progname -H\""
+  for i in $confs; do
-    exit 1
+    dir=$(dirname $i);
-  fi
+    test "$quite" = "true" || echo "Generating $dir/preinstall.am"
-  base="$PWD"
+    ${top_srcdir}/ampolish3 "$dir/Makefile.am" > "$dir/preinstall.am"
-
-  # Generate cpukit/header-dirs.am
-  tmp="$base/cpukit/header-dirs.am.new"
-  hdr_dirs=`for i in cpukit/include cpukit/libnetworking cpukit/score/cpu/*/include ; do
-    cd "$i"
-    find -mindepth 1 -type d
-    cd "$base"
-  done | sort -u | sed 's%^\./%%'`
-  echo '## This file was generated by "./boostrap -H".' > "$tmp"
-  echo 'include_HEADERS =' >> "$tmp"
-  for dir in $hdr_dirs ; do
-    am_dir=`echo $dir | sed 's%[/-]%_%g'`
-    echo "include_${am_dir}dir = \$(includedir)/$dir" >> "$tmp"
-    echo "include_${am_dir}_HEADERS =" >> "$tmp"
   done
-  diff -q "$tmp" "cpukit/header-dirs.am" || mv "$tmp" "cpukit/header-dirs.am"
-  rm -f "$tmp"
-
-  # Generate cpukit/*/headers.am
-  tmp="$base/headers.am.new"
-  cpukit="$base/cpukit"
-  cd "$cpukit"
-  for inc in include score/cpu/*/include ; do
-    echo '## This file was generated by "./boostrap -H".' > "$tmp"
-    hdr=`dirname $inc`
-    am_dir=""
-    cd $inc
-    for b in `find -type d | sort` ; do
-      for j in `find $b -mindepth 1 -maxdepth 1 -name '*.h' | sed 's%^\.%%' | sed 's%^/%%' | sort` ; do
-        dir=`dirname $j`
-        if test x$dir != x. ; then
-          am_dir=`echo $dir | sed 's%[/-]%_%g'`
-          am_dir="_$am_dir"
-        else
-          am_dir=""
-        fi
-        echo "include${am_dir}_HEADERS += $inc/$j" >> "$tmp"
-      done
-    done
-    cd "$cpukit"
-    diff -q "$tmp" "${hdr}/headers.am" || mv "$tmp" "${hdr}/headers.am"
-  done
-  rm -f "$tmp"
-  cd "$base"
-
-  # Generate bsps/*/headers.am
-  tmp="$base/headers.am.new"
-  for i in bsps/include bsps/*/include bsps/*/*/include ; do
-    dir=""
-    am_dir=""
-    echo '## This file was generated by "./boostrap -H".' > "$tmp"
-    case $i in
-      bsps/*/*/include)
-        hdr="../"
-        inc="../../../../../../$i/"
-        ;;
-      bsps/*/include)
-        hdr="../"
-        inc="../../../../../$i/"
-        ;;
-      bsps/include)
-        hdr="../"
-        inc="../../$i/"
-        ;;
-      *)
-        hdr=""
-        inc=""
-        ;;
-    esac
-    cd $i
-    for b in `find -type d | sort` ; do
-      for j in `find $b -mindepth 1 -maxdepth 1 -name '*.h' -or -name '*.inc' | sed 's%^\.%%' | sed 's%^/%%' | sort` ; do
-        d=`dirname $j`
-        if test x$d != x$dir ; then
-          dir=$d
-          if test x$d != x. ; then
-            am_dir=`echo $dir | sed 's%[/-]%_%g'`
-            am_dir="_$am_dir"
-            printf "\ninclude%sdir = \$(includedir)/$dir\n" "$am_dir" >> "$tmp"
-          else
-            am_dir=""
-            echo "" >> "$tmp"
-          fi
-          echo "include${am_dir}_HEADERS =" >> "$tmp"
-        fi
-        echo "include${am_dir}_HEADERS += $inc$j" >> "$tmp"
-        if test $j = bsp.h ; then
-          echo "include_HEADERS += include/bspopts.h" >> "$tmp"
-        fi
-      done
-    done
-    cd "$base"
-    diff -q "$tmp" "$i/${hdr}headers.am" || mv "$tmp" "$i/${hdr}headers.am"
-  done
-  rm -f "$tmp"
   ;;
 
 generate)
@@ -184,19 +112,19 @@ generate)
     echo "You must have autoconf installed to run $program"
     exit 1
   fi
-
+  
   AUTOHEADER=${AUTOHEADER-autoheader}
   if test -z "$AUTOHEADER"; then
     echo "You must have autoconf installed to run $program"
     exit 1
   fi
-
+  
   AUTOMAKE=${AUTOMAKE-automake}
   if test -z "$AUTOMAKE"; then
     echo "You must have automake installed to run $program"
     exit 1
   fi
-
+  
   ACLOCAL=${ACLOCAL-aclocal}
   if test -z "$ACLOCAL"; then
     echo "You must have automake installed to run $program"
@@ -212,21 +140,23 @@ generate)
 
   confs=`find . \( -name 'configure.in' -o -name 'configure.ac' \) -print`
   for i in $confs; do
-  dir=`dirname $i`
+  dir=`dirname $i`;
-  configure=`basename $i`
+  configure=`basename $i`;
-  ( test "$quiet" = "true" || echo "$dir"
+  ( test "$quiet" = "true" || echo "$dir";
-    cd $dir
+    cd $dir;
+    test -n "`grep RTEMS_CHECK_BSPDIR ${configure}`" && \
+      generate_bspdir_acinclude;
     pat="s,\$(RTEMS_TOPdir),${aclocal_dir},g"
     aclocal_args=`grep '^[ ]*ACLOCAL_AMFLAGS' Makefile.am | \
-      sed -e 's%.*ACLOCAL_AMFLAGS.*\=[ ]*%%g' -e $pat `
+      sed -e 's%.*ACLOCAL_AMFLAGS.*\=[ ]*%%g' -e $pat ` ;
     test "$verbose" = "-v" && echo "${ACLOCAL} $aclocal_args"
-    ${ACLOCAL} $aclocal_args
+    ${ACLOCAL} $aclocal_args;
     test -n "`grep CONFIG_HEADER ${configure}`" && ${AUTOHEADER} \
-      && test "$verbose" = "-v" && echo "${AUTOHEADER}"
+      && test "$verbose" = "-v" && echo "${AUTOHEADER}";
     test -n "`grep RTEMS_BSP_CONFIGURE ${configure}`" && ${AUTOHEADER} \
-      && test "$verbose" = "-v" && echo "${AUTOHEADER}"
+      && test "$verbose" = "-v" && echo "${AUTOHEADER}";
-    test -f Makefile.am && ${AUTOMAKE} -a -c $verbose
+    test -f Makefile.am && ${AUTOMAKE} -a -c $verbose ;
-    ${AUTOCONF}
+    ${AUTOCONF};
     test -f Makefile.am && test -n "`grep 'stamp-h\.in' Makefile.in`" \
       && echo timestamp > stamp-h.in
   )
@@ -242,11 +172,13 @@ autoreconf)
 
   confs=`find . -name 'configure.ac' -print`
   for i in $confs; do
-  dir=`dirname $i`
+  dir=`dirname $i`;
-  configure=`basename $i`
+  configure=`basename $i`;
-  ( test "$quiet" = "true" || echo "$dir"
+  ( test "$quiet" = "true" || echo "$dir";
-    cd $dir
+    cd $dir;
-    ${AUTORECONF} -i --no-recursive $verbose
+    test -n "`grep RTEMS_CHECK_BSPDIR ${configure}`" && \
+      generate_bspdir_acinclude;
+    ${AUTORECONF} -i --no-recursive $verbose;
     test -f Makefile.am && test -n "`grep 'stamp-h\.in' Makefile.in`" \
       && echo timestamp > stamp-h.in
   )
@@ -255,58 +187,28 @@ autoreconf)
 
 clean)
   test "$quiet" = "true" || echo "removing automake generated Makefile.in files"
-  files=`find . -name 'Makefile.am' -print | sed -e 's%\.am%\.in%g'`
+  files=`find . -name 'Makefile.am' -print | sed -e 's%\.am%\.in%g'` ;
-  for i in $files; do
+  for i in $files; do if test -f $i; then
-    if test -f $i; then
+    rm -f $i
-      rm -f $i
+    test "$verbose" = "-v" && echo "$i"    
-      test "$verbose" = "-v" && echo "$i"
+  fi; done
-    fi
-  done
 
   test "$quiet" = "true" || echo "removing configure files"
-  files=`find . -name 'configure' -print`
+  files=`find . -name 'configure' -print` ;
-  for i in $files; do
+  test "$verbose" = "-v" && test -n "$files" && echo "$files" ;
-    if test -f $i; then
+  for i in $files; do if test -f $i; then
-      rm -f $i
+    rm -f $i config.sub config.guess depcomp install-sh mdate-sh missing \
-      test "$verbose" = "-v" && echo "$i"
+	mkinstalldirs texinfo.tex compile
-    fi
+    test "$verbose" = "-v" && echo "$i"    
-  done
+  fi; done
-
+  
-  if test $force -gt 0; then
-    needles=""
-    if test $force -gt 1; then
-      # Manually maintained
-      needles="$needles config.sub"
-      needles="$needles config.guess"
-    fi
-    if test $force -gt 0; then
-      # Inherited from automake
-      needles="$needles compile"
-      needles="$needles depcomp"
-      needles="$needles install-sh"
-      needles="$needles missing"
-      needles="$needles mdate-sh"
-    fi
-    for j in $needles; do
-      files=`find . -name "$j" -print`
-      for i in $files; do
-        if test -f $i; then
-          rm -f $i
-          test "$verbose" = "-v" && echo "$i"
-        fi
-      done
-    done
-  fi
-
   test "$quiet" = "true" || echo "removing aclocal.m4 files"
-  files=`find . -name 'aclocal.m4' -print`
+  files=`find . -name 'aclocal.m4' -print` ;
-  test "$verbose" = "-v" && test -n "$files" && echo "$files"
+  test "$verbose" = "-v" && test -n "$files" && echo "$files" ;
-  for i in $files; do
+  for i in $files; do if test -f $i; then
-    if test -f $i; then
+    rm -f $i
-      rm -f $i
+    test "$verbose" = "-v" && echo "$i"    
-      test "$verbose" = "-v" && echo "$i"
+  fi; done
-    fi
-  done
 
   find . -name '*~' -print | xargs rm -f
   find . -name 'bspopts.h.in' -print | xargs rm -f
@@ -315,7 +217,7 @@ clean)
   find . -name 'config.status' -print | xargs rm -f
   find . -name 'config.log' -print | xargs rm -f
   find . -name 'config.cache' -print | xargs rm -f
-  find . -name 'Makefile' -and -not -path ./testsuites/ada/sptests/sp19/Makefile -print | xargs rm -f
+  find . -name 'Makefile' -print | xargs rm -f
   find . -name '.deps' -print | xargs rm -rf
   find . -name '.libs' -print | xargs rm -rf
   find . -name 'stamp-h.in' | xargs rm -rf

bspkit/README

@@ -0,0 +1,6 @@
+WARNING
+=======
+
+All files in here are considered to be unstable and experimental.
+
+They are subject to change at any time without prior notice.

bspkit/avr/bare/ChangeLog

@@ -0,0 +1,3 @@
+2004-10-22	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	* cfg/bare-avr3.cfg, cfg/bare-avr5.cfg: New.

bspkit/avr/bare/cfg/bare-avr3.cfg

@@ -0,0 +1,39 @@
+# 
+#  Config file for the "bare" BSP
+#
+#  $Id$
+#
+
+# This is the actual bsp directory used during the build process.
+RTEMS_BSP_FAMILY=bare
+
+RTEMS_CPU_MODEL=avr3
+
+CPU_CFLAGS=-mmcu=avr3
+
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+# optimize flag: typically -0, could use -O4 or -fast
+# -O4 is ok for RTEMS
+CFLAGS_OPTIMIZE_V=-Os -fomit-frame-pointer
+
+# this target has no start file
+START_BASE=
+
+# The following are definitions of make-exe which will work using ld as
+# is currently required.  It is expected that as of gcc 2.8, the end user
+# will be able to override parts of the compilers specs and link using gcc.
+
+define make-exe
+	@echo "*** Cannot do a link with the bare bsp. ***"
+        @echo "#!/bin/sh" > $(basename $@).exe
+        @echo "echo \"Cannot do a link with the bare bsp.\"" >> $(basename $@).exe
+endef
+
+define make-cxx-exe
+	@echo "*** Cannot do a link with the bare bsp. ***"
+        @echo "#!/bin/sh" > $(basename $@).exe
+        @echo "echo \"Cannot do a link with the bare bsp.\"" >> $(basename $@).exe
+endef
+
+# Miscellaneous additions go here

bspkit/avr/bare/cfg/bare-avr5.cfg

@@ -0,0 +1,39 @@
+# 
+#  Config file for the "bare" BSP
+#
+#  $Id$
+#
+
+# This is the actual bsp directory used during the build process.
+RTEMS_BSP_FAMILY=bare
+
+RTEMS_CPU_MODEL=avr5
+
+CPU_CFLAGS=-mmcu=avr5
+
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+# optimize flag: typically -0, could use -O4 or -fast
+# -O4 is ok for RTEMS
+CFLAGS_OPTIMIZE_V=-O4 -fomit-frame-pointer
+
+# this target has no start file
+START_BASE=
+
+# The following are definitions of make-exe which will work using ld as
+# is currently required.  It is expected that as of gcc 2.8, the end user
+# will be able to override parts of the compilers specs and link using gcc.
+
+define make-exe
+	@echo "*** Cannot do a link with the bare bsp. ***"
+        @echo "#!/bin/sh" > $(basename $@).exe
+        @echo "echo \"Cannot do a link with the bare bsp.\"" >> $(basename $@).exe
+endef
+
+define make-cxx-exe
+	@echo "*** Cannot do a link with the bare bsp. ***"
+        @echo "#!/bin/sh" > $(basename $@).exe
+        @echo "echo \"Cannot do a link with the bare bsp.\"" >> $(basename $@).exe
+endef
+
+# Miscellaneous additions go here

bsps/arm/altera-cyclone-v/README

@@ -1,44 +0,0 @@
-Overview
---------
-Evaluation board for this BSP: 
-- Cyclone V SoC FPGA Development Kit
-- DK-DEV-5CSXC6N/ES-0L
-
-RTC
----
-The evaluation board contains a DS1339C RTC connected to I2C0. To use it you
-have to set the following options:
-
-  #define CONFIGURE_APPLICATION_NEEDS_RTC_DRIVER
-  #define CONFIGURE_BSP_PREREQUISITE_DRIVERS I2C_DRIVER_TABLE_ENTRY
-
-Additional there has to be one free file descriptor to access the i2c. Set the
-CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS accordingly.
-
-Network
--------
-The default PHY address can be overwritten by the application. To do this, the
-drv_ctrl pointer of the rtems_bsdnet_ifconfig structure should point to a
-dwmac_ifconfig_drv_ctrl object with the appropriate settings before the
-rtems_bsdnet_initialize_network() is called. E.g.:
-
-  #include <libchip/dwmac.h>
-  #include <bsp.h>
-
-  static dwmac_ifconfig_drv_ctrl drv_ctrl = {
-    .phy_addr = 1
-  };
-
-  ...
-
-  static struct rtems_bsdnet_ifconfig some_ifconfig = {
-    .name = RTEMS_BSP_NETWORK_DRIVER_NAME,
-    .attach = RTEMS_BSP_NETWORK_DRIVER_ATTACH,
-    .drv_ctrl = &drv_ctrl
-  };
-
-  ...
-
-  rtems_bsdnet_initialize_network();
-
-If drv_ctrl is the NULL pointer, default values will be used instead.

bsps/arm/altera-cyclone-v/config/altcycv.inc

@@ -1,12 +0,0 @@
-include $(RTEMS_ROOT)/make/custom/default.cfg
-
-RTEMS_CPU = arm
-
-CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
-
-#CFLAGS_OPTIMIZE_V ?= -O0 -g
-CFLAGS_OPTIMIZE_V ?= -O2 -g
-
-# Add CFLAGS and LDFLAGS for compiling and linking with per item sections
-CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
-LDFLAGS            = -Wl,--gc-sections

bsps/arm/altera-cyclone-v/config/altcycv_devkit.cfg

@@ -1 +0,0 @@
-include $(RTEMS_ROOT)/make/custom/altcycv.inc

bsps/arm/altera-cyclone-v/console/console-config.c

@@ -1,164 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycV
- */
-
-/*
- * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Dornierstr. 4
- *  82178 Puchheim
- *  Germany
- *  <info@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <libchip/ns16550.h>
-
-#include <rtems/bspIo.h>
-
-#include <bsp.h>
-#include <bsp/irq.h>
-#include <bsp/alt_clock_manager.h>
-#include <bsp/console-termios.h>
-#include <bsp/socal/alt_rstmgr.h>
-#include <bsp/socal/socal.h>
-#include <bsp/socal/alt_uart.h>
-#include <bsp/socal/hps.h>
-
-#ifdef BSP_USE_UART_INTERRUPTS
-  #define DEVICE_FNS &ns16550_handler_interrupt
-#else
-  #define DEVICE_FNS &ns16550_handler_polled
-#endif
-
-static uint8_t altera_cyclone_v_uart_get_register(uintptr_t addr, uint8_t i)
-{
-  volatile uint32_t *reg = (volatile uint32_t *) addr;
-
-  return (uint8_t) reg [i];
-}
-
-static void altera_cyclone_v_uart_set_register(uintptr_t addr, uint8_t i, uint8_t val)
-{
-  volatile uint32_t *reg = (volatile uint32_t *) addr;
-
-  reg [i] = val;
-}
-
-static bool altera_cyclone_v_uart_probe(
-  rtems_termios_device_context *base,
-  uint32_t uart_set_mask
-)
-{
-  ns16550_context *ctx = (ns16550_context *) base;
-  bool            ret           = true;
-  uint32_t        ucr;
-  ALT_STATUS_CODE sc;
-  void*           location = (void *) ctx->port;
-
-  /* The ALT_CLK_L4_SP is required for all SoCFPGA UARTs. 
-   * Check that it's enabled. */
-  if ( alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE ) {
-    ret = false;
-  }
-
-  if ( ret ) {
-    sc = alt_clk_freq_get(ALT_CLK_L4_SP, &ctx->clock);
-    if ( sc != ALT_E_SUCCESS ) {
-      ret = false;
-    }
-  }
-
-  if ( ret ) {
-    // Bring UART out of reset.
-    alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, uart_set_mask);
-
-    // Verify the UCR (UART Component Version)
-    ucr = alt_read_word( ALT_UART_UCV_ADDR( location ) );
-    if ( ucr != ALT_UART_UCV_UART_COMPONENT_VER_RESET ) {
-      ret = false;
-    }
-  }
-
-  if ( ret ) {
-    // Write SRR::UR (Shadow Reset Register :: UART Reset)
-    alt_write_word( ALT_UART_SRR_ADDR( location ), ALT_UART_SRR_UR_SET_MSK );
-
-    // Read the MSR to work around case:119085.
-    (void)alt_read_word( ALT_UART_MSR_ADDR( location ) );
-
-    ret = ns16550_probe( base );
-  }
-
-  return ret;
-}
-
-#ifdef CYCLONE_V_CONFIG_CONSOLE
-static bool altera_cyclone_v_uart_probe_0(rtems_termios_device_context *base)
-{
-  return altera_cyclone_v_uart_probe(base, ALT_RSTMGR_PERMODRST_UART0_SET_MSK);
-}
-
-static ns16550_context altera_cyclone_v_uart_context_0 = {
-  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("UART 0"),
-  .get_reg = altera_cyclone_v_uart_get_register,
-  .set_reg = altera_cyclone_v_uart_set_register,
-  .port = (uintptr_t) ALT_UART0_ADDR,
-  .irq = ALT_INT_INTERRUPT_UART0,
-  .initial_baud = CYCLONE_V_UART_BAUD
-};
-#endif
-
-#ifdef CYCLONE_V_CONFIG_UART_1
-static bool altera_cyclone_v_uart_probe_1(rtems_termios_device_context *base)
-{
-  return altera_cyclone_v_uart_probe(base, ALT_RSTMGR_PERMODRST_UART1_SET_MSK);
-}
-
-static ns16550_context altera_cyclone_v_uart_context_1 = {
-  .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("UART 1"),
-  .get_reg = altera_cyclone_v_uart_get_register,
-  .set_reg = altera_cyclone_v_uart_set_register,
-  .port = (uintptr_t) ALT_UART1_ADDR,
-  .irq = ALT_INT_INTERRUPT_UART1,
-  .initial_baud = CYCLONE_V_UART_BAUD
-};
-#endif
-
-const console_device console_device_table[] = {
-  #ifdef CYCLONE_V_CONFIG_CONSOLE
-    {
-      .device_file = "/dev/ttyS0",
-      .probe = altera_cyclone_v_uart_probe_0,
-      .handler = DEVICE_FNS,
-      .context = &altera_cyclone_v_uart_context_0.base
-    },
-  #endif
-  #ifdef CYCLONE_V_CONFIG_UART_1
-    {
-      .device_file = "/dev/ttyS1",
-      .probe = altera_cyclone_v_uart_probe_1,
-      .handler = DEVICE_FNS,
-      .context = &altera_cyclone_v_uart_context_1.base
-    },
-  #endif
-};
-
-const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table);
-
-static void output_char(char c)
-{
-  rtems_termios_device_context *ctx = console_device_table[0].context;
-
-  ns16550_polled_putchar( ctx, c );
-}
-
-BSP_output_char_function_type BSP_output_char = output_char;
-
-BSP_polling_getchar_function_type BSP_poll_char = NULL;

bsps/arm/altera-cyclone-v/contrib/doxygen.h

@@ -1,85 +0,0 @@
-/**
- * @defgroup RTEMSBSPsARMCycVContrib Contributed Code
- *
- * @ingroup RTEMSBSPsARMCycV
- *
- * @brief Contributed code from Altera.
- */
-
-/**
- * @defgroup CACHE_MGR Cache Management API
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup ALT_DMA DMA Controller API
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup ALT_DMA_COMMON DMA Controller Common API Definitions
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup ALT_DMA_PRG DMA Controller Programming API
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup ALT_I2C I2C Controller API
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup INT_COMMON Interrupt Controller Common Definitions
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup ALT_QSPI QSPI Flash Controller Module
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup ALT_SOCAL_UTIL SoCAL Utilities
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup ADDR_SPACE_MGR The Address Space Manager
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup CLK_MGR The Clock Manager API
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup ALT_GPIO_API The General Purpose Input/Output Manager API
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup RST_MGR The Reset Manager
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/**
- * @defgroup UART UART Driver API
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */

bsps/arm/altera-cyclone-v/contrib/hwlib/README.txt

@@ -1,19 +0,0 @@
-HWLIB
-=====
-Hwlib is a collection of sources provided by Altera for the Cyclone-V.
-
-As hwlib is third party software, please keep modifications and additions 
-to the sources to a minimum for easy maintenance. Otherwise updating to a 
-new version of hwlib released by Altera can become difficult.
-
-The hwlib directory contains only those files from Alteras hwlib which are
-required by the BSP (the whole hwlib was considered too big).
-The directory structure within the hwlib directory is equivalent to Alteras
-hwlib directory structure. For easy maintenance only whole files have been
-left out.
-
-Altera provides the hwlib with their SoC Embedded Design Suite (EDS).
-
-HWLIB Version:
---------------
-All files are from hwlib 13.1 distributed with SoC EDS 14.0.0.200.

bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_address_space.c

@@ -1,515 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
- *
- * alt_address_space.c - API for the Altera SoC FPGA address space.
- *
- ******************************************************************************/
-
-/******************************************************************************
- *
- * Copyright 2013 Altera Corporation. All Rights Reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * 
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- * 
- ******************************************************************************/
-
-#include <stddef.h>
-#include <bsp/alt_address_space.h>
-#include <bsp/socal/alt_l3.h>
-#include <bsp/socal/socal.h>
-#include <bsp/socal/alt_acpidmap.h>
-#include <bsp/hwlib.h>
-
-
-#define ALT_ACP_ID_MAX_INPUT_ID     7
-#define ALT_ACP_ID_MAX_OUTPUT_ID    4096
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
-                                     ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
-                                     ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_bridge_attr,
-                                     ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_bridge_attr)
-{
-    uint32_t remap_reg_val = 0;
-
-    // Parameter checking and validation...
-    if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM)
-    {
-        remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_BOOTROM);
-    }
-    else if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM)
-    {
-        remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_OCRAM);
-    }
-    else
-    {
-        return ALT_E_INV_OPTION;
-    }
-
-    if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM)
-    {
-        remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_SDRAM);
-    }
-    else if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM)
-    {
-        remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_OCRAM);
-    }
-    else
-    {
-        return ALT_E_INV_OPTION;
-    }
-
-    if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_INACCESSIBLE)
-    {
-        remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_INVISIBLE);
-    }
-    else if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_ACCESSIBLE)
-    {
-        remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_VISIBLE);
-    }
-    else
-    {
-        return ALT_E_INV_OPTION;
-    }
-
-    if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_INACCESSIBLE)
-    {
-        remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_INVISIBLE);
-    }
-    else if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_ACCESSIBLE)
-    {
-        remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_VISIBLE);
-    }
-    else
-    {
-        return ALT_E_INV_OPTION;
-    }
-
-    // Perform the remap.
-    alt_write_word(ALT_L3_REMAP_ADDR, remap_reg_val);
-
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-// Remap the MPU address space view of address 0 to access the SDRAM controller.
-// This is done by setting the L2 cache address filtering register start address
-// to 0 and leaving the address filtering address end address value
-// unmodified. This causes all physical addresses in the range
-// address_filter_start <= physical_address < address_filter_end to be directed
-// to the to the AXI Master Port M1 which is connected to the SDRAM
-// controller. All other addresses are directed to AXI Master Port M0 which
-// connect the MPU subsystem to the L3 interconnect.
-//
-// It is unnecessary to modify the MPU remap options in the L3 remap register
-// because those options only affect addresses in the MPU subsystem address
-// ranges that are now redirected to the SDRAM controller and never reach the L3
-// interconnect anyway.
-ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void)
-{
-    uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) &
-                              L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
-    return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end);
-}
-
-/******************************************************************************/
-// Return the L2 cache address filtering registers configuration settings in the
-// user provided start and end address range out parameters.
-ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
-                                           uint32_t* addr_filt_end)
-{
-    if (addr_filt_start == NULL || addr_filt_end == NULL)
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR);
-    uint32_t addr_filt_end_reg   = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR);
-
-    *addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK);
-    *addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
-                                           uint32_t addr_filt_end)
-{
-    // Address filtering start and end values must be 1 MB aligned.
-    if (  (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK)
-       || (addr_filt_end   & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK)  )
-    {
-        return ALT_E_ARG_RANGE;
-    }
-
-    // While it is possible to set the address filtering end value above its
-    // reset value and thereby access a larger SDRAM address range, it is not
-    // recommended. Doing so would potentially obscure any mapped HPS to FPGA
-    // bridge address spaces and peripherals on the L3 interconnect.
-    if (addr_filt_end > L2_CACHE_ADDR_FILTERING_END_RESET)
-    {
-        return ALT_E_ARG_RANGE;
-    }
-
-    // NOTE: ARM (ARM DDI 0246F CoreLink Level 2 Cache Controller L2C-310 TRM)
-    // recommends programming the Address Filtering End Register before the
-    // Address Filtering Start Register to avoid unpredictable behavior between
-    // the two writes.
-    alt_write_word(L2_CACHE_ADDR_FILTERING_END_ADDR, addr_filt_end);
-    // It is recommended that address filtering always remain enabled.
-    addr_filt_start |= L2_CACHE_ADDR_FILTERING_ENABLE_MASK;
-    alt_write_word(L2_CACHE_ADDR_FILTERING_START_ADDR, addr_filt_start);
-
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
-                                              const uint32_t output_id,
-                                              const ALT_ACP_ID_MAP_PAGE_t page,
-                                              const uint32_t aruser)
-{
-    if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    switch (output_id)
-    {
-    case ALT_ACP_ID_OUT_FIXED_ID_2:
-        alt_write_word(ALT_ACPIDMAP_VID2RD_ADDR,
-                         ALT_ACPIDMAP_VID2RD_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID2RD_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID2RD_USER_SET(aruser)
-                       | ALT_ACPIDMAP_VID2RD_FORCE_SET(1UL));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_3:
-        alt_write_word(ALT_ACPIDMAP_VID3RD_ADDR,
-                         ALT_ACPIDMAP_VID3RD_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID3RD_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID3RD_USER_SET(aruser)
-                       | ALT_ACPIDMAP_VID3RD_FORCE_SET(1UL));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_4:
-        alt_write_word(ALT_ACPIDMAP_VID4RD_ADDR,
-                         ALT_ACPIDMAP_VID4RD_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID4RD_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID4RD_USER_SET(aruser)
-                       | ALT_ACPIDMAP_VID4RD_FORCE_SET(1UL));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_5:
-        alt_write_word(ALT_ACPIDMAP_VID5RD_ADDR,
-                         ALT_ACPIDMAP_VID5RD_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID5RD_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID5RD_USER_SET(aruser)
-                       | ALT_ACPIDMAP_VID5RD_FORCE_SET(1UL));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_6:
-        alt_write_word(ALT_ACPIDMAP_VID6RD_ADDR,
-                         ALT_ACPIDMAP_VID6RD_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID6RD_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID6RD_USER_SET(aruser)
-                       | ALT_ACPIDMAP_VID6RD_FORCE_SET(1UL));
-        break;
-    default:
-        return ALT_E_BAD_ARG;
-    }
-
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
-                                               const uint32_t output_id,
-                                               const ALT_ACP_ID_MAP_PAGE_t page,
-                                               const uint32_t awuser)
-{
-    if (input_id > ALT_ACP_ID_OUT_DYNAM_ID_7 || output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    switch (output_id)
-    {
-    case ALT_ACP_ID_OUT_FIXED_ID_2:
-        alt_write_word(ALT_ACPIDMAP_VID2WR_ADDR,
-                         ALT_ACPIDMAP_VID2WR_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID2WR_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID2WR_USER_SET(awuser)
-                       | ALT_ACPIDMAP_VID2WR_FORCE_SET(1UL));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_3:
-        alt_write_word(ALT_ACPIDMAP_VID3WR_ADDR,
-                         ALT_ACPIDMAP_VID3WR_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID3WR_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID3WR_USER_SET(awuser)
-                       | ALT_ACPIDMAP_VID3WR_FORCE_SET(1UL));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_4:
-        alt_write_word(ALT_ACPIDMAP_VID4WR_ADDR,
-                         ALT_ACPIDMAP_VID4WR_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID4WR_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID4WR_USER_SET(awuser)
-                       | ALT_ACPIDMAP_VID4WR_FORCE_SET(1UL));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_5:
-        alt_write_word(ALT_ACPIDMAP_VID5WR_ADDR,
-                         ALT_ACPIDMAP_VID5WR_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID5WR_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID5WR_USER_SET(awuser)
-                       | ALT_ACPIDMAP_VID5WR_FORCE_SET(1UL));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_6:
-        alt_write_word(ALT_ACPIDMAP_VID6WR_ADDR,
-                         ALT_ACPIDMAP_VID6WR_MID_SET(input_id)
-                       | ALT_ACPIDMAP_VID6WR_PAGE_SET(page)
-                       | ALT_ACPIDMAP_VID6WR_USER_SET(awuser)
-                       | ALT_ACPIDMAP_VID6WR_FORCE_SET(1UL)
-            );
-        break;
-    default:
-        return ALT_E_BAD_ARG;
-    }
-
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id)
-{
-    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    uint32_t aruser, page;
-
-    switch (output_id)
-    {
-    case ALT_ACP_ID_OUT_FIXED_ID_2:
-        aruser = ALT_ACPIDMAP_VID2RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
-        page = ALT_ACPIDMAP_VID2RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_3:
-        aruser = ALT_ACPIDMAP_VID3RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
-        page = ALT_ACPIDMAP_VID3RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_4:
-        aruser = ALT_ACPIDMAP_VID4RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
-        page = ALT_ACPIDMAP_VID4RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_5:
-        aruser = ALT_ACPIDMAP_VID5RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
-        page = ALT_ACPIDMAP_VID5RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_6:
-        aruser = ALT_ACPIDMAP_VID6RD_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
-        page = ALT_ACPIDMAP_VID6RD_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_ADDR));
-        break;
-    default:
-        return ALT_E_BAD_ARG;
-    }
-
-    alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
-                     ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
-                   | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id)
-{
-    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    uint32_t awuser, page;
-
-    switch (output_id)
-    {
-    case ALT_ACP_ID_OUT_FIXED_ID_2:
-        awuser = ALT_ACPIDMAP_VID2WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
-        page   = ALT_ACPIDMAP_VID2WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_3:
-        awuser = ALT_ACPIDMAP_VID3WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
-        page   = ALT_ACPIDMAP_VID3WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_4:
-        awuser = ALT_ACPIDMAP_VID4WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
-        page   = ALT_ACPIDMAP_VID4WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_5:
-        awuser = ALT_ACPIDMAP_VID5WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
-        page   = ALT_ACPIDMAP_VID5WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_6:
-        awuser = ALT_ACPIDMAP_VID6WR_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
-        page   = ALT_ACPIDMAP_VID6WR_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_ADDR));
-        break;
-    default:
-        return ALT_E_BAD_ARG;
-    }
-
-    alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
-                     ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
-                   | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
-                                                        const uint32_t aruser)
-{
-    alt_write_word(ALT_ACPIDMAP_DYNRD_ADDR,
-                     ALT_ACPIDMAP_DYNRD_PAGE_SET(page)
-                   | ALT_ACPIDMAP_DYNRD_USER_SET(aruser));
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
-                                                         const uint32_t awuser)
-{
-    alt_write_word(ALT_ACPIDMAP_DYNWR_ADDR,
-                     ALT_ACPIDMAP_DYNWR_PAGE_SET(page)
-                   | ALT_ACPIDMAP_DYNWR_USER_SET(awuser));
-    return ALT_E_SUCCESS;
-}
-
-/******************************************************************************/
-ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
-                                                bool * fixed,
-                                                uint32_t * input_id,
-                                                ALT_ACP_ID_MAP_PAGE_t * page,
-                                                uint32_t * aruser)
-{
-    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    switch (output_id)
-    {
-    case ALT_ACP_ID_OUT_FIXED_ID_2:
-        *aruser   = ALT_ACPIDMAP_VID2RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID2RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID2RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2RD_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_3:
-        *aruser   = ALT_ACPIDMAP_VID3RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID3RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID3RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3RD_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_4:
-        *aruser   = ALT_ACPIDMAP_VID4RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID4RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID4RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4RD_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_5:
-        *aruser   = ALT_ACPIDMAP_VID5RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID5RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID5RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5RD_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_6:
-        *aruser   = ALT_ACPIDMAP_VID6RD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6RD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID6RD_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID6RD_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6RD_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_7:
-        *aruser   = ALT_ACPIDMAP_DYNRD_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNRD_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNRD_S_ADDR));
-        break;
-    default:
-        return ALT_E_BAD_ARG;
-    }
-
-    return ALT_E_SUCCESS;
-}
-
-ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
-                                                 bool * fixed,
-                                                 uint32_t * input_id,
-                                                 ALT_ACP_ID_MAP_PAGE_t * page,
-                                                 uint32_t * awuser)
-{
-    if (output_id == ALT_ACP_ID_MAX_OUTPUT_ID)
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    switch (output_id)
-    {
-    case ALT_ACP_ID_OUT_FIXED_ID_2:
-        *awuser   = ALT_ACPIDMAP_VID2WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID2WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID2WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID2WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID2WR_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_3:
-        *awuser   = ALT_ACPIDMAP_VID3WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID3WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID3WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID3WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID3WR_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_4:
-        *awuser   = ALT_ACPIDMAP_VID4WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID4WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID4WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID4WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID4WR_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_5:
-        *awuser   = ALT_ACPIDMAP_VID5WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID5WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID5WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID5WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID5WR_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_6:
-        *awuser   = ALT_ACPIDMAP_VID6WR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_VID6WR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
-        *input_id = ALT_ACPIDMAP_VID6WR_S_MID_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
-        *fixed    = ALT_ACPIDMAP_VID6WR_S_FORCE_GET(alt_read_word(ALT_ACPIDMAP_VID6WR_S_ADDR));
-        break;
-    case ALT_ACP_ID_OUT_DYNAM_ID_7:
-        *awuser   = ALT_ACPIDMAP_DYNWR_S_USER_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
-        *page     = (ALT_ACP_ID_MAP_PAGE_t)ALT_ACPIDMAP_DYNWR_S_PAGE_GET(alt_read_word(ALT_ACPIDMAP_DYNWR_S_ADDR));
-        break;
-    default:
-        return ALT_E_BAD_ARG;
-    }
-
-    return ALT_E_SUCCESS;
-}

bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_generalpurpose_io.c

@@ -1,783 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
-*
-* Copyright 2013 Altera Corporation. All Rights Reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-*
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-*
-* 3. The name of the author may not be used to endorse or promote products
-* derived from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-* OF SUCH DAMAGE.
-*
-******************************************************************************/
-
-#include    <stdint.h>
-#include    <stdlib.h>
-#include    <stdbool.h>
-
-#include    <bsp/socal/hps.h>
-#include    <bsp/socal/socal.h>
-#include    <bsp/socal/alt_gpio.h>
-#include    <bsp/socal/alt_rstmgr.h>
-#include    <bsp/hwlib.h>
-#include    <bsp/alt_generalpurpose_io.h>
-
-
-/****************************************************************************************/
-/******************************* Useful local definitions *******************************/
-/****************************************************************************************/
-
-#define     ALT_GPIO_EOPA       ALT_GPIO_1BIT_28
-#define     ALT_GPIO_EOPB       ALT_GPIO_1BIT_57
-#define     ALT_GPIO_EOPC       ALT_HLGPI_15
-#define     ALT_GPIO_BITMASK    0x1FFFFFFF
-
-            // expands the zero or one bit to the 29-bit GPIO word
-#define     ALT_GPIO_ALLORNONE(tst)  ((uint32_t) ((tst == 0) ? 0 : ALT_GPIO_BITMASK))
-
-
-/****************************************************************************************/
-/* alt_gpio_init() initializes the GPIO modules 										*/
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_init(void)
-{
-		// put GPIO modules into system manager reset if not already there
-	alt_gpio_uninit();
-		// release GPIO modules from system reset (w/ two-instruction delay)
-	alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK |
-			ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK |
-			ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK, 0);
-	return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_uninit() uninitializes the GPIO modules			     				       	*/
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_uninit(void)
-{
-	// put all GPIO modules into system manager reset
-	alt_replbits_word(ALT_RSTMGR_PERMODRST_ADDR, ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK |
-			ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK |
-			ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK,
-			ALT_GPIO_BITMASK);
-	return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_datadir_set() sets the specified GPIO data bits to use the data        */
-/* direction(s) specified. 0 = input (default). 1 = output.                             */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask, uint32_t config)
-{
-    volatile uint32_t   *addr;
-
-    if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK))  { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_SWPORTA_DDR_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DDR_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DDR_ADDR; }
-    else { return ALT_E_BAD_ARG; }
-
-    alt_replbits_word(addr, mask, config);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/*  alt_gpio_port_datadir_get() returns the data direction configuration of selected    */
-/* bits of the designated GPIO module.                                                  */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_SWPORTA_DDR_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DDR_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DDR_ADDR; }
-    else { return 0; }
-
-    return alt_read_word(addr) & mask;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_data_write() sets the GPIO data outputs of the specified GPIO module   */
-/* to a one or zero. Actual outputs are only set if the data direction for that bit(s)  */
-/* has previously been set to configure them as output(s).                              */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask, uint32_t val)
-{
-    volatile uint32_t   *addr;
-
-    if ((mask & ~ALT_GPIO_BITMASK) || (val & ~ALT_GPIO_BITMASK))  { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_SWPORTA_DR_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_SWPORTA_DR_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_SWPORTA_DR_ADDR; }
-    else { return ALT_E_BAD_ARG; }
-
-    alt_replbits_word(addr, mask, val);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_data_read() returns the value of the data inputs of the specified      */
-/* GPIO module. Data direction for these bits must have been previously set to inputs.  */
-/****************************************************************************************/
-
-#if (!ALT_GPIO_DATAREAD_TEST_MODE)
-    /* This is the production code version. For software unit testing, set the      */
-    /* ALT_GPIO_DATAREAD_TEST_MODE flag to true in the makefile, which will compile */
-    /* the GPIO test software version of alt_gpio_port_data_read() instead.         */
-
-uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_EXT_PORTA_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_EXT_PORTA_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_EXT_PORTA_ADDR; }
-    else { return 0; }
-
-    return alt_read_word(addr) & mask;
-}
-#endif
-
-
-/****************************************************************************************/
-/* alt_gpio_port_int_type_set() sets selected signals of the specified GPIO port to     */
-/* be either level-sensitive ( =0) or edge-triggered ( =1).                             */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask, uint32_t config)
-{
-    volatile uint32_t   *addr;
-
-    if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK))  { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTTYPE_LEVEL_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTTYPE_LEVEL_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTTYPE_LEVEL_ADDR; }
-    else { return ALT_E_BAD_ARG; }
-
-    alt_replbits_word(addr, mask, config);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_int_type_get() returns the interrupt configuration (edge-triggered or  */
-/* level-triggered) for the specified signals of the specified GPIO module.             */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTTYPE_LEVEL_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTTYPE_LEVEL_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTTYPE_LEVEL_ADDR; }
-    else { return 0; }
-
-    return alt_read_word(addr) & mask;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_int_pol_set() sets the interrupt polarity of the signals of the        */
-/* specified GPIO register (when used as inputs) to active-high ( =0) or active-low     */
-/* ( =1).                                                                               */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask, uint32_t config)
-{
-    volatile uint32_t   *addr;
-
-    if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK))  { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INT_POL_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INT_POL_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INT_POL_ADDR; }
-    else { return ALT_E_BAD_ARG; }
-
-    alt_replbits_word(addr, mask, config);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_int_pol_get() returns the active-high or active-low polarity           */
-/* configuration for the possible interrupt sources of the specified GPIO module.       */
-/* 0 = The interrupt polarity for this bit is set to active-low mode. 1 = The           */
-/* interrupt polarity for this bit is set to active-highmode.                           */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INT_POL_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INT_POL_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INT_POL_ADDR; }
-    else { return 0; }
-
-    return alt_read_word(addr) & mask;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_debounce_set() sets the debounce configuration for input signals of    */
-/* the specified GPIO module. 0 - Debounce is not selected for this signal (default).   */
-/* 1 - Debounce is selected for this signal.                                            */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask, uint32_t config)
-{
-    volatile uint32_t   *addr;
-
-    if ((mask & ~ALT_GPIO_BITMASK) || (config & ~ALT_GPIO_BITMASK))  { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_DEBOUNCE_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_DEBOUNCE_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_DEBOUNCE_ADDR; }
-    else { return ALT_E_BAD_ARG; }
-
-    alt_replbits_word(addr, mask, config);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_debounce_get() returns the debounce configuration for the input        */
-/* signals of the specified GPIO register. 0 - Debounce is not selected for this        */
-/* signal. 1 - Debounce is selected for this signal.                                    */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_DEBOUNCE_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_DEBOUNCE_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_DEBOUNCE_ADDR; }
-    else { return 0; }
-
-    return alt_read_word(addr) & mask;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_sync_set() sets the synchronization configuration for the signals of   */
-/* the specified GPIO register. This allows for synchronizing level-sensitive           */
-/* interrupts to the internal clock signal. This is a port-wide option that controls    */
-/* all level-sensitive interrupt signals of that GPIO port.                             */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
-{
-    volatile uint32_t   *addr;
-
-    config = (config != 0) ? 1 : 0;
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_LS_SYNC_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_LS_SYNC_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_LS_SYNC_ADDR; }
-    else { return ALT_E_BAD_ARG; }
-
-    alt_write_word(addr, config);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_sync_get() returns the synchronization configuration for the signals   */
-/* of the specified GPIO register. This allows for synchronizing level-sensitive        */
-/* interrupts to the internal clock signal. This is a port-wide option that controls    */
-/* all level-sensitive interrupt signals of that GPIO port.                             */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_LS_SYNC_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_LS_SYNC_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_LS_SYNC_ADDR; }
-    else { return ALT_E_BAD_ARG; }         // error
-
-    return (alt_read_word(addr) != 0) ? ALT_E_TRUE : ALT_E_FALSE;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_config() configures a group of GPIO signals with the same parameters.  */
-/* Allows for configuring all parameters of a given port at one time.                   */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
-        ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc,
-        uint32_t data)
-{
-    ALT_STATUS_CODE     ret;
-
-        // set all affected GPIO bits to inputs
-    ret = alt_gpio_port_datadir_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(ALT_GPIO_PIN_INPUT));
-                // the ALT_GPIO_ALLORNONE() macro expands the zero or one bit to the 29-bit GPIO word
-
-        // set trigger type
-    if (ret == ALT_E_SUCCESS)
-    {
-        ret = alt_gpio_port_int_type_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(type));
-    }
-
-        // set polarity
-    if (ret == ALT_E_SUCCESS)
-    {
-        alt_gpio_port_int_pol_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(pol));
-    }
-
-        // set debounce
-    if (ret == ALT_E_SUCCESS)
-    {
-        alt_gpio_port_debounce_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(debounc));
-    }
-
-        // set data output(s)
-    if (ret == ALT_E_SUCCESS)
-    {
-        alt_gpio_port_data_write(gpio_pid, mask, ALT_GPIO_ALLORNONE(data));
-    }
-
-    if (ret == ALT_E_SUCCESS)
-    {
-        // set data direction of one or more bits to select output
-        ret = alt_gpio_port_datadir_set(gpio_pid, mask, ALT_GPIO_ALLORNONE(dir));
-    }
-
-    return ret;
-}
-
-
-/****************************************************************************************/
-/* Enables the specified GPIO data register interrupts.                                 */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
-{
-    volatile uint32_t   *addr;
-
-    if (config & ~ALT_GPIO_BITMASK)      { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTEN_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
-    else { return ALT_E_BAD_ARG; }
-
-    alt_replbits_word(addr, config, UINT32_MAX);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* Disables the specified GPIO data module interrupts.                                  */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config)
-{
-    volatile uint32_t   *addr;
-
-    if (config & ~ALT_GPIO_BITMASK)      { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTEN_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
-    else { return ALT_E_BAD_ARG; }
-
-    alt_replbits_word(addr, config, 0);
-    return ALT_E_SUCCESS;
-}
-
-
-
-/****************************************************************************************/
-/* Get the current state of the specified GPIO port interrupts enables.                 */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTEN_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTEN_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTEN_ADDR; }
-    else { return 0; }
-
-    return alt_read_word(addr);
-}
-
-
-/****************************************************************************************/
-/* Masks or unmasks selected interrupt source bits of the data register of the          */
-/* specified GPIO module. Uses a second bit mask to determine which signals may be      */
-/* changed by this call.                                                                */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t mask, uint32_t val)
-{
-    volatile uint32_t   *addr;
-
-    if ((mask & ~ALT_GPIO_BITMASK) || (val & ~ALT_GPIO_BITMASK))  { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTMSK_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTMSK_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTMSK_ADDR; }
-    else { return ALT_E_BAD_ARG; }         // argument error
-
-    alt_replbits_word(addr, mask, val);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/* Returns the interrupt source mask of the specified GPIO module.                      */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTMSK_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTMSK_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTMSK_ADDR; }
-    else { return 0; }         // error
-
-    return alt_read_word(addr);
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_int_status_get() returns the interrupt pending status of all signals   */
-/* of the specified GPIO register.                                                      */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTSTAT_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTSTAT_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTSTAT_ADDR; }
-    else { return 0; }         // error
-
-    return alt_read_word(addr);
-}
-
-
-/****************************************************************************************/
-/* Clear the interrupt pending status of selected signals of the specified GPIO         */
-/* register.                                                                            */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid,
-        uint32_t clrmask)
-{
-    volatile uint32_t   *addr;
-
-    if (clrmask & ~ALT_GPIO_BITMASK)      { return ALT_E_ERROR; }
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_INTSTAT_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_INTSTAT_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_INTSTAT_ADDR; }
-    else { return ALT_E_BAD_ARG; }         // argument error
-
-    alt_write_word(addr, clrmask);
-    return ALT_E_SUCCESS;
-}
-
-
-/****************************************************************************************/
-/*  alt_gpio_port_idcode_get() returns the ID code of the specified GPIO module.        */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_ID_CODE_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_ID_CODE_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_ID_CODE_ADDR; }
-    else { return 0; }
-
-    return alt_read_word(addr);
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_port_ver_get() returns the version code of the specified GPIO module.       */
-/****************************************************************************************/
-
-uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid)
-{
-    volatile uint32_t   *addr;
-
-    if (gpio_pid == ALT_GPIO_PORTA)      { addr = ALT_GPIO0_VER_ID_CODE_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTB) { addr = ALT_GPIO1_VER_ID_CODE_ADDR; }
-    else if (gpio_pid == ALT_GPIO_PORTC) { addr = ALT_GPIO2_VER_ID_CODE_ADDR; }
-    else { return 0; }
-
-    return alt_read_word(addr);
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_bit_config() configures one bit (signal) of the GPIO ports.                 */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num,
-        ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
-        ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce,
-        ALT_GPIO_PIN_DATA_t data)
-{
-    ALT_GPIO_PORT_t     pid;
-    uint32_t            mask;
-
-    pid = alt_gpio_bit_to_pid(signal_num);
-    mask = 0x1 << alt_gpio_bit_to_port_pin(signal_num);
-    return alt_gpio_port_config(pid, mask, dir, type, pol, debounce, data);
-}
-
-
-/****************************************************************************************/
-/* Returns the configuration parameters of a given GPIO bit.                            */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num,
-        ALT_GPIO_CONFIG_RECORD_t *config)
-{
-    ALT_STATUS_CODE     ret = ALT_E_ERROR;
-    ALT_GPIO_PORT_t     pid;
-    uint32_t            mask, shift;
-
-    if ((config != NULL) && (signal_num != ALT_END_OF_GPIO_SIGNALS) && (signal_num <= ALT_LAST_VALID_GPIO_BIT))
-    {
-        pid = alt_gpio_bit_to_pid(signal_num);
-        shift = alt_gpio_bit_to_port_pin(signal_num);
-        if ((pid != ALT_GPIO_PORT_UNKNOWN) && (shift <= ALT_GPIO_BIT_MAX))
-        {
-            config->signal_number = signal_num;
-            mask = 0x00000001 << shift;
-            config->direction = (alt_gpio_port_datadir_get(pid, mask) == 0) ? ALT_GPIO_PIN_INPUT : ALT_GPIO_PIN_OUTPUT;
-            config->type = (alt_gpio_port_int_type_get(pid, mask) == 0) ? ALT_GPIO_PIN_LEVEL_TRIG_INT : ALT_GPIO_PIN_EDGE_TRIG_INT;
-
-            // save the following data whatever the state of config->direction
-            config->polarity = (alt_gpio_port_int_pol_get(pid, mask) == 0) ? ALT_GPIO_PIN_ACTIVE_LOW : ALT_GPIO_PIN_ACTIVE_HIGH;
-            config->debounce = (alt_gpio_port_debounce_get(pid, mask) == 0) ? ALT_GPIO_PIN_NODEBOUNCE : ALT_GPIO_PIN_DEBOUNCE;
-            config->data = (alt_gpio_port_data_read(pid, mask) == 0) ? ALT_GPIO_PIN_DATAZERO : ALT_GPIO_PIN_DATAONE;
-            ret = ALT_E_SUCCESS;
-        }
-    }
-    return ret;
-}
-
-
-/****************************************************************************************/
-/* alt_gpio_group_config() configures a list of GPIO bits. The GPIO bits do not have    */
-/* to be configured the same, as was the case for the mask version of this function,    */
-/* alt_gpio_port_config(). Each bit may be configured differently and bits may be       */
-/* listed in any order.                                                                 */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array, uint32_t len)
-{
-    ALT_STATUS_CODE         ret = ALT_E_ERROR;
-
-    if (config_array != NULL)
-    {
-        if (config_array->signal_number == ALT_END_OF_GPIO_SIGNALS) { ret = ALT_E_SUCCESS; }
-            // catches the condition where the pointers are good, but the
-            // first index is the escape character - which isn't an error
-        else
-        {
-            for (; (len-- > 0) && (config_array->signal_number != ALT_END_OF_GPIO_SIGNALS) && (config_array != NULL); config_array++)
-            {
-                ret = alt_gpio_bit_config(config_array->signal_number,
-                        config_array->direction, config_array->type, config_array->polarity,
-                        config_array->debounce, config_array->data);
-                if ((config_array->direction == ALT_GPIO_PIN_OUTPUT) && (ret == ALT_E_SUCCESS))
-                {
-                    // if the pin is set to be an output, set it to the correct value
-                    alt_gpio_port_data_write(alt_gpio_bit_to_pid(config_array->signal_number),
-                             0x1 << alt_gpio_bit_to_port_pin(config_array->signal_number),
-                             ALT_GPIO_ALLORNONE(config_array->data));
-                        // ret should retain the value returned by alt_gpio_bit_config() above
-                        // and should not be changed by the alt_gpio_port_data_write() call.
-                }
-                if (((ret != ALT_E_SUCCESS) && (config_array->signal_number <= ALT_LAST_VALID_GPIO_BIT))
-                    || ((ret == ALT_E_SUCCESS) && (config_array->signal_number > ALT_LAST_VALID_GPIO_BIT)))
-                {
-                    ret = ALT_E_ERROR;
-                    break;
-                }
-            }
-        }
-    }
-    return ret;
-}
-
-
-/****************************************************************************************/
-/* Returns a list of the pin signal indices and the associated configuration settings   */
-/* (data direction, interrupt type, polarity, debounce, and synchronization) of that    */
-/* list of signals. Only the signal indices in the first field of each configuration    */
-/* record need be filled in. This function will fill in all the other fields of the     */
-/* configuration record, returning all configuration parameters in the array. A signal  */
-/* number index in the array equal to ALT_END_OF_GPIO_SIGNALS (-1) also terminates the  */
-/* function.                                                                            */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array,
-        uint32_t len)
-{
-    ALT_STATUS_CODE     ret = ALT_E_ERROR;
-
-    if ((config_array != NULL) && (config_array->signal_number == ALT_END_OF_GPIO_SIGNALS))
-    {
-        ret = ALT_E_SUCCESS;
-    }
-    else
-    {
-        for ( ; (len > 0) && (config_array != NULL) && (config_array->signal_number != ALT_END_OF_GPIO_SIGNALS)
-                    && (config_array->signal_number <= ALT_LAST_VALID_GPIO_BIT); len--)
-        {
-            ret = alt_gpio_bitconfig_get(config_array->signal_number, config_array);
-            config_array++;
-            if (ret != ALT_E_SUCCESS) { break; }
-        }
-    }
-    return ret;
-}
-
-/****************************************************************************************/
-/* Another way to return a configuration list. The difference between this version and  */
-/* alt_gpio_group_config_get() is that this version follows a separate list of signal   */
-/* indices instead of having the signal list provided in the first field of the         */
-/* configuration records in the array. This function will fill in the fields of the     */
-/* configuration record, returning all configuration parameters in the array. A signal  */
-/* number index in the array equal to ALT_END_OF_GPIO_SIGNALS (-1) also terminates      */
-/* operation.                                                                           */
-/****************************************************************************************/
-
-ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array,
-        ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len)
-{
-    ALT_STATUS_CODE     ret = ALT_E_ERROR;
-
-    if ((config_array != NULL) && (pinid_array != NULL) && (*pinid_array == ALT_END_OF_GPIO_SIGNALS))
-    {
-        ret = ALT_E_SUCCESS;
-        // catches the condition where the pointers are good, but the
-        // first index is the escape character - which isn't an error
-    }
-    else
-    {
-        for ( ;(len > 0) && (pinid_array != NULL) && (*pinid_array != ALT_END_OF_GPIO_SIGNALS) && (config_array != NULL); len--)
-        {
-            ret = alt_gpio_bitconfig_get(*pinid_array, config_array);
-            config_array++;
-            pinid_array++;
-            if (ret != ALT_E_SUCCESS) { break; }
-        }
-    }
-    return ret;
-}
-
-
-/****************************************************************************************/
-/* A useful utility function. Extracts the GPIO port ID from the supplied GPIO Signal   */
-/* Index Number.                                                                        */
-/****************************************************************************************/
-
-ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num)
-{
-    ALT_GPIO_PORT_t     pid = ALT_GPIO_PORT_UNKNOWN;
-
-    if (pin_num <= ALT_GPIO_EOPA) { pid = ALT_GPIO_PORTA; }
-    else if (pin_num <= ALT_GPIO_EOPB) { pid = ALT_GPIO_PORTB; }
-    else if (pin_num <= ALT_GPIO_EOPC) { pid = ALT_GPIO_PORTC; }
-    return pid;
-}
-
-
-/****************************************************************************************/
-/* A useful utility function. Extracts the GPIO signal (pin) mask from the supplied     */
-/* GPIO Signal Index Number.                                                           */
-/****************************************************************************************/
-
-ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num)
-{
-    if (pin_num <= ALT_GPIO_EOPA) {}
-    else if (pin_num <= ALT_GPIO_EOPB) { pin_num -= (ALT_GPIO_EOPA + 1); }
-    else if (pin_num <= ALT_GPIO_EOPC) { pin_num -= (ALT_GPIO_EOPB + 1); }
-    else { return ALT_END_OF_GPIO_PORT_SIGNALS; }
-    return (ALT_GPIO_PORTBIT_t) pin_num;
-}
-
-
-/****************************************************************************************/
-/* A useful utility function. Extracts the GPIO Signal Index Number from the supplied   */
-/* GPIO port ID and signal mask. If passed a bitmask composed of more than one signal,  */
-/* the signal number of the lowest bitmask presented is returned.                       */
-/****************************************************************************************/
-
-ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid,
-        uint32_t bitmask)
-{
-    uint32_t    i;
-
-    for (i=0; i <= ALT_GPIO_BITNUM_MAX ;i++)
-    {
-        if (bitmask & 0x00000001)
-        {
-            if (pid == ALT_GPIO_PORTA) {}
-            else if (pid == ALT_GPIO_PORTB) { i += ALT_GPIO_EOPA + 1; }
-            else if (pid == ALT_GPIO_PORTC) { i += ALT_GPIO_EOPB + 1; }
-            else { return ALT_END_OF_GPIO_SIGNALS; }
-            return (ALT_GPIO_1BIT_t) i;
-        }
-        bitmask >>= 1;
-    }
-    return ALT_END_OF_GPIO_SIGNALS;
-}
-

bsps/arm/altera-cyclone-v/contrib/hwlib/src/hwmgr/alt_reset_manager.c

@@ -1,141 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-
-/******************************************************************************
-*
-* alt_reset_manager.c - API for the Altera SoC FPGA reset manager.
-*
-******************************************************************************/
-
-/******************************************************************************
-*
-* Copyright 2013 Altera Corporation. All Rights Reserved.
-* 
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 
-* 3. The name of the author may not be used to endorse or promote products
-* derived from this software without specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-* OF SUCH DAMAGE.
-* 
-******************************************************************************/
-
-#include <bsp/alt_reset_manager.h>
-#include <bsp/socal/socal.h>
-#include <bsp/socal/hps.h>
-#include <bsp/socal/alt_rstmgr.h>
-
-/////
-
-
-uint32_t alt_reset_event_get(void)
-{
-    return alt_read_word(ALT_RSTMGR_STAT_ADDR);
-}
-
-ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask)
-{
-    alt_write_word(ALT_RSTMGR_STAT_ADDR, event_mask);
-    return ALT_E_SUCCESS;
-}
-
-ALT_STATUS_CODE alt_reset_cold_reset(void)
-{
-    alt_write_word(ALT_RSTMGR_CTL_ADDR, ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK);
-    return ALT_E_SUCCESS;
-}
-
-ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
-                                     uint32_t nRST_pin_clk_assertion,
-                                     bool sdram_refresh_enable,
-                                     bool fpga_mgr_handshake,
-                                     bool scan_mgr_handshake,
-                                     bool fpga_handshake,
-                                     bool etr_stall)
-{
-    // Cached register values
-    uint32_t ctrl_reg   = ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK;
-    uint32_t counts_reg = 0;
-
-    /////
-
-    // Validate warm_reset_delay is above 16 and below the field width
-    if ((warm_reset_delay < 16) || (warm_reset_delay >= (1 << ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH)))
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    // Validate nRST_pin_clk_assertion delay is non-zero and below the field width
-    if (!nRST_pin_clk_assertion)
-    {
-        return ALT_E_ERROR;
-    }
-    if (nRST_pin_clk_assertion >= (1 << ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH))
-    {
-        return ALT_E_BAD_ARG;
-    }
-
-    // Update counts register with warm_reset_delay information
-    counts_reg |= ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(warm_reset_delay);
-
-    // Update counts register with nRST_pin_clk_assertion information
-    counts_reg |= ALT_RSTMGR_COUNTS_NRSTCNT_SET(nRST_pin_clk_assertion);
-
-    /////
-
-    // Update ctrl register with the specified option flags
-
-    if (sdram_refresh_enable)
-    {
-        ctrl_reg |= ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK;
-    }
-
-    if (fpga_mgr_handshake)
-    {
-        ctrl_reg |= ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK;
-    }
-
-    if (scan_mgr_handshake)
-    {
-        ctrl_reg |= ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK;
-    }
-
-    if (fpga_handshake)
-    {
-        ctrl_reg |= ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK;
-    }
-
-    if (etr_stall)
-    {
-        ctrl_reg |= ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK;
-    }
-
-    /////
-
-    // Commit registers to hardware
-    alt_write_word(ALT_RSTMGR_COUNTS_ADDR, counts_reg);
-    alt_write_word(ALT_RSTMGR_CTL_ADDR,    ctrl_reg);
-
-    return ALT_E_SUCCESS;
-}

bsps/arm/altera-cyclone-v/headers.am

@@ -1,45 +0,0 @@
-## This file was generated by "./boostrap -H".
-
-include_HEADERS =
-include_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp.h
-include_HEADERS += include/bspopts.h
-include_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/tm27.h
-
-include_bspdir = $(includedir)/bsp
-include_bsp_HEADERS =
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/hwlib.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h
-include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/irq.h
-
-include_bsp_socaldir = $(includedir)/bsp/socal
-include_bsp_socal_HEADERS =
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h
-include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h

bsps/arm/altera-cyclone-v/i2c/i2cdrv-config.c

@@ -1,30 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVI2C
- */
-
-/*
- * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Dornierstr. 4
- *  82178 Puchheim
- *  Germany
- *  <info@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <bsp.h>
-#include "i2cdrv-config.h"
-
-const i2cdrv_configuration i2cdrv_config[CYCLONE_V_NO_I2C] = {
-  {
-    .controller = ALT_I2C_I2C0,
-    .device_name = "/dev/i2c0",
-    .speed = CYCLONE_V_I2C0_SPEED,
-  }
-};

bsps/arm/altera-cyclone-v/i2c/i2cdrv-config.h

@@ -1,43 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVI2C
- */
-
-/*
- * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Dornierstr. 4
- *  82178 Puchheim
- *  Germany
- *  <info@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef XXX_H
-#define XXX_H
-
-#include <rtems.h>
-#include <bsp/alt_i2c.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-typedef struct {
-  ALT_I2C_CTLR_t controller;
-  char *device_name;
-  uint32_t speed;
-} i2cdrv_configuration;
-
-extern const i2cdrv_configuration i2cdrv_config[];
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XXX_H */

bsps/arm/altera-cyclone-v/i2c/i2cdrv.c

@@ -1,221 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVI2C
- */
-
-/*
- * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Dornierstr. 4
- *  82178 Puchheim
- *  Germany
- *  <info@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <bsp.h>
-#include <bsp/i2cdrv.h>
-#include <assert.h>
-#include <rtems/libio.h>
-#include "i2cdrv-config.h"
-
-typedef struct {
-  ALT_I2C_DEV_t i2c_dev;
-  rtems_id mutex;
-} i2cdrv_entry;
-
-i2cdrv_entry i2cdrv_table[CYCLONE_V_NO_I2C];
-
-static ALT_I2C_DEV_t *get_device(i2cdrv_entry *e)
-{
-  return &e->i2c_dev;
-}
-
-static rtems_status_code init_i2c_module(
-  i2cdrv_entry *e,
-  const i2cdrv_configuration *cfg
-)
-{
-  ALT_STATUS_CODE asc = ALT_E_SUCCESS;
-  ALT_I2C_CTLR_t controller = cfg->controller;
-  ALT_I2C_DEV_t *dev = get_device(e);
-  ALT_I2C_MASTER_CONFIG_t i2c_cfg = {
-    .addr_mode = ALT_I2C_ADDR_MODE_7_BIT,
-    .restart_enable = false,
-  };
-
-  asc = alt_i2c_init(controller, dev);
-  if ( asc != ALT_E_SUCCESS ) {
-    return RTEMS_IO_ERROR;
-  }
-  asc = alt_i2c_op_mode_set(dev, ALT_I2C_MODE_MASTER);
-  if ( asc != ALT_E_SUCCESS ) {
-    return RTEMS_IO_ERROR;
-  }
-  asc = alt_i2c_master_config_speed_set(dev, &i2c_cfg, cfg->speed);
-  if ( asc != ALT_E_SUCCESS ) {
-    return RTEMS_IO_ERROR;
-  }
-  asc = alt_i2c_master_config_set(dev, &i2c_cfg);
-  if ( asc != ALT_E_SUCCESS ) {
-    return RTEMS_IO_ERROR;
-  }
-  asc = alt_i2c_enable(dev);
-  if ( asc != ALT_E_SUCCESS ) {
-    return RTEMS_IO_ERROR;
-  }
-
-  return RTEMS_SUCCESSFUL;
-}
-
-rtems_device_driver i2cdrv_initialize(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-)
-{
-  rtems_status_code sc = RTEMS_SUCCESSFUL;
-
-  for ( size_t i = 0; i < CYCLONE_V_NO_I2C; ++i ) {
-    i2cdrv_entry *e = &i2cdrv_table[i];
-    const i2cdrv_configuration *cfg = &i2cdrv_config[i];
-
-    sc = rtems_io_register_name(cfg->device_name, major, i);
-    assert(sc == RTEMS_SUCCESSFUL);
-
-    sc = rtems_semaphore_create(
-      rtems_build_name ('I', '2', 'C', '0' + i),
-      0,
-      RTEMS_BINARY_SEMAPHORE | RTEMS_PRIORITY | RTEMS_INHERIT_PRIORITY,
-      0,
-      &e->mutex
-    );
-    assert(sc == RTEMS_SUCCESSFUL);
-
-    sc = init_i2c_module(e, cfg);
-    if ( sc != RTEMS_SUCCESSFUL ) {
-      /* I2C is not usable at this point. Releasing the mutex would allow the
-       * usage which could lead to undefined behaviour. */
-      return sc;
-    }
-
-    sc = rtems_semaphore_release(e->mutex);
-    assert(sc == RTEMS_SUCCESSFUL);
-  }
-
-  return sc;
-}
-
-rtems_device_driver i2cdrv_open(
-  rtems_device_major_number major,
-  rtems_device_major_number minor,
-  void *arg
-)
-{
-  rtems_status_code sc = RTEMS_SUCCESSFUL;
-  i2cdrv_entry *e = &i2cdrv_table[minor];
-
-  sc = rtems_semaphore_obtain(e->mutex, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
-  return sc;
-}
-
-rtems_device_driver i2cdrv_close(
-  rtems_device_major_number major,
-  rtems_device_major_number minor,
-  void *arg
-)
-{
-  rtems_status_code sc = RTEMS_SUCCESSFUL;
-  i2cdrv_entry *e = &i2cdrv_table[minor];
-
-  sc = rtems_semaphore_release(e->mutex);
-  return sc;
-}
-
-rtems_device_driver i2cdrv_read(
-  rtems_device_major_number major,
-  rtems_device_major_number minor,
-  void *arg
-)
-{
-  rtems_status_code sc = RTEMS_SUCCESSFUL;
-  i2cdrv_entry *e = &i2cdrv_table[minor];
-  rtems_libio_rw_args_t *rw  = arg;
-  ALT_I2C_DEV_t *dev = get_device(e);
-  ALT_STATUS_CODE asc = ALT_E_SUCCESS;
-
-  asc = alt_i2c_master_receive(dev, rw->buffer, rw->count, true, true);
-  if ( asc == ALT_E_SUCCESS ) {
-    rw->bytes_moved = rw->count;
-  } else {
-    sc = RTEMS_IO_ERROR;
-  }
-
-  return sc;
-}
-
-rtems_device_driver i2cdrv_write(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-)
-{
-  rtems_status_code sc = RTEMS_SUCCESSFUL;
-  i2cdrv_entry *e = &i2cdrv_table[minor];
-  rtems_libio_rw_args_t *rw  = arg;
-  ALT_I2C_DEV_t *dev = get_device(e);
-  ALT_STATUS_CODE asc = ALT_E_SUCCESS;
-
-  asc = alt_i2c_master_transmit(dev, rw->buffer, rw->count, true, true);
-  if ( asc == ALT_E_SUCCESS ) {
-    rw->bytes_moved = rw->count;
-  } else {
-    sc = RTEMS_IO_ERROR;
-  }
-
-  return sc;
-}
-
-static rtems_status_code ioctl_set_slave_address(
-  i2cdrv_entry *e,
-  rtems_libio_ioctl_args_t *args
-)
-{
-  ALT_I2C_DEV_t *dev = get_device(e);
-  ALT_STATUS_CODE asc = ALT_E_SUCCESS;
-  uint32_t address = (uint32_t) args->buffer;
-
-  asc = alt_i2c_master_target_set(dev, address);
-  if ( asc != ALT_E_SUCCESS ) {
-    return RTEMS_IO_ERROR;
-  }
-
-  return RTEMS_SUCCESSFUL;
-}
-
-rtems_device_driver i2cdrv_ioctl(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-)
-{
-  rtems_status_code sc = RTEMS_SUCCESSFUL;
-  i2cdrv_entry *e = &i2cdrv_table[minor];
-  rtems_libio_ioctl_args_t *args = arg;
-
-  switch (args->command) {
-    case I2C_IOC_SET_SLAVE_ADDRESS:
-      sc = ioctl_set_slave_address(e, args);
-      break;
-    default:
-      sc = RTEMS_INVALID_NUMBER;
-      break;
-  }
-
-  return sc;
-}

bsps/arm/altera-cyclone-v/include/bsp.h

@@ -1,76 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycV
- */
-
-/*
- * Copyright (c) 2013, 2018 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Dornierstr. 4
- *  82178 Puchheim
- *  Germany
- *  <info@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
-#define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
-
-/**
- * @defgroup RTEMSBSPsARMCycV Intel Cyclone V
- *
- * @ingroup RTEMSBSPsARM
- *
- * @brief Intel Cyclone V Board Support Package.
- *
- * @{
- */
-
-#include <bspopts.h>
-
-#define BSP_FEATURE_IRQ_EXTENSION
-
-#ifndef ASM
-
-#include <rtems.h>
-
-#include <bsp/default-initial-extension.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
-
-#define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
-
-#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
-
-#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
-
-#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
-
-#ifndef BSP_ARM_A9MPCORE_PERIPHCLK
-extern uint32_t altera_cyclone_v_a9mpcore_periphclk;
-#define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk
-#define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
-#endif
-
-#define BSP_ARM_L2C_310_BASE 0xfffef000
-
-#define BSP_ARM_L2C_310_ID 0x410000c9
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* ASM */
-
-/* @} */
-
-#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */

bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h

@@ -1,831 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/*! \file
- *  Altera - SoC FPGA Address Space Manager
- */
-
-/******************************************************************************
-*
-* Copyright 2013 Altera Corporation. All Rights Reserved.
-* 
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 
-* 3. The name of the author may not be used to endorse or promote products
-* derived from this software without specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-* OF SUCH DAMAGE.
-* 
-******************************************************************************/
-
-#ifndef __ALT_ADDRESS_SPACE_H__
-#define __ALT_ADDRESS_SPACE_H__
-
-#include <stdbool.h>
-#include "hwlib.h"
-#include "socal/hps.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-/******************************************************************************/
-// ARM Level 2 Cache Controller L2C-310 Register Interface
-
-// Address Filtering Start Register
-// The Address Filtering Start Register is a read and write register.
-// Bits     Field                       Description
-// :-------|:--------------------------|:-----------------------------------------
-// [31:20] | address_filtering_start   | Address filtering start address for
-//         |                           | bits [31:20] of the filtering address.
-// [19:1]  | Reserved                  | SBZ/RAZ
-// [0]     | address_filtering_enable  | 0 - address filtering disabled
-//         |                           | 1 - address filtering enabled.
-
-// Address Filtering Start Register Address
-#define L2_CACHE_ADDR_FILTERING_START_OFST      0xC00
-#define L2_CACHE_ADDR_FILTERING_START_ADDR      (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST)
-// Address Filtering Start Register - Start Value Mask
-#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
-// Address Filtering Start Register - Reset Start Address Value (1 MB)
-#define L2_CACHE_ADDR_FILTERING_START_RESET     0x100000
-// Address Filtering Start Register - Enable Flag Mask
-#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK     0x00000001
-// Address Filtering Start Register - Reset Enable Flag Value (Enabled)
-#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET    0x1
-
-// Address Filtering End Register
-// The Address Filtering End Register is a read and write register.
-// Bits     Field                       Description
-// :-------|:--------------------------|:-----------------------------------------
-// [31:20] | address_filtering_end     | Address filtering end address for bits
-//         |                           | [31:20] of the filtering address.
-// [19:0]  | Reserved                  | SBZ/RAZ
-
-// Address Filtering End Register Address
-#define L2_CACHE_ADDR_FILTERING_END_OFST        0xC04
-#define L2_CACHE_ADDR_FILTERING_END_ADDR        (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST)
-// Address Filtering End Register - End Value Mask
-#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK   0xFFF00000
-// Address Filtering End Register - Reset End Address Value (3 GiB)
-#define L2_CACHE_ADDR_FILTERING_END_RESET       0xC0000000
-
-#ifndef __ASSEMBLY__
-
-/******************************************************************************/
-/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager
- *
- * This module contains group APIs for managing the HPS address space. This
- * module contains group APIs to manage:
- * * Memory Map Control
- * * Memory Coherence
- * * Cache Managment
- * * MMU Managment
- *
- * @{
- */
-
-/******************************************************************************/
-/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control
- *
- * This group API provides functions to map and remap selected address ranges
- * into the accessible (visible) views of the MPU and non MPU address spaces.
- *
- * \b Caveats
- *
- * \b NOTE: Caution should be observed when remapping address 0 to different
- * memory.  The code performing the remapping operation should not be executing
- * in the address range being remapped to different memory.
- *
- * For example, if address 0 is presently mapped to OCRAM and the code is
- * preparing to remap address 0 to SDRAM, then the code must not be executing in
- * the range 0 to 64 KB as this address space is about to be remapped to
- * different memory. If the code performing the remap operation is executing
- * from OCRAM then it needs to be executing from its permanently mapped OCRAM
- * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR).
- *
- * \b NOTE: The MPU address space view is controlled by two disparate hardware
- * control interfaces: the L3 remap register and the L2 cache address filtering
- * registers. To complicate matters, the L3 remap register is write-only which
- * means not only that current remap register state cannot be read but also that
- * a read-modify-write operation cannot be performed on the register.
- *
- * This should not present a problem in most use case scenarios except for the
- * case where a current MPU address space mapping of 0 to SDRAM is being changed
- * to to a mapping of 0 to Boot ROM or OCRAM.
- *
- * In this case, a two step process whereby the L3 remap register is first set
- * to the new desired MPU address 0 mapping and then the L2 cache address
- * filtering registers have their address ranges adjusted accordingly must be
- * followed. An example follows:
-\verbatim
-// 1 MB reset default value for address filtering start
-#define L2_CACHE_ADDR_FILTERING_START_RESET     0x100000
-uint32_t addr_filt_start;
-uint32_t addr_filt_end;
-
-// Perform L3 remap register programming first by setting the desired new MPU
-// address space 0 mapping. Assume OCRAM for the example.
-alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...);
-
-// Next, adjust the L2 cache address filtering range. Set the start address to
-// the default reset value and retain the existing end address configuration.
-alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end);
-if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET)
-{
-    alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end);
-}
-\endverbatim
- * @{
- */
-
-/******************************************************************************/
-/*!
- * This type definition enumerates the MPU address space attributes.
- *
- * The MPU address space consists of the ARM Cortex A9 processors and associated
- * processor peripherals (cache, MMU).
- */
-typedef enum ALT_ADDR_SPACE_MPU_ATTR_e
-{
-    ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,     /*!< Maps the Boot ROM to address
-                                             *   0x0 for the MPU L3 master. Note
-                                             *   that the Boot ROM is also
-                                             *   always mapped to address
-                                             *   0xfffd_0000 for the MPU L3
-                                             *   master independent of
-                                             *   attribute.
-                                             */
-
-    ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM        /*!< Maps the On-chip RAM to address
-                                             *   0x0 for the MPU L3 master. Note
-                                             *   that the On-chip RAM is also
-                                             *   always mapped to address
-                                             *   0xffff_0000 for the MPU L3
-                                             *   master independent of this
-                                             *   attribute.
-                                             */
-} ALT_ADDR_SPACE_MPU_ATTR_t;
-
-/******************************************************************************/
-/*!
- * This type definition enumerates the non-MPU address space attributes.
- *
- * The non-MPU address space consists of the non-MPU L3 masters including the
- * DMA controllers (standalone and those built into peripherals), the F2H AXI
- * Bridge, and the DAP.
- */
-typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e
-{
-    ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM,    /*!< Maps the SDRAM to address 0x0
-                                             *   for the non-MPU L3 masters.
-                                             */
-    ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM     /*!< Maps the On-chip RAM to address
-                                             *   0x0 for the non-MPU L3
-                                             *   masters. Note that the On-chip
-                                             *   RAM is also always mapped to
-                                             *   address 0xffff_0000 for the
-                                             *   non-MPU L3 masters independent
-                                             *   of this attribute.
-                                             */
-} ALT_ADDR_SPACE_NONMPU_ATTR_t;
-
-/******************************************************************************/
-/*!
- * This type definition enumerates the HPS to FPGA bridge accessiblity
- * attributes.
- */
-typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e
-{
-    ALT_ADDR_SPACE_H2F_INACCESSIBLE,        /*!< The H2F AXI Bridge is not
-                                             *   visible to L3 masters. Accesses
-                                             *   to the associated address range
-                                             *   return an AXI decode error to
-                                             *   the master.
-                                             */
-    ALT_ADDR_SPACE_H2F_ACCESSIBLE           /*!< The H2F AXI Bridge is visible
-                                             *   to L3 masters.
-                                             */
-} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t;
-
-/******************************************************************************/
-/*!
- * This type definition enumerates the Lightweight HPS to FPGA bridge
- * accessiblity attributes.
- */
-typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e
-{
-    ALT_ADDR_SPACE_LWH2F_INACCESSIBLE,      /*!< The LWH2F AXI Bridge is not
-                                             *   visible to L3 masters. Accesses
-                                             *   to the associated address range
-                                             *   return an AXI decode error to
-                                             *   the master.
-                                             */
-    ALT_ADDR_SPACE_LWH2F_ACCESSIBLE         /*!< The LWH2F AXI Bridge is visible
-                                             *   to L3 masters.
-                                             */
-} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t;
-
-/******************************************************************************/
-/*!
- * Configures the mapped and accessible (visible) address ranges for the HPS
- * MPU, non-MPU, and Bridge address spaces.
- *
- * \param       mpu_attr
- *              The MPU address space configuration attributes.
- *              
- * \param       nonmpu_attr
- *              The non-MPU address space configuration attributes.
- *              
- * \param       h2f_attr
- *              The H2F Bridge attribute mapping and accessibility attributes.
- *              
- * \param       lwh2f_attr
- *              The Lightweight H2F Bridge attribute mapping and accessibility
- *              attributes.
- *              
- * 
- * \retval      ALT_E_SUCCESS       The operation was succesful.
- * \retval      ALT_E_ERROR         The operation failed.
- * \retval      ALT_E_INV_OPTION    One or more invalid attribute options were
- *                                  specified.
- */
-ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
-                                     ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
-                                     ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr,
-                                     ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr);
-
-/******************************************************************************/
-/*!
- * Maps SDRAM to address 0x0 for the MPU address space view.
- *
- * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest
- * 64KB of the boot region are accessible because the size of the Boot ROM and
- * on-chip RAM are only 64KB.  Addresses in the range 0x100000 (1MiB) to
- * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to
- * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not
- * accessible to the MPU unless address 0 is remapped to SDRAM after reset.
- *
- * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access
- * SDRAM.
- *
- * \internal
- * The remap to address 0x0 is achieved by configuring the L2 cache Address
- * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM
- * AXI (M1) master port by calling:
- *
- * alt_l2_addr_filter_cfg_set(0x0, <current_addr_filt_end_value>);
- * 
- * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
- * Reference Manual, Section 3.3.12 Address Filtering </em>.
- * \endinternal
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void);
-
-/*! @} */
-
-/******************************************************************************/
-/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter
- *
- * The L2 cache address filter controls where physical addresses within certain
- * ranges of the MPU address space are directed.
- *
- * The L2 cache has master port connections to the L3 interconnect and the SDRAM
- * controller. A programmable address filter controls which portions of the
- * 32-bit physical address space use each master.
- * 
- * When l2 address filtering is configured and enabled, a physical address will
- * be redirected to one master or the other based upon the address filter
- * configuration.
- *
- * If \b address_filter_start <= \e physical_address < \b address_filter_end:
- * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller)
- * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect)
- *
- * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
- * Reference Manual, Section 3.3.12 Address Filtering </em> for more information.
- * @{
- */
-
-/******************************************************************************/
-/*!
- * Get the L2 cache address filtering configuration settings.
- *
- * \param       addr_filt_start
- *              [out] An output parameter variable for the address filtering
- *              start address for the range of physical addresses redirected to
- *              the SDRAM AXI master port. The value returned is always a 1 MiB
- *              aligned address.
- *              
- * \param       addr_filt_end
- *              [out] An output parameter variable for the address filtering
- *              end address for the range of physical addresses redirected to
- *              the SDRAM AXI master port. The value returned is always a 1 MiB
- *              aligned address.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   An bad argument was passed. Either \e addr_filt_start
- *                              or \e addr_filt_end or both are invalid addresses.
- */
-ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
-                                           uint32_t* addr_filt_end);
-
-/******************************************************************************/
-/*!
- * Set the L2 cache address filtering configuration settings.
- *
- * Address filtering start and end values must be 1 MiB aligned.
- *
- * \param       addr_filt_start
- *              The address filtering start address for the range of physical
- *              addresses redirected to the SDRAM AXI master port. Only bits
- *              [31:20] of the address are valid. Any bits outside the range
- *              [31:20] are invalid and will cause an error status to be
- *              returned.
- *              
- * \param       addr_filt_end
- *              The address filtering end address for the range of physical
- *              addresses redirected to the SDRAM AXI master port. Only bits
- *              [31:20] of the address are valid. Any bits outside the range
- *              [31:20] are invalid and will cause an error status to be
- *              returned.
- *              
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
- *                              more address arguments do not satisfy the argument
- *                              constraints.
- */
-ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
-                                           uint32_t addr_filt_end);
-
-/*! @} */
-
-/******************************************************************************/
-/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping
- *
- * This API provides management of the ACP ID Mapper that enables data coherent
- * access to the MPU address space by external masters. The set of external
- * masters include L3 master peripherals and FPGA soft IP.
- *
- * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA
- * based soft IP - to maintain data coherency with the Cortex-A9 MPCore
- * processors and the Snoop Control Unit (SCU).
- *
- * The ACP supports up to six masters. However, soft IP implemented in the FPGA
- * fabric can have a larger number of masters that need to access the ACP. The
- * ACP ID Mapper expands the number of masters able to access the ACP.  The ACP
- * ID Mapper is situated between the interconnect and the ACP of the MPU
- * subsystem. It has the following characteristics:
- * * Support for up to six concurrent ID mappings.
- * * 1 GiB coherent window into 4 GiB MPU address space
- * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU)
- *   and L2 cache.
- * 
- * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller
- * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input
- * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output
- * identifiers) required by the ACP slave port.
- *
- * The ACP ID Mapper supports the two ID mapping modes:
- * * Dynamic Mapping - In this mode an input ID is automatically mapped to an
- *   available output ID. The dynamic mode is more flexible because the hardware
- *   handles the mapping. The hardware mapping allows an output ID to be used
- *   for more than one input ID. Output IDs are assigned to input IDs on a
- *   first-come, first-served basis.
- * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs
- *   to output IDs.
- *
- * Out of the total of eight ACP output ID values, only six are available to the
- * ACP ID Mapper for remapping.  The first two output IDs (0 and 1) are
- * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the
- * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6
- * support fixed and dynamic modes of operation while output ID 7 supports
- * dynamic mode only.
- *
- * The following table summarizes the usage of the 3-bit ouput ID values by the
- * ACP ID Mapper and their settings at reset.
- *
- *  Output ID  | Usage                                             | Reset State     
- * :-----------|:--------------------------------------------------|:------------
- *         0   | Reserved for Cortex-A9 cores.                     | -               
- *         1   | Reserved for Cortex-A9 cores.                     | -               
- *         2   | Assigned to Debug Access Port (DAP) input ID at   | Fixed           
- * :           | reset. After reset, can be reconfigured to either | DAP Master
- * :           | fixed or dynamic.                                 |:
- *         3   | Configurable fixed or dynamic mode.               | Dynamic         
- *         4   | Configurable fixed or dynamic mode.               | Dynamic         
- *         5   | Configurable fixed or dynamic mode.               | Dynamic         
- *         6   | Configurable fixed or dynamic mode.               | Dynamic         
- *         7   | Dynamic mode only.                                | Dynamic         
- *
- * Where <em>Output ID</em> is the ACP ID Mapper output value that goes to the ACP.
- *
- * Additionally, for masters unable to drive the AXI user sideband signals of
- * incoming transactions, the ACP ID Mapper allows control of the AXI user
- * sideband signal values. Not all masters drive these signals, so the ACP ID
- * Mapper makes it possible to drive the 5-bit user sideband signal with either
- * a default value (in dynamic mode) or specific values (in fixed mode).
- *
- * The ACP ID Mapper can also control which 1 GiB coherent window into memory is
- * accessed by masters of the L3 interconnect. Each fixed mapping can be
- * assigned a different user sideband signal and memory window to allow specific
- * settings for different masters. All dynamic mappings share a common user
- * sideband signal and memory window setting.  One important exception, however,
- * is that the ACP ID mapper always allows user sideband signals from the
- * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured
- * user sideband value associated with the ID.
- *
- * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which
- * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows
- * transactions to be routed to different 1 GiB-sized memory views, called pages,
- * in both dynamic and fixed modes.
- *
- * See: <em>Chapter 6: Cortex-A9 Microprocessor Unit Subsystem</em> in
- * <em>Volume 3: Hard Processor System Technical Reference Manual</em> of the
- * <em>Arria V or Cyclone V Device Handbook</em> for a complete discussion of
- * the operation and restrictions on the ACP and the ACP ID Mapper.
- *
- * @{
- */
-
-/******************************************************************************/
-/*!
- * \name External Master ID Macros
- *
- * These macros define the HPS external master identifiers that are 12-bit input
- * IDs to the ACP ID Mapper. Some of the masters have a range of identifier
- * values assigned to them and are distinguished by taking a <em>(var)\</em>
- * argument.
- * @{
- */
-
-/*! Bit mask for the relevant 12 bits of an external master ID */
-#define ALT_ACP_ID_MAP_MASTER_ID_MASK           0xfff
-
-/*! Master ID for L2M0 */
-#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var)      (0x00000002 | (0x000007f8 & (var)))
-/*! Master ID for DMA */
-#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var)       (0x00000001 | (0x00000078 & (var)))
-/*! Master ID for EMAC0 */
-#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var)     (0x00000801 | (0x00000878 & (var)))
-/*! Master ID for EMAC1 */
-#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var)     (0x00000802 | (0x00000878 & (var)))
-/*! Master ID for USB0 */
-#define ALT_ACP_ID_MAP_MASTER_ID_USB0           0x00000803
-/*! Master ID for USB1 */
-#define ALT_ACP_ID_MAP_MASTER_ID_USB1           0x00000806
-/*! Master ID for NAND controller */
-#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var)      (0x00000804 | (0x00000ff8 & (var)))
-/*! Master ID for Embedded Trace Router (ETR) */
-#define ALT_ACP_ID_MAP_MASTER_ID_TMC            0x00000800
-/*! Master ID for  Debug Access Port (DAP) */
-#define ALT_ACP_ID_MAP_MASTER_ID_DAP            0x00000004
-/*! Master ID for  SD/MMC controller */
-#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC          0x00000805
-/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */
-#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var)       (0x00000000 | (0x000007f8 & (var)))
-/*! @} */
-
-/******************************************************************************/
-/*!
-  * This type defines the enumerations 3-bit output ids to ACP ID mapper.
- */
-typedef enum ALT_ACP_ID_OUTPUT_ID_e
-{
-    ALT_ACP_ID_OUT_FIXED_ID_2 = 2,  /*!< Assigned to the input ID of the DAP at reset. 
-                                     *   After reset, can be either fixed or dynamic, 
-                                     *   programmed by software.
-                                     */
-    ALT_ACP_ID_OUT_DYNAM_ID_3 = 3,  /*!< Fixed or dynamic, programmed by software output id */
-    ALT_ACP_ID_OUT_DYNAM_ID_4 = 4,  /*!< Fixed or dynamic, programmed by software output id */
-    ALT_ACP_ID_OUT_DYNAM_ID_5 = 5,  /*!< Fixed or dynamic, programmed by software output id */
-    ALT_ACP_ID_OUT_DYNAM_ID_6 = 6,  /*!< Fixed or dynamic, programmed by software output id */
-    ALT_ACP_ID_OUT_DYNAM_ID_7 = 7   /*!< Dynamic mapping only */
-} ALT_ACP_ID_OUTPUT_ID_t;
-
-/*!
- * This type defines the enumerations used to specify the 1 GiB page view of the
- * MPU address space used by an ACP ID mapping configuration.
- */
-typedef enum ALT_ACP_ID_MAP_PAGE_e
-{
-    ALT_ACP_ID_MAP_PAGE_0 = 0,  /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */
-    ALT_ACP_ID_MAP_PAGE_1 = 1,  /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */
-    ALT_ACP_ID_MAP_PAGE_2 = 2,  /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */
-    ALT_ACP_ID_MAP_PAGE_3 = 3   /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */
-} ALT_ACP_ID_MAP_PAGE_t;
-
-/******************************************************************************/
-/*!
- * Configure a fixed ACP ID mapping for read transactions originating from
- * external masters identified by \e input_id. The \e input_id value is
- * translated to the specified 3-bit \e output_id required by the ACP slave
- * port.
- *
- * \param       input_id
- *              The 12 bit external master ID originating read transactions
- *              targeted for ID translation. Valid argument range must be 0 <=
- *              \e output_id <= 4095.
- *
- * \param       output_id
- *              The 3-bit output ID value the ACP ID Mapper translates read
- *              transactions identified by \e input_id to. This is the value
- *              propogated to the ACP slave port.  Valid argument values must be
- *              0 <= \e output_id <= 7.
- *
- * \param       page
- *              The MPU address space page view to use for the ACP window used
- *              by the ID tranlation mapping.
- *
- * \param       aruser
- *              The 5-bit AXI ARUSER read user sideband signal value to use for
- *              masters unable to drive the AXI user sideband signals.  Valid
- *              argument range is 0 <= \e aruser <= 31.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
- *                              more of the \e input_id, and/or \e output_id
- *                              arguments violates its range constraint.
- * \retval      ALT_E_BAD_ARG   The \e page argument is invalid.
- */
-ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
-                                              const uint32_t output_id,
-                                              const ALT_ACP_ID_MAP_PAGE_t page,
-                                              const uint32_t aruser);
-
-/******************************************************************************/
-/*!
- * Configure a fixed ACP ID mapping for write transactions originating from
- * external masters identified by \e input_id. The \e input_id value is
- * translated to the specified 3-bit \e output_id required by the ACP slave
- * port.
- *
- * \param       input_id
- *              The 12 bit external master ID originating write transactions
- *              targeted for ID translation. Valid argument range must be 0 <=
- *              \e output_id <= 4095.
- *
- * \param       output_id
- *              The 3-bit output ID value the ACP ID Mapper translates write
- *              transactions identified by \e input_id to. This is the value
- *              propogated to the ACP slave port.  Valid argument values must be
- *              0 <= \e output_id <= 7.
- *
- * \param       page
- *              The MPU address space page view to use for the ACP window used
- *              by the ID tranlation mapping.
- *
- * \param       awuser
- *              The 5-bit AXI AWUSER write user sideband signal value to use for
- *              masters unable to drive the AXI user sideband signals.  Valid
- *              argument range is 0 <= \e awuser <= 31.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
- *                              more of the \e input_id, and/or \e output_id
- *                              arguments violates its range constraint.
- * \retval      ALT_E_BAD_ARG   The \e page argument is invalid.
- */
-ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
-                                               const uint32_t output_id,
-                                               const ALT_ACP_ID_MAP_PAGE_t page,
-                                               const uint32_t awuser);
-
-/******************************************************************************/
-/*!
- * Configure the designated 3-bit output ID as an available identifier resource
- * for use by the dynamic ID mapping function of the ACP ID Mapper for read
- * transactions. The \e output_id value is available for dynamic assignment to
- * external master read transaction IDs that do not have an explicit fixed ID
- * mapping.
- *
- * \param       output_id
- *              The 3-bit output ID value designated as an available ID for use
- *              by the dynamic mapping function of the ACP ID Mapper. The \e
- *              ouput_id value is used exclusively for dynamic ID mapping until
- *              reconfigured as a fixed ID mapping by a call to
- *              alt_acp_id_map_fixed_read_set().  Valid argument values must be
- *              0 <= \e output_id <= 7.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint.
- */
-ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id);
-
-/******************************************************************************/
-/*!
- * Configure the designated 3-bit output ID as an available identifier resource
- * for use by the dynamic ID mapping function of the ACP ID Mapper for write
- * transactions. The \e output_id value is available for dynamic assignment to
- * external master write transaction IDs that do not have an explicit fixed ID
- * mapping.
- *
- * \param       output_id
- *              The 3-bit output ID value designated as an available ID for use
- *              by the dynamic mapping function of the ACP ID Mapper. The \e
- *              ouput_id value is used exclusively for dynamic ID mapping until
- *              reconfigured as a fixed ID mapping by a call to
- *              alt_acp_id_map_fixed_write_set().  Valid argument values must be
- *              0 <= \e output_id <= 7.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint.
- */
-ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id);
-
-/******************************************************************************/
-/*!
- * Configure the page and user read sideband signal options that are applied to
- * all read transactions that have their input IDs dynamically mapped.
- *
- * \param       page
- *              The MPU address space page view to use for the ACP window used
- *              by the dynamic ID tranlation mapping.
- *
- * \param       aruser
- *              The 5-bit AXI ARUSER read user sideband signal value to use for
- *              masters unable to drive the AXI user sideband signals.  Valid
- *              argument range is 0 <= \e aruser <= 31.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
- *                              more of the \e page and/or \e aruser
- *                              arguments violates its range constraint.
- * \retval      ALT_E_BAD_ARG   The \e mid argument is not a valid master 
- *                              identifier.
- */
-ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
-                                                        const uint32_t aruser);
-
-/******************************************************************************/
-/*!
- * Configure the page and user write sideband signal options that are applied to
- * all write transactions that have their input IDs dynamically mapped.
- *
- * \param       page
- *              The MPU address space page view to use for the ACP window used
- *              by the dynamic ID tranlation mapping.
- *
- * \param       awuser
- *              The 5-bit AXI AWUSER write user sideband signal value to use for
- *              masters unable to drive the AXI user sideband signals.  Valid
- *              argument range is 0 <= \e aruser <= 31.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. One or
- *                              more of the \e page and/or \e awuser
- *                              arguments violates its range constraint.
- * \retval      ALT_E_BAD_ARG   The \e mid argument is not a valid master 
- *                              identifier.
- */
-ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
-                                                         const uint32_t awuser);
-
-/******************************************************************************/
-/*!
- * Return the current read transaction mapping configuration used by the ACP ID
- * Mapper for the specified output ID.
- *
- * If \e output_id is configured as a fixed mapping then \b true is returned in
- * the \e fixed output parameter and the translation mapping options configured
- * for that \e output_id are returned in the other output parameters.
- *
- * If \e output_id is configured as a dynamic mapping then \b false is returned
- * in the \e fixed output parameter and the translation mapping options
- * configured for all dynamically remapped output IDs are returned in the other
- * output parameters.
- *
- * \param       output_id
- *              The output ID to return the mapping configuration for. 0 <= \e
- *              output_id <= 7.
- *
- * \param       fixed
- *              [out] Set to \b true if the specified \e output_id is a fixed ID
- *              mapping configuration. Set to \b false if the mapping
- *              configuration is dynamic.
- *
- * \param       input_id
- *              [out] The input ID of the external master that a fixed ID
- *              mapping is applied to for the \e output_id. If \e fixed is \b
- *              false then this output parameter is set to 0 and its value
- *              should be considered as not applicable.
- *
- * \param       page
- *              [out] The MPU address space page view used by the mapping
- *              configuration.
- *
- * \param       aruser
- *              [out] The 5-bit AXI ARUSER read user sideband signal value used
- *              by the mapping configuration when masters are unable to drive
- *              the AXI user sideband signals.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. The \e 
- *                              output_id argument violates its range constraint.
- */
-ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
-                                                bool* fixed,
-                                                uint32_t* input_id,
-                                                ALT_ACP_ID_MAP_PAGE_t* page,
-                                                uint32_t* aruser);
-
-/******************************************************************************/
-/*!
- * Return the current write transaction mapping configuration used by the ACP ID
- * Mapper for the specified output ID.
- *
- * If \e output_id is configured as a fixed mapping then \b true is returned in
- * the \e fixed output parameter and the translation mapping options configured
- * for that \e output_id are returned in the other output parameters.
- *
- * If \e output_id is configured as a dynamic mapping then \b false is returned
- * in the \e fixed output parameter and the translation mapping options
- * configured for all dynamically remapped output IDs are returned in the other
- * output parameters.
- *
- * \param       output_id
- *              The output ID to return the mapping configuration for. 0 <= \e
- *              output_id <= 7.
- *
- * \param       fixed
- *              [out] Set to \b true if the specified \e output_id is a fixed ID
- *              mapping configuration. Set to \b false if the mapping
- *              configuration is dynamic.
- *
- * \param       input_id
- *              [out] The input ID of the external master that a fixed ID
- *              mapping is applied to for the \e output_id. If \e fixed is \b
- *              false then this output parameter is set to 0 and its value
- *              should be considered as not applicable.
- *
- * \param       page
- *              [out] The MPU address space page view used by the mapping
- *              configuration.
- *
- * \param       awuser
- *              [out] The 5-bit AXI AWUSER write user sideband signal value used
- *              by the mapping configuration when masters are unable to drive
- *              the AXI user sideband signals.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_RESERVED  The argument value is reserved or unavailable.
- * \retval      ALT_E_ARG_RANGE An argument violates a range constraint. The \e 
- *                              output_id argument violates its range constraint.
- */
-ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
-                                                 bool* fixed,
-                                                 uint32_t* input_id,
-                                                 ALT_ACP_ID_MAP_PAGE_t* page,
-                                                 uint32_t* awuser);
-
-/*! @} */
-
-/*! @} */
-
-#endif  /* __ASSEMBLY__ */
-
-#ifdef __cplusplus
-}
-#endif  /* __cplusplus */
-#endif  /* __ALT_ADDRESS_SPACE_H__ */

bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h

@@ -1,970 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
- *
- * Copyright 2013 Altera Corporation. All Rights Reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * 
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- * 
- ******************************************************************************/
-
-#ifndef __ALT_CACHE_H__
-#define __ALT_CACHE_H__
-
-#include "hwlib.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*!
- * \addtogroup CACHE_MGR Cache Management API
- *
- * This module defines the cache management API for enabling and disabling L1
- * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1
- * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform
- * cache maintenance operations on these caches. This includes the following
- * operations:
- *  * Invalidate: Marks the cache line as being invalid, freeing up the space
- *    to cache other data. All APIs which enable caches invalidates the memory
- *    before being enabling the cache.
- *  * Clean: If the cache line is dirty, it synchronizes the cache line data
- *    with the upper level memory system and marks that line as clean. All APIs
- *    which disable caches cleans the memory before disabling the cache.
- *  * Purge: A term used in this API as a short form for clean and invalidate.
- *    This operation cleans and invalidates a cache line in that order, as a
- *    single command to the cache controller.
- *
- * The following reference materials were used in the design of this API:
- *  * ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition
- *  * Cortex™-A9 Technical Reference Manual
- *  * Cortex™-A9 MPCore Technical Reference Manual
- *  * CoreLink™ Level 2 Cache Controller L2C-310 Technical Reference
- *    Manual
- *
- * @{
- */
-
-/*!
- * \addtogroup CACHE_SYS System Level Cache Management API
- *
- * This API group provides cache maintenance operations which affects multiple
- * cache levels.
- *
- * The enable and disable functions enables and disables all caches in the
- * system respectively. For caches shared by the CPU core(s), particularly the
- * L2 cache, once that cache is enabled or disabled it will not be invalidated
- * or cleaned again respectively. This allows the safe system-wide enable and
- * disable to be used in single-core and multi-core scenarios.
- *
- * For cache maintenance operations, this API implements the procedures
- * outlined in the L2C-310 Technical Reference Manual, section 3.3.10,
- * subsection "System cache maintenance considerations". This allows for a
- * convenient way to invalidate, clean, or clean and invalidate cache data from
- * the L1 to L2 to L3 while avoiding any potential race conditions in
- * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is
- * set in "non-exclusive" mode. This means a segment of data can reside in both
- * the L1 and L2 simultaneously. This is the default mode for caches in the
- * system.
- *
- * The current implementation of the system cache APIs assumes that the MMU is
- * configured with a flat memory mapping or that every virtual address matches
- * perfectly with the physical address. This restriction may be lifted in a
- * future release of the cache API implementation.
- *
- * @{
- */
-
-/*!
- * Enables support for a non-flat virtual memory. A flat virtual memory is
- * where every virtual address matches exactly to the physical address, making
- * the virtual to physical translation trivial. Adding support for non-flat
- * adds some overhead for the VA to PA translation and error detection.
- *
- * To enable non-flat virtual memory support, defined
- * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling
- * HWLibs.
- */
-#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY
-#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0)
-#endif
-
-/*!
- * This is the system wide cache line size, given in bytes.
- */
-#define ALT_CACHE_LINE_SIZE         32
-
-/*!
- * Enables all caches and features which improve reliability and speed on all
- * cache controllers visible to the current CPU core. This includes parity
- * error detection. Cache controllers visible to multiple CPU cores, for
- * example the L2, will first be checked to be disabled before being enabled.
- * All necessary cache maintenance operations will be done automatically.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_system_enable(void);
-
-/*!
- * Disables all cache controllers visible to the current CPU core. Cache
- * controllers visible to multiple CPU cores, for example the L2, will first
- * be checked to be enabled before being disabled. All necessary cache
- * maintenance operations will be done automatically.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_system_disable(void);
-
-/*!
- * Invalidates the specified contents of all cache levels visible to the
- * current CPU core for the given memory segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * The following pseudocode outlines the operations carried out by this
- * function:
- *  -# L2 invalidate address(es)
- *  -# L2 cache sync
- *  -# L1 invalidate address(es)
- *  -# DSB instruction
- *
- * The current implementation of the system cache APIs assumes that the MMU is
- * configured with a flat memory mapping or that every virtual address matches
- * perfectly with the physical address. This restriction may be lifted in a
- * future release of the cache API implementation.
- *
- * \param       vaddress
- *              The virtual address of the memory segment to be invalidated.
- *
- * \param       length
- *              The length of the memory segment to be invalidated.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length);
-
-/*!
- * Cleans the specified contents of all cache levels visible to the current
- * CPU core for the given memory segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * The following pseudocode outlines the operations carried out by this
- * function:
- *  -# L1 clean address(es)
- *  -# DSB instruction
- *  -# L2 clean address(es)
- *  -# L2 cache sync
- *
- * The current implementation of the system cache APIs assumes that the MMU is
- * configured with a flat memory mapping or that every virtual address matches
- * perfectly with the physical address. This restriction may be lifted in a
- * future release of the cache API implementation.
- *
- * \param       vaddress
- *              The virtual address of the memory segment to be cleaned.
- *
- * \param       length
- *              The length of the memory segment to be cleaned.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length);
-
-/*!
- * Cleans and invalidates the specified contents of all cache levels visible
- * to the current CPU core for the given memory segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * The following pseudocode outlines the operations carried out by this
- * function:
- *  -# L1 clean address(es)
- *  -# DSB instruction
- *  -# L2 clean and invalidate address(es)
- *  -# L2 cache sync
- *  -# L1 invalidate address(es)
- *  -# DSB instruction
- *
- * The current implementation of the system cache APIs assumes that the MMU is
- * configured with a flat memory mapping or that every virtual address matches
- * perfectly with the physical address. This restriction may be lifted in a
- * future release of the cache API implementation.
- *
- * \param       vaddress
- *              The virtual address of the memory segment to be purged.
- *
- * \param       length
- *              The length of the memory segment to be purged.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length);
-
-/*!
- * @}
- */
-
-/*!
- * \addtogroup CACHE_L1 L1 Cache Management API
- *
- * This API group provides functions to interact with various components of the
- * L1 cache on the SoCFPGA. This includes the following cache components:
- *  * Instruction Cache
- *  * Data Cache
- *  * Parity error detection
- *  * Dynamic branch prediction
- *  * Data prefetching
- *
- * The API within this group only affects the L1 cache on the current CPU. To
- * interact the L1 cache on another CPU, the API must be called from that other
- * CPU.
- *
- * With respect to bring-up, the L1 and L2 cache controller setups are fully
- * independent. The L2 can be setup at any time, before or after the L1 is setup.
- * \internal
- * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up".
- * \endinternal
- *
- * @{
- */
-
-/*!
- * Enables all L1 caches and features on the current CPU core. This includes
- * the instruction cache, data cache, parity error detection, branch target
- * address cache, global history buffer, and data prefetching. All necessary
- * maintenance tasks will be taken care of.
- *
- * This function should not be mixed with other L1 cache related functions
- * which enable or disable caches individually.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_enable_all(void);
-
-/*!
- * Disables all L1 caches and features on the current CPU core. This includes
- * the instruction cache, data cache, parity error detection, branch target
- * address cache, global history buffer, and data prefetching. All necessary
- * maintenance tasks will be taken care of.
- *
- * This function should not be mixed with other L1 cache related functions
- * which enable or disable caches individually.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_disable_all(void);
-
-/*!
- * Enables the L1 instruction cache on the current CPU core. If the cache is
- * already enabled, nothing is done. Otherwise the instruction cache is first
- * invalidated before being enabled.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_instruction_enable(void);
-
-/*!
- * Disables the L1 instruction cache on the current CPU core.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_instruction_disable(void);
-
-/*!
- * Returns \b true when the L1 instruction cache is enabled and \b false when
- * it is disabled on the current CPU core.
- *
- * \retval      true            The L1 instruction cache is enabled.
- * \retval      false           The L1 instruction cache is disabled.
- */
-bool alt_cache_l1_instruction_is_enabled(void);
-
-/*!
- * Invalidates the contents of the L1 instruction cache on the current CPU
- * core.
- *
- * Normally this is done automatically as part of
- * alt_cache_l1_instruction_enable(), but in certain circumstances it may be
- * necessary to invalidate it manually. An example of this situation is when
- * the address space is remapped and the processor executes instructions from
- * the new memory area.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void);
-
-/*!
- * Enables the L1 data cache on the current CPU core.
- *
- * If the cache is already enabled nothing is done. Otherwise the data cache is
- * first invalidated before being enabled.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_data_enable(void);
-
-/*!
- * Disables the L1 data cache on the current CPU core.
- *
- * If the cache is already disabled nothing is done. Otherwise the data cache
- * is first cleaned before being disabled.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_data_disable(void);
-
-/*!
- * Returns \b true when the L1 data cache is enabled and \b false when it is
- * disabled on the current CPU core.
- *
- * \retval      true            The L1 data cache is enabled.
- * \retval      false           The L1 data cache is disabled.
- */
-bool alt_cache_l1_data_is_enabled(void);
-
-/*!
- * Invalidates the specified contents of the L1 data cache on the current CPU
- * core for the given memory segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * \param       vaddress
- *              The virtual address of the memory segment to be invalidated.
- *
- * \param       length
- *              The length of the memory segment to be invalidated.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- */
-ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length);
-
-/*!
- * Invalidates the entire contents of the L1 data cache on the current CPU
- * core.
- *
- * Normally this is done automatically as part of alt_cache_l1_data_enable(),
- * but in certain circumstances it may be necessary to invalidate it manually.
- * An example of this situation is when the address space is remapped and the
- * processor accesses memory from the new memory area.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void);
-
-/*!
- * Cleans the specified contents of the L1 data cache on the current CPU core
- * for the given memory segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * \param       vaddress
- *              The virtual address of the memory segment to be cleaned.
- *
- * \param       length
- *              The length of the memory segment to be cleaned.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- */
-ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length);
-
-/*!
- * Cleans the entire L1 data cache for the current CPU core.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_data_clean_all(void);
-
-/*!
- * Cleans and invalidates the specified contents of the L1 data cache on the
- * current CPU core for the given memory segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * Normally this is done automatically as part of alt_cache_l1_data_disable(),
- * but in certain circumstances it may be necessary to purged it manually.
- * An example of this situation is when the address space is remapped and the
- * processor accesses memory from the new memory area.
- *
- * \param       vaddress
- *              The virtual address of the memory segment to be purged.
- *
- * \param       length
- *              The length of the memory segment to be purged.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- */
-ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length);
-
-/*!
- * Cleans and invalidates the entire L1 data cache for the current CPU core.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_data_purge_all(void);
-
-/*!
- * Enables the parity error detection feature in the L1 caches on the current
- * CPU core.
- *
- * Ideally parity should be enabled before any L1 caches are enabled. If the
- * instruction, data, and / or dynamic branch predictor caches are already
- * enabled, they will first be cleaned (if needed) and disabled before parity
- * is enabled in hardware. Afterwards, the affected caches will be invalidated
- * and enabled.
- *
- * Parity and TLB interaction deserves special attention. The TLB is considered
- * to be a L1 cache but is enabled when the MMU, which is grouped in another
- * API, is enabled. Due to the system-wide influence of the MMU, it cannot be
- * disabled and enabled with impunity as the other L1 caches, which are
- * designed to operate as transparently as possible. Thus parity error
- * detection must be enabled before the L1 TLB cache, and by extension the MMU,
- * is enabled.
- *
- * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt
- * for the current CPU core must be enabled using the interrupt controller API.
- * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error
- * is detected while the other PARITYFAIL interrupts are for parity errors in a
- * specific memory. Refer to the interrupt controller API for more details
- * about programming the interrupt controller.
- *
- * In the event of a parity error is detected, the appropriate CPU parity
- * interrupt will be raised. CPU parity interrupts are all edge triggered and
- * are cleared by acknowledging them in the interrupt controller API.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_parity_enable(void);
-
-/*!
- * Disables parity error detection in the L1 caches.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_parity_disable(void);
-
-/*!
- * Returns \b true when parity error detection is enabled and \b false when it
- * is disabled on the current CPU core.
- *
- * \retval      true            Parity error detection for L1 caches is
- *                              enabled.
- * \retval      false           Parity error detection for L1 caches is
- *                              disabled.
- */
-bool alt_cache_l1_parity_is_enabled(void);
-
-/*!
- * Enables the dynamic branch predictor features on the current CPU core.
- *
- * This operation enables both the Branch Target Address Cache (BTAC) and
- * the Global History Buffer (GHB). Affected caches are automatically
- * invalidated before use.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_branch_enable(void);
-
-/*!
- * Disables the dynamic branch predictor features on the current CPU core.
- *
- * This operation disables both the Branch Target Address Cache (BTAC) and
- * the Global History Buffer (GHB).
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_branch_disable(void);
-
-/*!
- * Returns \b true when both the dynamic predictor features are enabled and
- * \b false when they are disabled on the current CPU core.
- *
- * \retval      true            The L1 branch predictor caches are all enabled.
- * \retval      false           Some or all L1 branch predictor caches are
- *                              disabled.
- */
-bool alt_cache_l1_branch_is_enabled(void);
-
-/*!
- * Invalidates the dynamic branch predictor feature caches on the current CPU
- * core.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void);
-
-/*!
- * Enables the L1 cache data prefetch feature on the current CPU core.
- *
- * This allows data to be prefetched into the data cache before it is to be
- * used. For example in a loop the current iteration may want to preload the
- * data which will be used in the next teration. This is done by using the PLD
- * instructions.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void);
-
-/*!
- * Disables the L1 cache data prefetch feature on the current CPU core.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void);
-
-/*!
- * Returns \b true if the L1 cache data prefetch feature is enabled and
- * \b false if it is disabled on the current CPU core.
- *
- * \retval      true            The L1 data cache prefetch feature is enabled.
- * \retval      false           The L1 data cache prefetch feature is disabled.
- */
-bool alt_cache_l1_prefetch_is_enabled(void);
-
-/*!
- * @}
- */
-
-/*!
- * \addtogroup CACHE_L2 L2 Cache Management API
- *
- * This API group provides functions to interact with various features of the
- * L2 cache on the SoCFPGA. This includes the following features:
- *  * L2 cache
- *  * Parity error detection
- *  * Data prefetching
- *  * Interrupt Management
- *
- * \internal
- * Additional features that may be implemented in the future:
- *  * Lockdown
- *  * Event counter
- * \endinternal
- *
- * The API within this group affects the L2 cache which is visible to all CPUs
- * on the system.
- *
- * With respect to bring-up, the L1 and L2 cache controller setups are fully
- * independent. The L2 can be setup at any time, before or after the L1 is setup.
- * \internal
- * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up".
- * \endinternal
- *
- * @{
- */
-
-/*!
- * Initializes the L2 cache controller.
- *
- * \retval      ALT_E_SUCCESS   Successful status.
- * \retval      ALT_E_ERROR     Details about error status code
- */
-ALT_STATUS_CODE alt_cache_l2_init(void);
-
-/*!
- * Uninitializes the L2 cache controller.
- *
- * \retval      ALT_E_SUCCESS   Successful status.
- * \retval      ALT_E_ERROR     Details about error status code
- */
-ALT_STATUS_CODE alt_cache_l2_uninit(void);
-
-/*!
- * Enables the L2 cache features for data and instruction prefetching.
- *
- * Prefetching can be enabled or disabled while the L2 cache is enabled.
- * \internal
- * Source: Use the Prefetch Control Register.
- * \endinternal
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void);
-
-/*!
- * Disables the L2 cache features for data and instruction prefetching.
- *
- * Prefetching can be enabled or disabled while the L2 cache is enabled.
- * \internal
- * Source: Use the Prefetch Control Register.
- * \endinternal
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void);
-
-/*!
- * Returns \b true if either L2 cache data or instruction prefetch features are
- * enabled and \b false if no prefetching features are enabled.
- *
- * \retval      true            The L2 data and instruction prefetch features
- *                              are enabled.
- * \retval      false           Some L2 data and instruction prefetch features
- *                              are disabled.
- */
-bool alt_cache_l2_prefetch_is_enabled(void);
-
-/*!
- * Enables parity error detection in the L2 cache.
- *
- * Ideally parity should be enabled before the L2 cache is enabled. If the
- * cache is already enabled, it will first be cleaned and disabled before
- * parity is enabled in hardware. Afterwards, the cache will be invalidated and
- * enabled.
- *
- * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or
- * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is
- * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt
- * must be enabled using the interrupt controller API. Refer to the interrupt
- * controller API for more details about programming the interrupt controller.
- *
- * In the event of a parity error is detected, the appropriate L2 cache parity
- * interrupt will be raised. To clear the parity interrupt(s), the appropriate
- * L2 cache parity interrupt must be cleared by calling
- * alt_cache_l2_int_status_clear().
- *
- * For ECC support, refer to the ECC related API documentation for more
- * information.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_parity_enable(void);
-
-/*!
- * Disables parity error detection in the L2 cache.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_parity_disable(void);
-
-/*!
- * Returns \b true when parity error detection is enabled and \b false when it
- * is disabled.
- *
- * \retval      true            The L2 cache parity error detection feature is
- *                              enabled.
- * \retval      false           The L2 cache parity error detection feature is
- *                              disabled.
- */
-bool alt_cache_l2_parity_is_enabled(void);
-
-/*!
- * Enables the L2 cache.
- *
- * If the L2 cache is already enabled, nothing is done. Otherwise the entire
- * contents of the cache is first invalidated before being enabled.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_enable(void);
-
-/*!
- * Disables the L2 cache.
- *
- * If the L2 cache is already disabled, nothing is done. Otherwise the entire
- * contents of the cache is first cleaned before being disabled.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_disable(void);
-
-/*!
- * Returns \b true when the L2 cache is enabled and \b false when it is
- * disabled.
- *
- * \retval      true            The L2 cache is enabled.
- * \retval      false           The L2 cache is disabled.
- */
-bool alt_cache_l2_is_enabled(void);
-
-/*!
- * Flushes the L2 cache controller hardware buffers.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_l2_sync(void);
-
-/*!
- * Invalidates the specified contents of the L2 cache for the given memory
- * segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * \param       paddress
- *              The physical address of the memory segment to be invalidated.
- *
- * \param       length
- *              The length of the memory segment to be invalidated.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length);
-
-/*!
- * Invalidates th entire contents of the L2 cache.
- *
- * Normally this is done automatically as part of alt_cache_l2_enable(), but
- * in certain circumstances it may be necessary to invalidate it manually. An
- * example of this situation is when the address space is remapped and the
- * processor accesses memory from the new memory area.
-
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_l2_invalidate_all(void);
-
-/*!
- * Cleans the specified contents of the L2 cache for the given memory segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * \param       paddress
- *              The physical address of the memory segment to be cleaned.
- *
- * \param       length
- *              The length of the memory segment to be cleaned.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length);
-
-/*!
- * Cleans the entire L2 cache. All L2 cache controller interrupts will be
- * temporarily disabled while the clean operation is in progress and restored
- * once the it is finished.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_l2_clean_all(void);
-
-/*!
- * Cleans and invalidates the specified contents of the L2 cache for the
- * given memory segment.
- *
- * The memory segment address and length specified must align to the
- * characteristics of the cache line. This means the address and length must be
- * multiples of the cache line size. To determine the cache line size, use the
- * \b ALT_CACHE_LINE_SIZE macro.
- *
- * \param       paddress
- *              The physical address of the memory segment to be purged.
- *
- * \param       length
- *              The length of the memory segment to be purged.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_BAD_ARG   The memory segment is invalid.
- */
-ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length);
-
-/*!
- * Cleans and invalidates the entire L2 cache. All L2 cache controller
- * interrupts will be temporarily disabled while the clean and invalidate
- * operation is in progress and restored once the it is finished.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- * \retval      ALT_E_TMO       The memory operation timed out.
- */
-ALT_STATUS_CODE alt_cache_l2_purge_all(void);
-
-/*!
- * This type definition enumerates all the interrupt conditions that can be
- * generated by the L2 cache controller as register mask values.
- */
-enum ALT_CACHE_L2_INTERRUPT_e
-{
-    /*! Decode error received on the master ports from L3. */
-    ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8,
-
-    /*! Slave error received on the master ports from L3.  */
-    ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7,
-
-    /*! Error on the L2 data RAM read.                     */
-    ALT_CACHE_L2_INTERRUPT_ERRRD  = 1 << 6,
-
-    /*! Error on the L2 tag RAM read.                      */
-    ALT_CACHE_L2_INTERRUPT_ERRRT  = 1 << 5,
-
-    /*! Error on the L2 data RAM write.                    */
-    ALT_CACHE_L2_INTERRUPT_ERRWD  = 1 << 4,
-
-    /*! Error on the L2 tag RAM write.                     */
-    ALT_CACHE_L2_INTERRUPT_ERRWT  = 1 << 3,
-
-    /*! Parity error on the L2 data RAM read.              */
-    ALT_CACHE_L2_INTERRUPT_PARRD  = 1 << 2,
-
-    /*! Parity error on the L2 tag RAM read.               */
-    ALT_CACHE_L2_INTERRUPT_PARRT  = 1 << 1,
-
-    /*! Event counter overflow or increment.               */
-    ALT_CACHE_L2_INTERRUPT_ECNTR  = 1 << 0
-};
-typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t;
-
-/*!
- * Enables the L2 cache controller interrupts for the specified set of
- * condition(s).
- *
- * \param       interrupt
- *              A register mask of the selected L2 cache controller
- *              interrupting conditions.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt);
-
-/*!
- * Disables the L2 cache controller interrupts for the specified set of
- * condition(s).
- *
- * \param       interrupt
- *              A register mask of the selected L2 cache controller
- *              interrupting conditions.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt);
-
-/*!
- * Gets the condition(s) causing the L2 cache controller to interrupt as a
- * register mask.
- *
- * \returns     A register mask of the currently asserted and enabled
- *              conditions resulting in an interrupt being generated.
- */
-uint32_t alt_cache_l2_int_status_get(void);
-
-/*!
- * Clears the specified conditon(s) causing the L2 cache controller to
- * interrupt as a mask. Condition(s) specified which are not causing an
- * interrupt or condition(s) specified which are not enabled are ignored.
- *
- * \param       interrupt
- *              A register mask of the selected L2 cache controller
- *              interrupting conditions.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt);
-
-/*!
- * @}
- */
-
-/*!
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALT_CACHE_H__ */

bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h

@@ -1,120 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
- *
- * Copyright 2013 Altera Corporation. All Rights Reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- ******************************************************************************/
-
-/*!
- * \file
- *
- * Contains the definition of an opaque data structure that contains raw
- * configuration information for a clock group.
- */
-
-#ifndef __ALT_CLK_GRP_H__
-#define __ALT_CLK_GRP_H__
-
-#include "hwlib.h"
-#include "socal/alt_clkmgr.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-/*!
- * This type definition enumerates the clock groups
- */
-typedef enum ALT_CLK_GRP_e
-{
-    ALT_MAIN_PLL_CLK_GRP,        /*!< Main PLL clock group */
-
-    ALT_PERIPH_PLL_CLK_GRP,      /*!< Peripheral PLL clock group */
-
-    ALT_SDRAM_PLL_CLK_GRP        /*!< SDRAM PLL clock group */
-
-} ALT_CLK_GRP_t;
-
-/*!
- * This type definition defines an opaque data structure for holding the
- * configuration settings for a complete clock group.
- */
-typedef struct ALT_CLK_GROUP_RAW_CFG_s
-{
-    uint32_t      verid;     /*!< SoC FPGA version identifier. This field
-                              *   encapsulates the silicon identifier and
-                              *   version information associated with this
-                              *   clock group configuration. It is used to
-                              *   assert that this clock group configuration
-                              *   is valid for this device. */
-
-    uint32_t      siliid2;   /*!< Reserved register - reserved for future
-                              *   device IDs or capability flags. */
-
-    ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */
-
-    /*!
-     * This union holds the register values for configuration of the set of
-     * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
-     * identifies the valid clock group union data member.
-     */
-    union ALT_CLK_GROUP_RAW_CFG_u
-    {
-        /*! Clock group configuration for Main PLL group. */
-        union
-        {
-            ALT_CLKMGR_MAINPLL_t     fld; /*!< Field access. */
-            ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */
-        } mainpllgrp;
-
-        /*! Clock group configuration for Peripheral PLL group. */
-        union
-        {
-            ALT_CLKMGR_PERPLL_t     fld; /*!< Field access. */
-            ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */
-        } perpllgrp;
-
-        /*! Clock group configuration for SDRAM PLL group. */
-        union
-        {
-            ALT_CLKMGR_SDRPLL_t     fld; /*!< Field access. */
-            ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */
-        } sdrpllgrp;
-
-    } clkgrp;
-} ALT_CLK_GROUP_RAW_CFG_t;
-
-#ifdef __cplusplus
-}
-#endif  /* __cplusplus */
-#endif  /* __ALT_CLK_GRP_H__ */

bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h

@@ -1,168 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
- *
- * Copyright 2013 Altera Corporation. All Rights Reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * 
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- * 
- ******************************************************************************/
-
-#ifndef __ALT_DMA_COMMON_H__
-#define __ALT_DMA_COMMON_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-/*!
- * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions
- *
- * This module contains the common definitions for the DMA controller related
- * APIs.
- *
- * @{
- */
-
-/*!
- * This type definition enumerates the DMA controller channel threads.
- */
-typedef enum ALT_DMA_CHANNEL_e
-{
-    ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */
-    ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */
-    ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */
-    ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */
-    ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */
-    ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */
-    ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */
-    ALT_DMA_CHANNEL_7 = 7  /*!< DMA Channel Thread 7 */
-}
-ALT_DMA_CHANNEL_t;
-
-/*!
- * This type definition enumerates the SoC system peripherals implementing the
- * required request interface that enables direct DMA transfers to/from the
- * device.
- *
- * FPGA soft IP interface to the DMA are required to comply with the Synopsys
- * protocol.
- *
- * Request interface numbers 4 through 7 are multiplexed between the CAN
- * controllers and soft logic implemented in the FPGA fabric. The selection
- * between the CAN controller and FPGA interfaces is determined at DMA
- * initialization.
- */
-typedef enum ALT_DMA_PERIPH_e
-{
-    ALT_DMA_PERIPH_FPGA_0             = 0,  /*!< FPGA soft IP interface 0 */
-    ALT_DMA_PERIPH_FPGA_1             = 1,  /*!< FPGA soft IP interface 1 */
-    ALT_DMA_PERIPH_FPGA_2             = 2,  /*!< FPGA soft IP interface 2 */
-    ALT_DMA_PERIPH_FPGA_3             = 3,  /*!< FPGA soft IP interface 3 */
-
-    ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4,  /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */
-    ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5,  /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */
-    ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6,  /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */
-    ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7,  /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */
-
-    ALT_DMA_PERIPH_FPGA_4             = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
-    ALT_DMA_PERIPH_FPGA_5             = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
-    ALT_DMA_PERIPH_FPGA_6             = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
-    ALT_DMA_PERIPH_FPGA_7             = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
-
-    ALT_DMA_PERIPH_CAN0_IF1           = 4,  /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
-    ALT_DMA_PERIPH_CAN0_IF2           = 5,  /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
-    ALT_DMA_PERIPH_CAN1_IF1           = 6,  /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
-    ALT_DMA_PERIPH_CAN1_IF2           = 7,  /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
-
-    ALT_DMA_PERIPH_I2C0_TX            = 8,  /*!< I<sup>2</sup>C 0 TX */
-    ALT_DMA_PERIPH_I2C0_RX            = 9,  /*!< I<sup>2</sup>C 0 RX */
-    ALT_DMA_PERIPH_I2C1_TX            = 10, /*!< I<sup>2</sup>C 1 TX */
-    ALT_DMA_PERIPH_I2C1_RX            = 11, /*!< I<sup>2</sup>C 1 RX */
-    ALT_DMA_PERIPH_I2C2_TX            = 12, /*!< I<sup>2</sup>C 2 TX */
-    ALT_DMA_PERIPH_I2C2_RX            = 13, /*!< I<sup>2</sup>C 2 RX */
-    ALT_DMA_PERIPH_I2C3_TX            = 14, /*!< I<sup>2</sup>C 3 TX */
-    ALT_DMA_PERIPH_I2C3_RX            = 15, /*!< I<sup>2</sup>C 3 RX */
-    ALT_DMA_PERIPH_SPI0_MASTER_TX     = 16, /*!< SPI 0 Master TX */
-    ALT_DMA_PERIPH_SPI0_MASTER_RX     = 17, /*!< SPI 0 Master RX */
-    ALT_DMA_PERIPH_SPI0_SLAVE_TX      = 18, /*!< SPI 0 Slave TX */
-    ALT_DMA_PERIPH_SPI0_SLAVE_RX      = 19, /*!< SPI 0 Slave RX */
-    ALT_DMA_PERIPH_SPI1_MASTER_TX     = 20, /*!< SPI 1 Master TX */
-    ALT_DMA_PERIPH_SPI1_MASTER_RX     = 21, /*!< SPI 1 Master RX */
-    ALT_DMA_PERIPH_SPI1_SLAVE_TX      = 22, /*!< SPI 1 Slave TX */
-    ALT_DMA_PERIPH_SPI1_SLAVE_RX      = 23, /*!< SPI 1 Slave RX */
-    ALT_DMA_PERIPH_QSPI_FLASH_TX      = 24, /*!< QSPI Flash TX */
-    ALT_DMA_PERIPH_QSPI_FLASH_RX      = 25, /*!< QSPI Flash RX */
-    ALT_DMA_PERIPH_STM                = 26, /*!< System Trace Macrocell */
-    ALT_DMA_PERIPH_RESERVED           = 27, /*!< Reserved */
-    ALT_DMA_PERIPH_UART0_TX           = 28, /*!< UART 0 TX */
-    ALT_DMA_PERIPH_UART0_RX           = 29, /*!< UART 0 RX */
-    ALT_DMA_PERIPH_UART1_TX           = 30, /*!< UART 1 TX */
-    ALT_DMA_PERIPH_UART1_RX           = 31  /*!< UART 1 RX */
-}
-ALT_DMA_PERIPH_t;
-
-/*!
- * This type enumerates the DMA security state options available.
- */
-typedef enum ALT_DMA_SECURITY_e
-{
-    ALT_DMA_SECURITY_DEFAULT   = 0, /*!< Use the default security value (e.g. reset default) */
-    ALT_DMA_SECURITY_SECURE    = 1, /*!< Secure */
-    ALT_DMA_SECURITY_NONSECURE = 2  /*!< Non-secure */
-}
-ALT_DMA_SECURITY_t;
-
-/*!
- * This type definition enumerates the DMA event-interrupt resources.
- */
-typedef enum ALT_DMA_EVENT_e
-{
-    ALT_DMA_EVENT_0     = 0, /*!< DMA Event 0 */
-    ALT_DMA_EVENT_1     = 1, /*!< DMA Event 1 */
-    ALT_DMA_EVENT_2     = 2, /*!< DMA Event 2 */
-    ALT_DMA_EVENT_3     = 3, /*!< DMA Event 3 */
-    ALT_DMA_EVENT_4     = 4, /*!< DMA Event 4 */
-    ALT_DMA_EVENT_5     = 5, /*!< DMA Event 5 */
-    ALT_DMA_EVENT_6     = 6, /*!< DMA Event 6 */
-    ALT_DMA_EVENT_7     = 7, /*!< DMA Event 7 */
-    ALT_DMA_EVENT_ABORT = 8  /*!< DMA Abort Event */
-}
-ALT_DMA_EVENT_t;
-
-/*!
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __ALT_DMA_COMMON_H__ */

bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h

@@ -1,957 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
- *
- * Copyright 2013 Altera Corporation. All Rights Reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- ******************************************************************************/
-
-#ifndef __ALT_DMA_PROGRAM_H__
-#define __ALT_DMA_PROGRAM_H__
-
-#include "hwlib.h"
-#include "alt_dma_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-/*!
- * \addtogroup ALT_DMA_PRG DMA Controller Programming API
- *
- * This API provides functions for dynamically defining and assembling microcode
- * programs for execution on the DMA controller.
- *
- * The microcode program assembly API provides users with the ability to develop
- * highly optimized and tailored algorithms for data transfer between SoC FPGA
- * IP blocks and/or system memory.
- *
- * The same microcode program assembly facilities are also used to implement the
- * functions found in the HWLIB Common DMA Operations functional API.
- *
- * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA
- * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated
- * from used specified system memory. Once a microcode program has been
- * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA
- * channel thread. The microcode program may be rerun on any DMA channel thread
- * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t
- * containing the program is maintained.
- *
- * @{
- */
-
-/*!
- * This preprocessor declares the DMA channel thread microcode instruction
- * cache line width in bytes. It is recommended that the program buffers be
- * sized to a multiple of the cache line size. This will allow for the most
- * efficient microcode speed and space utilization.
- */
-#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE     (32)
-
-/*!
- * This preprocessor declares the DMA channel thread microcode instruction
- * cache line count. Thus the total size of the cache is the cache line size
- * multipled by the cache line count. Programs larger than the cache size risk
- * having a cache miss while executing.
- */
-#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT    (16)
-
-/*!
- * This preprocessor definition determines the size of the program buffer
- * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate
- * size for most DMA microcode programs. If calls within this API are
- * reporting out of memory response codes, consider increasing the provisioned
- * program buffersize.
- *
- * To specify another DMA microcode program buffer size, redefine the macro
- * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in
- * your Makefile. It is recommended that the size be a multiple of the
- * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for
- * more information. The largest supported buffer size is 65536 bytes.
- */
-#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE
-#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE   (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT)
-#endif
-
-/*!
- * This type defines the structure used to assemble and contain a microcode
- * program which can be executed by the DMA controller. The internal members
- * are undocumented and should not be altered outside of this API.
- */
-typedef struct ALT_DMA_PROGRAM_s
-{
-    uint32_t flag;
-
-    uint16_t buffer_start;
-    uint16_t code_size;
-
-    uint16_t loop0;
-    uint16_t loop1;
-
-    uint16_t sar;
-    uint16_t dar;
-
-    /*
-     * Add a little extra space so that regardless of where this structure
-     * sits in memory, a suitable start address can be aligned to the cache
-     * line stride while providing the requested buffer space.
-     */
-    uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +
-                    ALT_DMA_PROGRAM_CACHE_LINE_SIZE];
-}
-ALT_DMA_PROGRAM_t;
-
-/*!
- * This type definition enumerates the DMA controller register names for use in
- * microcode program definition.
- */
-typedef enum ALT_DMA_PROGRAM_REG_e
-{
-    /*! Source Address Register */
-    ALT_DMA_PROGRAM_REG_SAR = 0x0,
-
-    /*! Destination Address Register */
-    ALT_DMA_PROGRAM_REG_DAR = 0x2,
-
-    /*! Channel Control Register */
-    ALT_DMA_PROGRAM_REG_CCR = 0x1
-}
-ALT_DMA_PROGRAM_REG_t;
-
-/*!
- * This type definition enumerates the instruction modifier options available
- * for use with selected DMA microcode instructions.
- *
- * The enumerations values are context dependent upon the instruction being
- * modified.
- *
- * For the <b>DMALD[S|B]</b>, <b>DMALDP\<S|B></b>, <b>DMAST[S|B]</b>, and
- * <b>DMASTP\<S|B></b> microcode instructions, the enumeration
- * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the <b>S</b> option modifier
- * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the <b>B</b>
- * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies
- * that no modifier is present for instructions where use of <b>[S|B]</b> is
- * optional.
- *
- * For the <b>DMAWFP</b> microcode instruction, the enumerations
- * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or
- * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding
- * options <b>\<single|burst|periph></b>.
- */
-typedef enum ALT_DMA_PROGRAM_INST_MOD_e
-{
-    /*!
-     * This DMA instruction modifier specifies that no special modifier is
-     * added to the instruction.
-     */
-    ALT_DMA_PROGRAM_INST_MOD_NONE,
-
-    /*!
-     * Depending on the DMA microcode instruction modified, this modifier
-     * specifies <b>S</b> case for a <b>[S|B]</b> or a <b>\<single></b> for a
-     * <b>\<single|burst|periph></b>.
-     */
-    ALT_DMA_PROGRAM_INST_MOD_SINGLE,
-
-    /*!
-     * Depending on the DMA microcode instruction modified, this modifier
-     * specifies <b>B</b> case for a <b>[S|B]</b> or a <b>\<burst></b> for a
-     * <b>\<single|burst|periph></b>.
-     */
-    ALT_DMA_PROGRAM_INST_MOD_BURST,
-
-    /*!
-     * This DMA instruction modifier specifies a <b>\<periph></b> for a
-     * <b>\<single|burst|periph></b>.
-     */
-    ALT_DMA_PROGRAM_INST_MOD_PERIPH
-}
-ALT_DMA_PROGRAM_INST_MOD_t;
-
-/*!
- * This function initializes a system memory buffer for use as a DMA microcode
- * program buffer. This should be the first API call made on the program
- * buffer type.
- *
- * \param       pgm
- *              A pointer to a DMA program buffer structure.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     Details about error status code
- */
-ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * This function verifies that the DMA microcode program buffer is no longer
- * in use and performs any needed uninitialization steps.
- *
- * \param       pgm
- *              A pointer to a DMA program buffer structure.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     Details about error status code
- */
-ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * This function clears the existing DMA microcode program in the given
- * program buffer.
- *
- * \param       pgm
- *              A pointer to a DMA program buffer structure.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     Details about error status code.
- */
-ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * This function validate that the given DMA microcode program buffer contains
- * a well formed program. If caches are enabled, the program buffer contents
- * will be cleaned to RAM.
- *
- * \param       pgm
- *              A pointer to a DMA program buffer structure.
- *
- * \retval      ALT_E_SUCCESS   The given program is well formed.
- * \retval      ALT_E_ERROR     The given program is not well formed.
- * \retval      ALT_E_TMO       The cache operation timed out.
- */
-ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * This function reports the number bytes incremented for the register
- * specified. The purpose is to determine the progress of an ongoing DMA
- * transfer.
- *
- * It is implemented by calculating the difference of the programmed SAR or DAR
- * with the current channel SAR or DAR register value.
- *
- * \param       pgm
- *              A pointer to a DMA program buffer structure.
- *
- * \param       channel
- *              The channel that the program is running on.
- *
- * \param       reg
- *              Register to change the value for. Valid for only
- *              ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR.
- *
- * \param       current
- *              The current snapshot value of the register read from the DMA
- *              channel.
- *
- * \param       progress
- *              [out] A pointer to a memory location that will be used to store
- *              the number of bytes transfered.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     Details about error status code.
- * \retval      ALT_E_BAD_ARG   The specified channel is invalid, the specified
- *                              register is invalid, or the DMAMOV for the
- *                              specified register has not yet been assembled
- *                              in the current program buffer.
- */
-ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm,
-                                             ALT_DMA_PROGRAM_REG_t reg,
-                                             uint32_t current, uint32_t * progress);
-
-/*!
- * This function updates a pre-existing DMAMOV value affecting the SAR or DAR
- * registers. This allows for pre-assembled programs that can be used on
- * different source and destination addresses.
- *
- * \param       pgm
- *              A pointer to a DMA program buffer structure.
- *
- * \param       reg
- *              Register to change the value for. Valid for only
- *              ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR.
- *
- * \param       val
- *              The value to update to.
- *
- * \retval      ALT_E_SUCCESS   The operation was successful.
- * \retval      ALT_E_ERROR     Details about error status code.
- * \retval      ALT_E_BAD_ARG   The specified register is invalid or the DMAMOV
- *                              for the specified register has not yet been
- *                              assembled in the current program buffer.
- */
-ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm,
-                                           ALT_DMA_PROGRAM_REG_t reg, uint32_t val);
-
-/*!
- */
-
-/*!
- * Assembles a DMAADDH (Add Halfword) instruction into the microcode program
- * buffer. This instruction uses 3 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA program buffer to contain the assembled instruction.
- *
- * \param       addr_reg
- *              The channel address register (ALT_DMA_PROGRAM_REG_DAR or
- *              ALT_DMA_PROGRAM_REG_SAR) to add the value to.
- *
- * \param       val
- *              The 16-bit unsigned value to add to the channel address
- *              register.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid channel register specified.
- */
-// Assembler Syntax: DMAADDH <address_register>, <16-bit immediate>
-ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm,
-                                        ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);
-
-/*!
- * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode
- * program buffer. This instruction uses 3 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       addr_reg
- *              The channel address register (ALT_DMA_PROGRAM_REG_DAR or
- *              ALT_DMA_PROGRAM_REG_SAR) to add the value to.
- *
- * \param       val
- *              The 16-bit unsigned value to add to the channel address
- *              register.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid channel register specified.
- */
-// Assembler Syntax: DMAADNH <address_register>, <16-bit immediate>
-ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm,
-                                        ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);
-
-/*!
- * Assembles a DMAEND (End) instruction into the microcode program buffer.
- * This instruction uses 1 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- */
-// Assembler Syntax: DMAEND
-ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode
- * program buffer. This instruction uses 2 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       periph
- *              The peripheral to flush.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid peripheral specified.
- */
-// Assembler Syntax: DMAFLUSHP <peripheral>
-ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm,
-                                          ALT_DMA_PERIPH_t periph);
-
-/*!
- * Assembles a DMAGO (Go) instruction into the microcode program buffer. This
- * instruction uses 6 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       channel
- *              The stopped channel to act upon.
- *
- * \param       val
- *              The value to write to the channel program counter register.
- *
- * \param       sec
- *              The security state for the operation.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid channel or security specified.
- */
-// Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns]
-ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm,
-                                      ALT_DMA_CHANNEL_t channel, uint32_t val,
-                                      ALT_DMA_SECURITY_t sec);
-
-/*!
- * Assembles a DMAKILL (Kill) instruction into the microcode program buffer.
- * This instruction uses 1 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- */
-// Assembler Syntax: DMAKILL
-ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * Assembles a DMALD (Load) instruction into the microcode program buffer.
- * This instruction uses 1 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       mod
- *              The program instruction modifier for the type of transfer.
- *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 
- *              ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid instruction modifier specified.
- */
-// Assembler Syntax: DMALD[S|B]
-ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm,
-                                      ALT_DMA_PROGRAM_INST_MOD_t mod);
-
-/*!
- * Assembles a DMALDP (Load and notify Peripheral) instruction into the
- * microcode program buffer. This instruction uses 2 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       mod
- *              The program instruction modifier for the type of transfer.
- *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 
- *              ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
- *
- * \param       periph
- *              The peripheral to notify.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid instruction modifier or peripheral
- *                                  specified.
- */
-// Assembler Syntax: DMALDP<S|B> <peripheral>
-ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm,
-                                       ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);
-
-/*!
- * Assembles a DMALP (Loop) instruction into the microcode program buffer.
- * This instruction uses 2 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       iterations
- *              The number of iterations to run for. Valid values are 1 - 256.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid iterations specified.
- * \retval      ALT_E_BAD_OPERATION All loop registers are in use.
- */
-// Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations>
-ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm,
-                                      uint32_t iterations);
-
-/*!
- * Assembles a DMALPEND (Loop End) instruction into the microcode program
- * buffer. This instruction uses 2 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       mod
- *              The program instruction modifier for the loop terminator. Only
- *              ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE
- *              and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid instruction modifier specified.
- * \retval      ALT_E_ARG_RANGE     Loop size is too large to be supported.
- * \retval      ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to
- *                                  the program buffer before adding this
- *                                  DMALPEND instruction.
- */
-// Assembler Syntax: DMALPEND[S|B]
-ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm,
-                                         ALT_DMA_PROGRAM_INST_MOD_t mod);
-
-/*!
- * Assembles a DMALPFE (Loop Forever) instruction into the microcode program
- * buffer. No instruction is added to the buffer but a previous DMALPEND to
- * create an infinite loop.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- */
-// Assembler Syntax: DMALPFE
-ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * Assembles a DMAMOV (Move) instruction into the microcode program buffer.
- * This instruction uses 6 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       chan_reg
- *              The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR,
- *              ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy
- *              the value to.
- *
- * \param       val
- *              The value to write to the specified register.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid channel register specified.
- */
-// Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate>
-ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm,
-                                       ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val);
-
-/*!
- * Assembles a DMANOP (No Operation) instruction into the microcode program
- * buffer. This instruction uses 1 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- */
-// Assembler Syntax: DMANOP
-ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode
- * program buffer. This instruction uses 1 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- */
-// Assembler Syntax: DMARMB
-ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * Assembles a DMASEV (Send Event) instruction into the microcode program
- * buffer. This instruction uses 2 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       evt
- *              The event to send.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid event specified.
- */
-// Assembler Syntax: DMASEV <event_num>
-ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm,
-                                       ALT_DMA_EVENT_t evt);
-
-/*!
- * Assembles a DMAST (Store) instruction into the microcode program buffer.
- * This instruction uses 1 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       mod
- *              The program instruction modifier for the type of transfer.
- *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 
- *              ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- */
-// Assembler Syntax: DMAST[S|B]
-ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm,
-                                      ALT_DMA_PROGRAM_INST_MOD_t mod);
-
-/*!
- * Assembles a DMASTP (Store and notify Peripheral) instruction into the
- * microcode program buffer. This instruction uses 2 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       mod
- *              The program instruction modifier for the type of transfer.
- *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and 
- *              ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
- *
- * \param       periph
- *              The peripheral to notify.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid instruction modifier or peripheral
- *                                  specified.
- */
-// Assembler Syntax: DMASTP<S|B> <peripheral>
-ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm,
-                                       ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);
-
-/*!
- * Assembles a DMASTZ (Store Zero) instruction into the microcode program
- * buffer. This instruction uses 1 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- */
-// Assembler Syntax: DMASTZ
-ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * Assembles a DMAWFE (Wait For Event) instruction into the microcode program
- * buffer. This instruction uses 2 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       evt
- *              The event to wait for.
- *
- * \param       invalid
- *              If invalid is set to true, the instruction will be configured
- *              to invalidate the instruction cache for the current DMA
- *              thread.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid event specified.
- */
-// Assembler Syntax: DMAWFE <event_num>[, invalid]
-ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm,
-                                       ALT_DMA_EVENT_t evt, bool invalid);
-
-/*!
- * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode
- * program buffer. This instruction uses 2 bytes of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \param       periph
- *              The peripheral to wait on.
- *
- * \param       mod
- *              The program instruction modifier for the type of transfer.
- *              Only ALT_DMA_PROGRAM_INST_MOD_SINGLE,
- *              ALT_DMA_PROGRAM_INST_MOD_BURST, or
- *              ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- * \retval      ALT_E_BAD_ARG       Invalid peripheral or instruction modifier
- *                                  specified.
- */
-// Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph>
-ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm,
-                                       ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod);
-
-/*!
- * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode
- * program buffer. This instruction uses 1 byte of buffer space.
- *
- * \param       pgm
- *              The DMA programm buffer to contain the assembled instruction.
- *
- * \retval      ALT_E_SUCCESS       Successful instruction assembly status.
- * \retval      ALT_E_DMA_BUF_OVF   DMA program buffer overflow.
- */
-// Assembler Syntax: DMAWMB
-ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm);
-
-/*!
- * \addtogroup DMA_CCR Support for DMAMOV CCR
- *
- * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the
- * dynamic microcode programming of the assembler directive:
-\verbatim
-
-DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA<I|F>]
-            [SP<imm3>] [SC<imm4>]
-            [DB<1-16>] [DS<8|16|32|64|128>] [DA<I|F>]
-            [DP<imm3>] [DC<imm4>]
-            [ES<8|16|32|64|128>]
-
-\endverbatim
-* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()).
-*
-* For example the assembler directive:
-\verbatim
-DMAMOV CCR SB1 SS32 DB1 DS32
-\endverbatim
-* would be dynamically programmed with the following API call:
-\verbatim
-alt_dma_program_DMAMOV( pgm,
-                        ALT_DMA_PROGRAM_REG_CCR,
-                        (   ALT_DMA_CCR_OPT_SB1
-                          | ALT_DMA_CCR_OPT_SS32
-                          | ALT_DMA_CCR_OPT_SA_DEFAULT
-                          | ALT_DMA_CCR_OPT_SP_DEFAULT
-                          | ALT_DMA_CCR_OPT_SC_DEFAULT
-                          | ALT_DMA_CCR_OPT_DB1
-                          | ALT_DMA_CCR_OPT_DS32
-                          | ALT_DMA_CCR_OPT_DA_DEFAULT
-                          | ALT_DMA_CCR_OPT_DP_DEFAULT
-                          | ALT_DMA_CCR_OPT_DC_DEFAULT
-                          | ALT_DMA_CCR_OPT_ES8
-                        )
-                      );
-\endverbatim
-*
-* Each CCR option category should be specified regardless of whether it
-* specifies a custom value or the normal default value (i.e. an
-* ALT_DMA_CCR_OPT_*_DEFAULT.
-*
-* @{
-*/
-
-/*
- * Source Address {Fixed,Incrementing}
- */
-/*! Source Address Fixed address burst. */
-#define ALT_DMA_CCR_OPT_SAF         (0 << 0)
-/*! Source Address Incrementing address burst. */
-#define ALT_DMA_CCR_OPT_SAI         (1 << 0)
-/*! Source Address Default value. */
-#define ALT_DMA_CCR_OPT_SA_DEFAULT  ALT_DMA_CCR_OPT_SAI
-
-/*
- * Source burst Size (in bits)
- */
-/*! Source burst Size of 8 bits. */
-#define ALT_DMA_CCR_OPT_SS8         (0 << 1)
-/*! Source burst Size of 16 bits. */
-#define ALT_DMA_CCR_OPT_SS16        (1 << 1)
-/*! Source burst Size of 32 bits. */
-#define ALT_DMA_CCR_OPT_SS32        (2 << 1)
-/*! Source burst Size of 64 bits. */
-#define ALT_DMA_CCR_OPT_SS64        (3 << 1)
-/*! Source burst Size of 128 bits. */
-#define ALT_DMA_CCR_OPT_SS128       (4 << 1)
-/*! Source burst Size default bits. */
-#define ALT_DMA_CCR_OPT_SS_DEFAULT  ALT_DMA_CCR_OPT_SS8
-
-/*
- * Source burst Length (in transfer(s))
- */
-/*! Source Burst length of 1 transfer. */
-#define ALT_DMA_CCR_OPT_SB1         (0x0 << 4)
-/*! Source Burst length of 2 transfers. */
-#define ALT_DMA_CCR_OPT_SB2         (0x1 << 4)
-/*! Source Burst length of 3 transfers. */
-#define ALT_DMA_CCR_OPT_SB3         (0x2 << 4)
-/*! Source Burst length of 4 transfers. */
-#define ALT_DMA_CCR_OPT_SB4         (0x3 << 4)
-/*! Source Burst length of 5 transfers. */
-#define ALT_DMA_CCR_OPT_SB5         (0x4 << 4)
-/*! Source Burst length of 6 transfers. */
-#define ALT_DMA_CCR_OPT_SB6         (0x5 << 4)
-/*! Source Burst length of 7 transfers. */
-#define ALT_DMA_CCR_OPT_SB7         (0x6 << 4)
-/*! Source Burst length of 8 transfers. */
-#define ALT_DMA_CCR_OPT_SB8         (0x7 << 4)
-/*! Source Burst length of 9 transfers. */
-#define ALT_DMA_CCR_OPT_SB9         (0x8 << 4)
-/*! Source Burst length of 10 transfers. */
-#define ALT_DMA_CCR_OPT_SB10        (0x9 << 4)
-/*! Source Burst length of 11 transfers. */
-#define ALT_DMA_CCR_OPT_SB11        (0xa << 4)
-/*! Source Burst length of 12 transfers. */
-#define ALT_DMA_CCR_OPT_SB12        (0xb << 4)
-/*! Source Burst length of 13 transfers. */
-#define ALT_DMA_CCR_OPT_SB13        (0xc << 4)
-/*! Source Burst length of 14 transfers. */
-#define ALT_DMA_CCR_OPT_SB14        (0xd << 4)
-/*! Source Burst length of 15 transfers. */
-#define ALT_DMA_CCR_OPT_SB15        (0xe << 4)
-/*! Source Burst length of 16 transfers. */
-#define ALT_DMA_CCR_OPT_SB16        (0xf << 4)
-/*! Source Burst length default transfers. */
-#define ALT_DMA_CCR_OPT_SB_DEFAULT  ALT_DMA_CCR_OPT_SB1
-
-/*
- * Source Protection
- */
-/*! Source Protection bits for AXI bus ARPROT[2:0]. */
-#define ALT_DMA_CCR_OPT_SP(imm3)    ((imm3) << 8)
-/*! Source Protection bits default value. */
-#define ALT_DMA_CCR_OPT_SP_DEFAULT  ALT_DMA_CCR_OPT_SP(0)
-
-/*
- * Source cache
- */
-/*! Source Cache bits for AXI bus ARCACHE[2:0]. */
-#define ALT_DMA_CCR_OPT_SC(imm4)    ((imm4) << 11)
-/*! Source Cache bits default value. */
-#define ALT_DMA_CCR_OPT_SC_DEFAULT  ALT_DMA_CCR_OPT_SC(0)
-
-/*
- * Destination Address {Fixed,Incrementing}
- */
-/*! Destination Address Fixed address burst. */
-#define ALT_DMA_CCR_OPT_DAF         (0 << 14)
-/*! Destination Address Incrementing address burst. */
-#define ALT_DMA_CCR_OPT_DAI         (1 << 14)
-/*! Destination Address Default value. */
-#define ALT_DMA_CCR_OPT_DA_DEFAULT  ALT_DMA_CCR_OPT_DAI
-
-/*
- * Destination burst Size (in bits)
- */
-/*! Destination burst Size of 8 bits. */
-#define ALT_DMA_CCR_OPT_DS8         (0 << 15)
-/*! Destination burst Size of 16 bits. */
-#define ALT_DMA_CCR_OPT_DS16        (1 << 15)
-/*! Destination burst Size of 32 bits. */
-#define ALT_DMA_CCR_OPT_DS32        (2 << 15)
-/*! Destination burst Size of 64 bits. */
-#define ALT_DMA_CCR_OPT_DS64        (3 << 15)
-/*! Destination burst Size of 128 bits. */
-#define ALT_DMA_CCR_OPT_DS128       (4 << 15)
-/*! Destination burst Size default bits. */
-#define ALT_DMA_CCR_OPT_DS_DEFAULT  ALT_DMA_CCR_OPT_DS8
-
-/*
- * Destination Burst length (in transfer(s))
- */
-/*! Destination Burst length of 1 transfer. */
-#define ALT_DMA_CCR_OPT_DB1         (0x0 << 18)
-/*! Destination Burst length of 2 transfers. */
-#define ALT_DMA_CCR_OPT_DB2         (0x1 << 18)
-/*! Destination Burst length of 3 transfers. */
-#define ALT_DMA_CCR_OPT_DB3         (0x2 << 18)
-/*! Destination Burst length of 4 transfers. */
-#define ALT_DMA_CCR_OPT_DB4         (0x3 << 18)
-/*! Destination Burst length of 5 transfers. */
-#define ALT_DMA_CCR_OPT_DB5         (0x4 << 18)
-/*! Destination Burst length of 6 transfers. */
-#define ALT_DMA_CCR_OPT_DB6         (0x5 << 18)
-/*! Destination Burst length of 7 transfers. */
-#define ALT_DMA_CCR_OPT_DB7         (0x6 << 18)
-/*! Destination Burst length of 8 transfers. */
-#define ALT_DMA_CCR_OPT_DB8         (0x7 << 18)
-/*! Destination Burst length of 9 transfers. */
-#define ALT_DMA_CCR_OPT_DB9         (0x8 << 18)
-/*! Destination Burst length of 10 transfers. */
-#define ALT_DMA_CCR_OPT_DB10        (0x9 << 18)
-/*! Destination Burst length of 11 transfers. */
-#define ALT_DMA_CCR_OPT_DB11        (0xa << 18)
-/*! Destination Burst length of 12 transfers. */
-#define ALT_DMA_CCR_OPT_DB12        (0xb << 18)
-/*! Destination Burst length of 13 transfers. */
-#define ALT_DMA_CCR_OPT_DB13        (0xc << 18)
-/*! Destination Burst length of 14 transfers. */
-#define ALT_DMA_CCR_OPT_DB14        (0xd << 18)
-/*! Destination Burst length of 15 transfers. */
-#define ALT_DMA_CCR_OPT_DB15        (0xe << 18)
-/*! Destination Burst length of 16 transfers. */
-#define ALT_DMA_CCR_OPT_DB16        (0xf << 18)
-/*! Destination Burst length default transfers. */
-#define ALT_DMA_CCR_OPT_DB_DEFAULT  ALT_DMA_CCR_OPT_DB1
-
-/*
- * Destination Protection
- */
-/*! Destination Protection bits for AXI bus AWPROT[2:0]. */
-#define ALT_DMA_CCR_OPT_DP(imm3)    ((imm3) << 22)
-/*! Destination Protection bits default value. */
-#define ALT_DMA_CCR_OPT_DP_DEFAULT  ALT_DMA_CCR_OPT_DP(0)
-
-/*
- * Destination Cache
- */
-/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */
-#define ALT_DMA_CCR_OPT_DC(imm4)    ((imm4) << 25)
-/*! Destination Cache bits default value. */
-#define ALT_DMA_CCR_OPT_DC_DEFAULT  ALT_DMA_CCR_OPT_DC(0)
-
-/*
- * Endian Swap size (in bits)
- */
-/*! Endian Swap: No swap, 8-bit data. */
-#define ALT_DMA_CCR_OPT_ES8         (0 << 28)
-/*! Endian Swap: Swap bytes within 16-bit data. */
-#define ALT_DMA_CCR_OPT_ES16        (1 << 28)
-/*! Endian Swap: Swap bytes within 32-bit data. */
-#define ALT_DMA_CCR_OPT_ES32        (2 << 28)
-/*! Endian Swap: Swap bytes within 64-bit data. */
-#define ALT_DMA_CCR_OPT_ES64        (3 << 28)
-/*! Endian Swap: Swap bytes within 128-bit data. */
-#define ALT_DMA_CCR_OPT_ES128       (4 << 28)
-/*! Endian Swap: Default byte swap. */
-#define ALT_DMA_CCR_OPT_ES_DEFAULT  ALT_DMA_CCR_OPT_ES8
-
-/*! Default CCR register options for a DMAMOV CCR assembler directive. */
-#define ALT_DMA_CCR_OPT_DEFAULT \
-    (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \
-     ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \
-     ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \
-     ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \
-     ALT_DMA_CCR_OPT_ES8)
-
-/*!
- * @}
- */
-
-/*!
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif  /* __cplusplus */
-
-#endif /* __ALT_DMA_PROGRAM_H__ */

bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h

@@ -1,62 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
-*
-* Copyright 2013 Altera Corporation. All Rights Reserved.
-* 
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 
-* 3. The name of the author may not be used to endorse or promote products
-* derived from this software without specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-* OF SUCH DAMAGE.
-* 
-******************************************************************************/
-
-#ifndef __ALT_HWLIBS_VER_H__
-
-/***********************************************************************
- *
- * Set of macros to provide version information
- *
- ***********************************************************************/
-
-/* This is the major revision of the Altera ACDS Release    	*/
-#define ALTERA_ACDS_MAJOR_REV           13
-
-/* This is the minor revision of the Altera ACDS Release    	*/
-#define ALTERA_ACDS_MINOR_REV            1
-
-/* This is an internal HwLibs revision/feature control code.	*/
-/* End-users should NOT depend upon the value of this field 	*/
-#define ALTERA_HWLIBS_REV                0
-
-/* This is a text string containing the current release and service pack IDs */
-#define ALTERA_ACDS_REV_STR             "13.1"
-
-/* This is a text string containing the current SoC EDS ID 		*/
-#define ALTERA_SOCEDS_REV_STR           "Altera SoC Embedded Design Suite v13.1"
-
-
-#endif   /* __ALT_HWLIBS_VER_H__ */

bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h

@@ -1,539 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
-*
-* Copyright 2013 Altera Corporation. All Rights Reserved.
-* 
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 
-* 3. The name of the author may not be used to endorse or promote products
-* derived from this software without specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-* OF SUCH DAMAGE.
-* 
-******************************************************************************/
-
-#ifndef __ALT_INT_COMMON_H__
-#define __ALT_INT_COMMON_H__
-
-#include "hwlib.h"
-#include <stdbool.h>
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/*!
- * \addtogroup INT_COMMON Interrupt Controller Common Definitions
- *
- * This module contains the definitions common to the Interrupt Controller
- * Low-Level API and Interrupt Controller Manager Interface.
- *
- * @{
- */
-
-/*!
- * This type definition enumerates all the interrupt identification types.
- */
-typedef enum ALT_INT_INTERRUPT_e
-{
-    ALT_INT_INTERRUPT_SGI0  =  0, /*!< # */
-    ALT_INT_INTERRUPT_SGI1  =  1, /*!< # */
-    ALT_INT_INTERRUPT_SGI2  =  2, /*!< # */
-    ALT_INT_INTERRUPT_SGI3  =  3, /*!< # */
-    ALT_INT_INTERRUPT_SGI4  =  4, /*!< # */
-    ALT_INT_INTERRUPT_SGI5  =  5, /*!< # */
-    ALT_INT_INTERRUPT_SGI6  =  6, /*!< # */
-    ALT_INT_INTERRUPT_SGI7  =  7, /*!< # */
-    ALT_INT_INTERRUPT_SGI8  =  8, /*!< # */
-    ALT_INT_INTERRUPT_SGI9  =  9, /*!< # */
-    ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */
-    ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */
-    ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */
-    ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */
-    ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */
-    ALT_INT_INTERRUPT_SGI15 = 15,
-    /*!<
-     * Software Generated Interrupts (SGI), 0 - 15.
-     *  * All interrupts in this group are software triggered.
-     */
-
-    ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL   = 27, /*!< # */
-    ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE  = 29, /*!< # */
-    ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */
-    /*!<
-     * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU
-     * private timer, and watchdog timer.
-     *  * All interrupts in this group are edge triggered.
-     */
-
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL         = 32, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC    = 33, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB     = 34, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG   = 35, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA  = 36, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB     = 37, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG   = 39, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA  = 40, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_DEFLAGS0           = 41, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_DEFLAGS1           = 42, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_DEFLAGS2           = 43, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_DEFLAGS3           = 44, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_DEFLAGS4           = 45, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_DEFLAGS5           = 46, /*!< # */
-    ALT_INT_INTERRUPT_CPU0_DEFLAGS6           = 47,
-    /*!<
-     * Interrupts sourced from CPU0.
-     *
-     * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the
-     * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
-     * for CPU0.
-     *
-     *  * PARITYFAIL interrupts in this group are edge triggered.
-     *  * DEFFLAGS interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL         = 48, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC    = 49, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB     = 50, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG   = 51, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA  = 52, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB     = 53, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG   = 55, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA  = 56, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_DEFLAGS0           = 57, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_DEFLAGS1           = 58, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_DEFLAGS2           = 59, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_DEFLAGS3           = 60, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_DEFLAGS4           = 61, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_DEFLAGS5           = 62, /*!< # */
-    ALT_INT_INTERRUPT_CPU1_DEFLAGS6           = 63,
-    /*!<
-     * Interrupts sourced from CPU1.
-     *
-     * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the
-     * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
-     * for CPU1.
-     *
-     *  * PARITYFAIL interrupts in this group are edge triggered.
-     *  * DEFFLAGS interrupts in this group are level triggered.
-     */
-    
-    ALT_INT_INTERRUPT_SCU_PARITYFAIL0 =  64, /*!< # */
-    ALT_INT_INTERRUPT_SCU_PARITYFAIL1 =  65, /*!< # */
-    ALT_INT_INTERRUPT_SCU_EV_ABORT    =  66,
-    /*!<
-     * Interrupts sourced from the Snoop Control Unit (SCU).
-     *  * All interrupts in this group are edge triggered.
-     */
-    
-    ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ     = 67, /*!< # */
-    ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ   = 68, /*!< # */
-    ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */
-    ALT_INT_INTERRUPT_L2_COMBINED_IRQ        = 70,
-    /*!<
-     * Interrupts sourced from the L2 Cache Controller.
-     *
-     * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache
-     * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
-     * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts.
-     * Consult the L2C documentation for information on these interrupts.
-     *
-     *  * ECC interrupts in this group are edge triggered.
-     *  * Other interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ =  71,
-    /*!<
-     * Interrupts sourced from the SDRAM Controller.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ0  =  72, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ1  =  73, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ2  =  74, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ3  =  75, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ4  =  76, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ5  =  77, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ6  =  78, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ7  =  79, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ8  =  80, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ9  =  81, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 =  82, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 =  83, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 =  84, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 =  85, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 =  86, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 =  87, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 =  88, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 =  89, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 =  90, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 =  91, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 =  92, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 =  93, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 =  94, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 =  95, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 =  96, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 =  97, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 =  98, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 =  99, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */
-    ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135,
-    /*!<
-     * Interrupt request from the FPGA logic, 0 - 63.
-     *  * Trigger type depends on the implementation in the FPGA.
-     */
-
-    ALT_INT_INTERRUPT_DMA_IRQ0                = 136, /*!< # */
-    ALT_INT_INTERRUPT_DMA_IRQ1                = 137, /*!< # */
-    ALT_INT_INTERRUPT_DMA_IRQ2                = 138, /*!< # */
-    ALT_INT_INTERRUPT_DMA_IRQ3                = 139, /*!< # */
-    ALT_INT_INTERRUPT_DMA_IRQ4                = 140, /*!< # */
-    ALT_INT_INTERRUPT_DMA_IRQ5                = 141, /*!< # */
-    ALT_INT_INTERRUPT_DMA_IRQ6                = 142, /*!< # */
-    ALT_INT_INTERRUPT_DMA_IRQ7                = 143, /*!< # */
-    ALT_INT_INTERRUPT_DMA_IRQ_ABORT           = 144, /*!< # */
-    ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ   = 145, /*!< # */
-    ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146,
-    /*!<
-     * Interrupts sourced from the DMA Controller.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_EMAC0_IRQ                    = 147, /*!< # */
-    ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ   = 148, /*!< # */
-    ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */
-    ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ   = 150, /*!< # */
-    ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151,
-    /*!<
-     * Interrupts sourced from the Ethernet MAC 0 (EMAC0).
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_EMAC1_IRQ                    = 152, /*!< # */
-    ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ   = 153, /*!< # */
-    ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */
-    ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ   = 155, /*!< # */
-    ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,
-    /*!<
-     * Interrupts sourced from the Ethernet MAC 1 (EMAC1).
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_USB0_IRQ             = 157, /*!< # */
-    ALT_INT_INTERRUPT_USB0_ECC_CORRECTED   = 158, /*!< # */
-    ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159,
-    /*!<
-     * Interrupts sourced from the USB OTG 0.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_USB1_IRQ             = 160, /*!< # */
-    ALT_INT_INTERRUPT_USB1_ECC_CORRECTED   = 161, /*!< # */
-    ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162,
-    /*!<
-     * Interrupts sourced from the USB OTG 1.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_CAN0_STS_IRQ             = 163, /*!< # */
-    ALT_INT_INTERRUPT_CAN0_MO_IRQ              = 164, /*!< # */
-    ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ   = 165, /*!< # */
-    ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166,
-    /*!<
-     * Interrupts sourced from the CAN Controller 0.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_CAN1_STS_IRQ             = 167, /*!< # */
-    ALT_INT_INTERRUPT_CAN1_MO_IRQ              = 168, /*!< # */
-    ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ   = 169, /*!< # */
-    ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170,
-    /*!<
-     * Interrupts sourced from the CAN Controller 1.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_SDMMC_IRQ                   = 171, /*!< # */
-    ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED   = 172, /*!< # */
-    ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */
-    ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED   = 174, /*!< # */
-    ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175,
-    /*!<
-     * Interrupts sourced from the SDMMC Controller.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_NAND_IRQ                  = 176, /*!< # */
-    ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ   = 177, /*!< # */
-    ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */
-    ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ   = 179, /*!< # */
-    ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */
-    ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ   = 181, /*!< # */
-    ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182,
-    /*!<
-     * Interrupts sourced from the NAND Controller.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_QSPI_IRQ                 = 183, /*!< # */
-    ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ   = 184, /*!< # */
-    ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185,
-    /*!<
-     * Interrupts sourced from the QSPI Controller.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */
-    ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */
-    ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */
-    ALT_INT_INTERRUPT_SPI3_IRQ = 189,
-    /*!<
-     * Interrupts sourced from the SPI Controllers 0 - 3.
-     * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1.
-     * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */
-    ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */
-    ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */
-    ALT_INT_INTERRUPT_I2C3_IRQ = 193,
-    /*!<
-     * Interrupts sourced from the I2C Controllers 0 - 3.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_UART0 = 194, /*!< # */
-    ALT_INT_INTERRUPT_UART1 = 195,
-    /*!<
-     * Interrupts sourced from the UARTs 0 - 1.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */
-    ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */
-    ALT_INT_INTERRUPT_GPIO2 = 198,
-    /*!<
-     * Interrupts sourced from the GPIO 0 - 2.
-     *  * All interrupts in this group are level triggered.
-     */
-    
-    ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */
-    ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */
-    ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */
-    ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202,
-    /*!<
-     * Interrupts sourced from the Timer controllers.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */
-    ALT_INT_INTERRUPT_WDOG1_IRQ = 204,
-    /*!<
-     * Interrupts sourced from the Watchdog Timers 0 - 1.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_CLKMGR_IRQ = 205,
-    /*!<
-     * Interrupts sourced from the Clock Manager.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206,
-    /*!<
-     * Interrupts sourced from the Clock Manager MPU Wakeup.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207,
-    /*!<
-     * Interrupts sourced from the FPGA Manager.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */
-    ALT_INT_INTERRUPT_NCTIIRQ1 = 209,
-    /*!<
-     * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI.
-     *  * All interrupts in this group are level triggered.
-     */
-
-    ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ   = 210, /*!< # */
-    ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211
-    /*!<
-     * Interrupts sourced from the On-chip RAM.
-     *  * All interrupts in this group are level triggered.
-     */
-
-} ALT_INT_INTERRUPT_t;
-
-/*!
- * This is the CPU target type. It is used to specify a set of CPUs on the
- * system. If only bit 0 is set then it specifies a set of CPUs containing
- * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit
- * up to the number of CPUs on the system.
- */
-typedef uint32_t alt_int_cpu_target_t;
-
-/*!
- * This type definition enumerates all the interrupt trigger types.
- */
-typedef enum ALT_INT_TRIGGER_e
-{
-    /*!
-     * Edge triggered interrupt. This applies to Private Peripheral Interrupts
-     * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs
-     * 16 - 1019.
-     */
-    ALT_INT_TRIGGER_EDGE,
-
-    /*!
-     * Level triggered interrupt. This applies to Private Peripheral
-     * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with
-     * interrupt IDs 16 - 1019.
-     */
-    ALT_INT_TRIGGER_LEVEL,
-
-    /*!
-     * Software triggered interrupt. This applies to Software Generated
-     * Interrupts (SGI) only, with interrupt IDs 0 - 15.
-     */
-    ALT_INT_TRIGGER_SOFTWARE,
-
-    /*!
-     * All triggering types except for those in the Shared Peripheral Interrupts
-     * (SPI) F2S FPGA family interrupts can be determined by the system
-     * automatically. In all functions which ask for the triggering type, the
-     * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger
-     * type for all non F2S interrupt types.
-     */
-    ALT_INT_TRIGGER_AUTODETECT,
-
-    /*!
-     * The interrupt triggering information is not applicable. This is possibly
-     * due to querying an invalid interrupt identifier.
-     */
-    ALT_INT_TRIGGER_NA
-}
-ALT_INT_TRIGGER_t;
-
-/*!
- * This type definition enumerates all the target list filter options. This is
- * used by the trigger Software Generated Interrupt (SGI) feature to issue a
- * SGI to the specified processor(s) in the system. Depending on the target
- * list filter and the target list, interrupts can be routed to any
- * combinations of CPUs.
- */
-typedef enum ALT_INT_SGI_TARGET_e
-{
-    /*!
-     * This filter list uses the target list parameter to specify which CPUs
-     * to send the interrupt to. If target list is 0, no interrupts are sent.
-     */
-    ALT_INT_SGI_TARGET_LIST,
-
-    /*!
-     * This filter list sends the interrupt all CPUs except the current CPU.
-     * The target list parameter is ignored.
-     */
-    ALT_INT_SGI_TARGET_ALL_EXCL_SENDER,
-
-    /*!
-     * This filter list sends the interrupt to the current CPU only. The
-     * target list parameter is ignored.
-     */
-    ALT_INT_SGI_TARGET_SENDER_ONLY
-}
-ALT_INT_SGI_TARGET_t;
-
-/*!
- * Extracts the CPUID field from the ICCIAR register.
- */
-#define ALT_INT_ICCIAR_CPUID_GET(icciar)    ((icciar >> 10) & 0x7)
-
-/*!
- * Extracts the ACKINTID field from the ICCIAR register.
- */
-#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF)
-
-/*!
- * The callback to use when an interrupt needs to be serviced.
- *
- * \param       icciar          The Interrupt Controller CPU Interrupt
- *                              Acknowledgement Register value (ICCIAR) value
- *                              corresponding to the current interrupt.
- *
- * \param       context         The user provided context.
- */
-typedef void (*alt_int_callback_t)(uint32_t icciar, void * context);
-
-/*!
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ALT_INT_COMMON_H__ */

bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h

@@ -1,162 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-
-/******************************************************************************
-*
-* Copyright 2013 Altera Corporation. All Rights Reserved.
-* 
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 
-* 3. The name of the author may not be used to endorse or promote products
-* derived from this software without specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-* OF SUCH DAMAGE.
-* 
-******************************************************************************/
-
-#ifndef __ALT_MPUSCU_H__
-#define __ALT_MPUSCU_H__
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-
-/************************************************************************************************************/
-/*                                alt_mpuscu.h                                                                 */
-/*                                                                                                            */
-/*  Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog         */
-/*  Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor.    */
-/*                                                                                                            */
-/************************************************************************************************************/
-
-#ifndef ALT_HPS_ADDR
-#define ALT_HPS_ADDR 0x00
-#endif
-
-
-/*     ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h            */
-/*    and is the address of the base of the Snoop Control Unit (SCU)                                */
-#define GLOBALTMR_BASE                      (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET)
-#define CPU_WDTGPT_TMR_BASE                 (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET)
-#define CPU_PRIVATE_TMR_BASE                (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
-#define CPU_INT_CTRL_BASE                   (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET)
-#define CPU_INT_DIST_BASE                   (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
-
-
-            /* offsets */
-        /* Global Timer offsets */
-#define GLOBALTMR_MODULE_BASE_OFFSET        0x00000200
-#define GLOBALTMR_CNTR_LO_REG_OFFSET        0x00000000
-#define GLOBALTMR_CNTR_HI_REG_OFFSET        0x00000004
-#define GLOBALTMR_CTRL_REG_OFFSET           0x00000008
-#define GLOBALTMR_INT_STAT_REG_OFFSET       0x0000000C
-#define GLOBALTMR_COMP_LO_REG_OFFSET        0x00000010
-#define GLOBALTMR_COMP_HI_REG_OFFSET        0x00000014
-#define GLOBALTMR_AUTOINC_REG_OFFSET        0x00000018
-
-/* Global Timer bitmasks */
-#define GLOBALTMR_ENABLE_BIT                0x00000001
-#define GLOBALTMR_COMP_ENABLE_BIT           0x00000002
-#define GLOBALTMR_INT_ENABLE_BIT            0x00000004
-#define GLOBALTMR_AUTOINC_ENABLE_BIT        0x00000008
-#define GLOBALTMR_PS_MASK                   0x0000FF00
-#define GLOBALTMR_PS_SHIFT                  8
-#define GLOBALTMR_INT_STATUS_BIT            0x00000001
-
-/* Global timer constants */
-#define GLOBALTMR_MAX                       0xFFFFFFFF
-#define GLOBALTMR_PS_MAX                    0x000000FF
-
-
-/* Private timer offsets */
-#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET   0x00000600
-#define CPU_PRIV_TMR_LOAD_REG_OFFSET        0x00000000
-#define CPU_PRIV_TMR_CNTR_REG_OFFSET        0x00000004
-#define CPU_PRIV_TMR_CTRL_REG_OFFSET        0x00000008
-#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET  0x0000000C
-
-/* Private timer bitmasks */
-#define CPU_PRIV_TMR_ENABLE                 0x00000001
-#define CPU_PRIV_TMR_AUTO_RELOAD            0x00000002
-#define CPU_PRIV_TMR_INT_EN                 0x00000004
-#define CPU_PRIV_TMR_PS_MASK                0x0000FF00
-#define CPU_PRIV_TMR_PS_SHIFT               8
-#define CPU_PRIV_TMR_INT_STATUS             0x00000001
-
-/* Private timer constants */
-#define CPU_PRIV_TMR_MAX                    0xFFFFFFFF
-#define CPU_PRIV_TMR_PS_MAX                 0x000000FF
-
-
-
-    /* Watchdog timer offsets */
-#define WDOG_TIMER_MODULE_BASE_OFFSET       0x00000620
-#define WDOG_LOAD_REG_OFFSET                0x00000000
-#define WDOG_CNTR_REG_OFFSET                0x00000004
-#define WDOG_CTRL_REG_OFFSET                0x00000008
-#define WDOG_INTSTAT_REG_OFFSET             0x0000000C
-#define WDOG_RSTSTAT_REG_OFFSET             0x00000010
-#define WDOG_DISABLE_REG_OFFSET             0x00000014
-
-    /* Watchdog timer bitmasks : */
-    /* Control Register bitmasks */
-#define WDOG_TMR_ENABLE                     0x00000001
-#define WDOG_AUTO_RELOAD                    0x00000002
-#define WDOG_INT_EN                         0x00000004
-#define WDOG_WDT_MODE                       0x00000008
-#define WDOG_PS_MASK                        0x0000FF00
-#define WDOG_PS_SHIFT                       8
-    /* Interrupt Status Register bitmasks */
-#define WDOG_INT_STAT_BIT                   0x00000001
-    /* Reset Status Register bitmasks */
-#define WDOG_RST_STAT_BIT                   0x00000001
-
-    /* Watchdog timer constants */
-#define WDOG_TMR_MAX                        UINT32_MAX
-#define WDOG_PS_MAX                         UINT8_MAX
-#define WDOG_DISABLE_VAL0                   0x12345678
-#define WDOG_DISABLE_VAL1                   0x87654321
-
-
-
-    /* Interrupt Manager offsets */
-/*   <Add definitions here> */
-#define INT_CONTROLLER_MODULE_BASE_OFFSET   0x00000100
-#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET  0x00001000
-#define INT_DIST_TYPE_REG                   0x00000004
-
-
-/*  Upper bound of the MPUSCU address space  */
-#define MPUSCU_MAX                          0x00001FFF
-
-
-
-#ifdef __cplusplus
-}
-#endif  /* __cplusplus */
-
-#endif  /* __ALT_MPUSCU_H__ */

bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h

@@ -1,173 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
- *
- * Copyright 2013 Altera Corporation. All Rights Reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
- * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- ******************************************************************************/
-
-/*! \file
- *  Altera - QSPI Flash Controller Module
- */
-
-#ifndef __ALT_QSPI_PRIVATE_H__
-#define __ALT_QSPI_PRIVATE_H__
-
-#include "socal/socal.h"
-
-//
-// This section provisions support for various flash devices.
-//
-
-#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1
-
-/////
-
-#define ALT_QSPI_PAGE_ADDR_MSK          0xFFFFFF00
-#define ALT_QSPI_PAGE_SIZE              0x00000100 // 256 B
-#define ALT_QSPI_SUBSECTOR_ADDR_MSK     0xFFFFF000
-#define ALT_QSPI_SUBSECTOR_SIZE         0x00001000 // 4096 B
-#define ALT_QSPI_SECTOR_ADDR_MSK        0xFFFF0000
-#define ALT_QSPI_SECTOR_SIZE            0x00010000 // 64 KiB
-#define ALT_QSPI_BANK_ADDR_MSK          0xFF000000
-#define ALT_QSPI_BANK_SIZE              0x01000000 // 16 MiB
-
-#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
-#define ALT_QSPI_N25Q_DIE_ADDR_MSK      0xFE000000
-#define ALT_QSPI_N25Q_DIE_SIZE          0x02000000 // 32 MiB
-#endif
-
-/////
-
-// Default delay timing (in ns) for N25Q.
-// These values are from the N25Q handbook. The timing correctness is difficult
-// to test because the test setup does not feature mutliple chips.
-#define ALT_QSPI_TSHSL_NS_DEF       (50)
-#define ALT_QSPI_TSD2D_NS_DEF       (0)
-#define ALT_QSPI_TCHSH_NS_DEF       (4)
-#define ALT_QSPI_TSLCH_NS_DEF       (4)
-
-/*
-// Default delay timing (in ns)
-#define ALT_QSPI_TSHSL_NS_DEF       (200)
-#define ALT_QSPI_TSD2D_NS_DEF       (255)
-#define ALT_QSPI_TCHSH_NS_DEF       (20)
-#define ALT_QSPI_TSLCH_NS_DEF       (20)
-*/
-
-// Flash commands
-#define ALT_QSPI_STIG_OPCODE_READ                 (0x03)
-#define ALT_QSPI_STIG_OPCODE_4BYTE_READ           (0x13)
-#define ALT_QSPI_STIG_OPCODE_FASTREAD             (0x0B)
-#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B)
-#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B)
-#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO     (0xBB)
-#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO     (0xEB)
-#define ALT_QSPI_STIG_OPCODE_PP                   (0x02)
-#define ALT_QSPI_STIG_OPCODE_DUAL_PP              (0xA2)
-#define ALT_QSPI_STIG_OPCODE_QUAD_PP              (0x32)
-#define ALT_QSPI_STIG_OPCODE_RDID                 (0x9F)
-#define ALT_QSPI_STIG_OPCODE_WREN                 (0x06)
-#define ALT_QSPI_STIG_OPCODE_WRDIS                (0x04)
-#define ALT_QSPI_STIG_OPCODE_RDSR                 (0x05)
-#define ALT_QSPI_STIG_OPCODE_WRSR                 (0x01)
-#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE         (0x20)
-#define ALT_QSPI_STIG_OPCODE_SEC_ERASE            (0xD8)
-#define ALT_QSPI_STIG_OPCODE_BULK_ERASE           (0xC7)
-#define ALT_QSPI_STIG_OPCODE_DIE_ERASE            (0xC4)
-#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE           (0x60)
-#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG           (0xC8)
-#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG           (0xC5)
-#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG          (0x05)
-#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG          (0x01)
-#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE     (0xB7)
-#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE      (0xE9)
-
-// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts.
-#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
-#define ALT_QSPI_STIG_OPCODE_RESET_EN             (0x66)
-#define ALT_QSPI_STIG_OPCODE_RESET_MEM            (0x99)
-#define ALT_QSPI_STIG_OPCODE_RDFLGSR              (0x70)
-#define ALT_QSPI_STIG_OPCODE_CLRFLGSR             (0x50)
-#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM         (0x5A)
-#endif
-
-// Spansion commands
-// #define OPCODE_ECRM                 (0xFF) // Exit continuous read mode
-
-#define QSPI_READ_CLK_MHZ           (50)
-#define QSPI_FASTREAD_CLK_MHZ       (100)
-
-// Manufacturer ID
-#define ALT_QSPI_STIG_RDID_JEDECID_MICRON      (0x20)
-#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX     (0x20) // Same as Micron
-#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION    (0xEF)
-#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND     (0xEF) // Same as Spansion
-#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC    (0xC2)
-#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL       (0x1F)
-
-#define ALT_QSPI_STIG_RDID_JEDECID_GET(value)    ((value >>  0) & 0xff)
-#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff)
-
-#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1)
-#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value)        ((value >> 7) & 0x1)
-#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value)      ((value >> 7) & 0x1)
-#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value)        ((value >> 5) & 0x1)
-#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value)      ((value >> 4) & 0x1)
-#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value)    ((value >> 1) & 0x1)
-#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value)   ((value >> 0) & 0x1)
-
-#define ALT_QSPI_STIG_SR_BUSY_GET(value)       		  	  ((value >> 0) & 0x1)
-
-/////
-
-#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff)
-
-ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size);
-
-ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout);
-ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy,
-                                     uint32_t num_bytes, uint32_t * output,
-                                     uint32_t timeout);
-ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy,
-                                     uint32_t num_bytes, const uint32_t * input,
-                                     uint32_t timeout);
-ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy,
-                                       uint32_t address,
-                                       uint32_t timeout);
-
-ALT_STATUS_CODE alt_qspi_device_wren(void);
-ALT_STATUS_CODE alt_qspi_device_wrdis(void);
-ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid);
-ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param);
-ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank);
-
-#endif // __ALT_PRIVATE_QSPI_H__

bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h

@@ -1,297 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/*! \file
- *  Altera - SoC Reset Manager
- */
-
-/******************************************************************************
-*
-* Copyright 2013 Altera Corporation. All Rights Reserved.
-* 
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 
-* 3. The name of the author may not be used to endorse or promote products
-* derived from this software without specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-* OF SUCH DAMAGE.
-* 
-******************************************************************************/
-
-#ifndef __ALT_RESET_MGR_H__
-#define __ALT_RESET_MGR_H__
-
-#include "hwlib.h"
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-/*! \addtogroup RST_MGR The Reset Manager
- *
- * The Reset Manager API defines functions for accessing, configuring, and
- * controlling the HPS reset behavior.
- * @{
- */
-
-/******************************************************************************/
-/*! \addtogroup RST_MGR_STATUS Reset Status
- *
- * This functional group provides information on various aspects of SoC reset
- * status and timeout events.
- *
- * @{
- */
-
-/******************************************************************************/
-/*!
- * This type definition enumerates the set of reset causes and timeout events as
- * register mask values.
- */
-typedef enum ALT_RESET_EVENT_e
-{
-    /*! Power-On Voltage Detector Cold Reset */
-    ALT_RESET_EVENT_PORVOLTRST          = 0x00000001,
-
-    /*! nPOR Pin Cold Reset                  */
-    ALT_RESET_EVENT_NPORPINRST          = 0x00000002,
-
-    /*! FPGA Core Cold Reset                 */
-    ALT_RESET_EVENT_FPGACOLDRST         = 0x00000004,
-
-    /*! CONFIG_IO Cold Reset                 */
-    ALT_RESET_EVENT_CONFIGIOCOLDRST     = 0x00000008,
-
-    /*! Software Cold Reset                  */
-    ALT_RESET_EVENT_SWCOLDRST           = 0x00000010,
-
-    /*! nRST Pin Warm Reset                  */
-    ALT_RESET_EVENT_NRSTPINRST          = 0x00000100,
-
-    /*! FPGA Core Warm Reset                 */
-    ALT_RESET_EVENT_FPGAWARMRST         = 0x00000200,
-
-    /*! Software Warm Reset                  */
-    ALT_RESET_EVENT_SWWARMRST           = 0x00000400,
-
-    /*! MPU Watchdog 0 Warm Reset            */
-    ALT_RESET_EVENT_MPUWD0RST           = 0x00001000,
-
-    /*! MPU Watchdog 1 Warm Reset            */
-    ALT_RESET_EVENT_MPUWD1RST           = 0x00002000,
-
-    /*! L4 Watchdog 0 Warm Reset             */
-    ALT_RESET_EVENT_L4WD0RST            = 0x00004000,
-
-    /*! L4 Watchdog 1 Warm Reset             */
-    ALT_RESET_EVENT_L4WD1RST            = 0x00008000,
-
-    /*! FPGA Core Debug Reset                */
-    ALT_RESET_EVENT_FPGADBGRST          = 0x00040000,
-
-    /*! DAP Debug Reset                      */
-    ALT_RESET_EVENT_CDBGREQRST          = 0x00080000,
-
-    /*! SDRAM Self-Refresh Timeout           */
-    ALT_RESET_EVENT_SDRSELFREFTIMEOUT   = 0x01000000,
-
-    /*! FPGA manager handshake Timeout       */
-    ALT_RESET_EVENT_FPGAMGRHSTIMEOUT    = 0x02000000,
-
-    /*! SCAN manager handshake Timeout       */
-    ALT_RESET_EVENT_SCANHSTIMEOUT       = 0x04000000,
-
-    /*! FPGA handshake Timeout               */
-    ALT_RESET_EVENT_FPGAHSTIMEOUT       = 0x08000000,
-
-    /*! ETR Stall Timeout                    */
-    ALT_RESET_EVENT_ETRSTALLTIMEOUT     = 0x10000000
-} ALT_RESET_EVENT_t;
-
-/******************************************************************************/
-/*!
- * Gets the reset and timeout events that caused the last reset.
- *
- * The ALT_RESET_EVENT_t enumeration values should be used to selectively
- * examine the returned reset cause(s).
- *
- * \returns     A mask of the reset and/or timeout events that caused the last
- *              reset.
- */
-uint32_t alt_reset_event_get(void);
-
-/******************************************************************************/
-/*!
- * Clears the reset and timeout events that caused the last reset.
- *
- * \param       event_mask
- *              A mask of the selected reset and timeout events to clear in the
- *              Reset Manager \e stat register. The mask selection can be formed
- *              using the ALT_RESET_EVENT_t enumeration values.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask);
-
-/*! @} */
-
-/******************************************************************************/
-/*! \addtogroup RST_MGR_CTRL Reset Control
- *
- * This functional group provides global and selective reset control for the SoC
- * and its constituent modules.
- *
- * @{
- */
-
-/******************************************************************************/
-/*!
- * Initiate a cold reset of the SoC.
- *
- * If this function is successful, then it should never return.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_reset_cold_reset(void);
-
-/******************************************************************************/
-/*!
- * Initiate a warm reset of the SoC.
- *
- * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced
- * reset handshake with certain modules can optionally be requested in an
- * attempt to ensure an orderly reset transition.
- *
- * \param       warm_reset_delay
- *              Specifies the number of cycles after the Reset Manager releases
- *              the Clock Manager reset before releasing any other hardware
- *              controlled resets. Value must be greater than 16 and less than
- *              256.
- *
- * \param       nRST_pin_clk_assertion
- *              Specifies that number of clock cycles (osc1_clk?) to externally
- *              assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <=
- *              (2**20 - 1). A value of 0 prevents any assertion of nRST.
- *
- * \param       sdram_refresh
- *              Controls whether the contents of SDRAM survive a hardware
- *              sequenced warm reset. The reset manager requests the SDRAM
- *              controller to put SDRAM devices into self-refresh mode before
- *              asserting warm reset signals. An argument value of \b true
- *              enables the option, \b false disables the option.
- *
- * \param       fpga_mgr_handshake
- *              Controls whether a handshake between the reset manager and FPGA
- *              manager occurs before a warm reset. The handshake is used to
- *              warn the FPGA manager that a warm reset is imminent so it can
- *              prepare for it by driving its output clock to a quiescent state
- *              to avoid glitches. An argument value of \b true enables the
- *              option, \b false disables the option.
- *
- * \param       scan_mgr_handshake
- *              Controls whether a handshake between the reset manager and scan
- *              manager occurs before a warm reset. The handshake is used to
- *              warn the scan manager that a warm reset is imminent so it can
- *              prepare for it by driving its output clock to a quiescent state
- *              to avoid glitches. An argument value of \b true enables the
- *              option, \b false disables the option.
- *
- * \param       fpga_handshake
- *              Controls whether a handshake between the reset manager and the
- *              FPGA occurs before a warm reset. The handshake is used to warn
- *              the FPGA that a warm reset is imminent so that the FPGA prepare
- *              for the reset event in soft IP. An argument value of \b true
- *              enables the option, \b false disables the option.
- *
- * \param       etr_stall
- *              Controls whether the ETR is requested to idle its AXI master
- *              interface (i.e. finish outstanding transactions and not initiate
- *              any more) to the L3 Interconnect before a warm reset. An
- *              argument value of \b true enables the option, \b false disables
- *              the option.
- *
- * \retval      ALT_E_SUCCESS   The operation was succesful.
- * \retval      ALT_E_ERROR     The operation failed.
- */
-ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
-                                     uint32_t nRST_pin_clk_assertion,
-                                     bool sdram_refresh,
-                                     bool fpga_mgr_handshake,
-                                     bool scan_mgr_handshake,
-                                     bool fpga_handshake,
-                                     bool etr_stall);
-
-#if 0
-/*! \addtogroup RST_MGR_MPU 
- *
- * This functional group provides reset control for the Cortex-A9 MPU module.
- *
- * @{
- */
-
-/*! @} */
-
-/*! \addtogroup RST_MGR_PERIPH
- *
- * This functional group provides inidividual reset control for the HPS
- * peripheral modules.
- *
- * @{
- */
-
-/*! @} */
-
-/*! \addtogroup RST_MGR_BRG
- *
- * This functional group provides inidividual reset control for the bridge
- * interfaces between the HPS and FPGA.
- *
- * @{
- */
-
-/*! @} */
-
-/*! \addtogroup RST_MGR_MISC
- *
- * This functional group provides inidividual reset control for miscellaneous
- * HPS modules.
- *
- * @{
- */
-
-/*! @} */
-
-#endif
-
-/*! @} */
-
-/*! @} */
-
-#ifdef __cplusplus
-}
-#endif  /* __cplusplus */
-#endif  /* __ALT_RESET_MGR_H__ */

bsps/arm/altera-cyclone-v/include/bsp/hwlib.h

@@ -1,195 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/******************************************************************************
-*
-* Copyright 2013 Altera Corporation. All Rights Reserved.
-* 
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* 
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 
-* 3. The name of the author may not be used to endorse or promote products
-* derived from this software without specific prior written permission.
-* 
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-* OF SUCH DAMAGE.
-* 
-******************************************************************************/
-
-#ifndef __HWLIB_H__
-#define __HWLIB_H__
-
-#ifdef __cplusplus
-#include <cstddef>
-#include <cstdbool>
-#include <cstdint>
-#else   /* __cplusplus */
-#include <stddef.h>
-#include <stdbool.h>
-#include <stdint.h>
-#endif  /* __cplusplus */
-
-#include "alt_hwlibs_ver.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-/*!
- * The type definition for status codes returned by the HWLIB.
- */
-typedef int32_t             ALT_STATUS_CODE;
-
-/*! Definitions of status codes returned by the HWLIB. */
-
-/*! The operation was successful. */
-#define ALT_E_SUCCESS               0
-
-/*! The operation failed. */
-#define ALT_E_ERROR                 (-1)
-/*! FPGA configuration error detected.*/
-#define ALT_E_FPGA_CFG              (-2)
-/*! FPGA CRC error detected. */
-#define ALT_E_FPGA_CRC              (-3)
-/*! An error occurred on the FPGA configuration bitstream input source. */
-#define ALT_E_FPGA_CFG_STM          (-4)
-/*! The FPGA is powered off. */
-#define ALT_E_FPGA_PWR_OFF          (-5)
-/*! The SoC does not currently control the FPGA. */
-#define ALT_E_FPGA_NO_SOC_CTRL      (-6)
-/*! The FPGA is not in USER mode. */
-#define ALT_E_FPGA_NOT_USER_MODE    (-7)
-/*! An argument violates a range constraint. */
-#define ALT_E_ARG_RANGE             (-8)
-/*! A bad argument value was passed. */
-#define ALT_E_BAD_ARG               (-9)
-/*! The operation is invalid or illegal. */
-#define ALT_E_BAD_OPERATION         (-10)
-/*! An invalid option was selected. */
-#define ALT_E_INV_OPTION            (-11)
-/*! An operation or response timeout period expired. */
-#define ALT_E_TMO                   (-12)
-/*! The argument value is reserved or unavailable. */
-#define ALT_E_RESERVED              (-13)
-/*! A clock is not enabled or violates an operational constraint. */
-#define ALT_E_BAD_CLK               (-14)
-/*! The version ID is invalid. */
-#define ALT_E_BAD_VERSION           (-15)
-/*! The buffer does not contain enough free space for the operation. */
-#define ALT_E_BUF_OVF               (-20)
-
-/*!
- * Indicates a FALSE condition.
- */
-#define ALT_E_FALSE                 (0)
-/*!
- * Indicates a TRUE condition.
- */
-#define ALT_E_TRUE                  (1)
-
-/* Note, additional positive status codes may be defined to return
- * a TRUE condition with additional information */
-
-
-/* Some other useful definitions */
-
-/*!
- * Specifies the current major and minor revision of the HWLibs. The
- * MS four decimal digits specify the Altera ACDS release number, the
- * LS two decimal digits specify minor revisions of the HWLibs, if any.
- *
- * A typical use is:
- * \code
- * #if  ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0)
- * \endcode
- *     for a dependency on the major or minor ACDS revision
- *   or
- * \code
- * #if  ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12)
- * \endcode
- *     for a dependency on the hwlibs revision
- *
- */
-#define ALT_HWLIBS_VERSION(a,b,c)   (((a)*10000)+((b)*100)+(c))
-
-#define ALTERA_HWLIBS_VERSION_CODE   ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \
-                                    ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV)
-
-/*!
- * Allow some parts of the documentation to be hidden by setting to zero
- */
-#define ALTERA_INTERNAL_ONLY_DOCS   1
-
-
-/*!
- * Provide base address of MPU address space
- */
-
-#ifndef ALT_HPS_ADDR
-#define ALT_HPS_ADDR            0
-#endif
-
-/*!
- * These constants are sometimes useful:
- */
-#define ALT_MILLISECS_IN_A_SEC      1000
-#define ALT_MICROSECS_IN_A_SEC      1000000
-#define ALT_NANOSECS_IN_A_SEC       1000000000
-
-#define ALT_TWO_TO_POW0             (1)
-#define ALT_TWO_TO_POW1             (1<<1)
-#define ALT_TWO_TO_POW2             (1<<2)
-#define ALT_TWO_TO_POW3             (1<<3)
-#define ALT_TWO_TO_POW4             (1<<4)
-#define ALT_TWO_TO_POW5             (1<<5)
-#define ALT_TWO_TO_POW6             (1<<6)
-#define ALT_TWO_TO_POW7             (1<<7)
-#define ALT_TWO_TO_POW8             (1<<8)
-#define ALT_TWO_TO_POW9             (1<<9)
-#define ALT_TWO_TO_POW10            (1<<10)
-#define ALT_TWO_TO_POW11            (1<<11)
-#define ALT_TWO_TO_POW12            (1<<12)
-#define ALT_TWO_TO_POW13            (1<<13)
-#define ALT_TWO_TO_POW14            (1<<14)
-#define ALT_TWO_TO_POW15            (1<<15)
-#define ALT_TWO_TO_POW16            (1<<16)
-#define ALT_TWO_TO_POW17            (1<<17)
-#define ALT_TWO_TO_POW18            (1<<18)
-#define ALT_TWO_TO_POW19            (1<<19)
-#define ALT_TWO_TO_POW20            (1<<20)
-#define ALT_TWO_TO_POW21            (1<<21)
-#define ALT_TWO_TO_POW22            (1<<22)
-#define ALT_TWO_TO_POW23            (1<<23)
-#define ALT_TWO_TO_POW24            (1<<24)
-#define ALT_TWO_TO_POW25            (1<<25)
-#define ALT_TWO_TO_POW26            (1<<26)
-#define ALT_TWO_TO_POW27            (1<<27)
-#define ALT_TWO_TO_POW28            (1<<28)
-#define ALT_TWO_TO_POW29            (1<<29)
-#define ALT_TWO_TO_POW30            (1<<30)
-#define ALT_TWO_TO_POW31            (1<<31)
-
-#ifdef __cplusplus
-}
-#endif  /* __cplusplus */
-#endif  /* __HWLIB_H__ */
-

bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h

@@ -1,94 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVI2C
- */
-
-/*
- * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Dornierstr. 4
- *  82178 Puchheim
- *  Germany
- *  <info@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef I2CDRV_H
-#define I2CDRV_H
-
-#include <rtems.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/**
- * @defgroup RTEMSBSPsARMCycVI2C I2C Driver
- *
- * @ingroup RTEMSBSPsARMCycV
- *
- * @brief I2C Driver.
- *
- * @{
- */
-
-rtems_device_driver i2cdrv_initialize(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-);
-
-rtems_device_driver i2cdrv_open(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-);
-
-rtems_device_driver i2cdrv_close(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-);
-
-rtems_device_driver i2cdrv_read(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-);
-
-rtems_device_driver i2cdrv_write(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-);
-
-rtems_device_driver i2cdrv_ioctl(
-  rtems_device_major_number major,
-  rtems_device_minor_number minor,
-  void *arg
-);
-
-#define I2C_DRIVER_TABLE_ENTRY \
-  { \
-    i2cdrv_initialize, \
-    i2cdrv_open, \
-    i2cdrv_close, \
-    i2cdrv_read, \
-    i2cdrv_write, \
-    i2cdrv_ioctl \
-  }
-
-#define I2C_IOC_SET_SLAVE_ADDRESS 1
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* I2CDRV_H */

bsps/arm/altera-cyclone-v/include/bsp/irq.h

@@ -1,61 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVIRQ
- */
-
-/*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Dornierstr. 4
- *  82178 Puchheim
- *  Germany
- *  <info@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
-#define LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
-
-#ifndef ASM
-
-#include <rtems/irq.h>
-#include <rtems/irq-extension.h>
-
-#include <bsp/arm-a9mpcore-irq.h>
-#include <bsp/arm-gic-irq.h>
-#include <bsp/alt_interrupt_common.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/**
- * @defgroup RTEMSBSPsARMCycVIRQ Interrupt Support
- *
- * @ingroup RTEMSBSPsARMCycV
- *
- * @ingroup bsp_interrupt
- *
- * @brief Intel Cyclone V Interrupt Support.
- *
- * @{
- */
-
-/* Use interrupt IDs as defined in alt_interrupt_common.h */
-#define BSP_INTERRUPT_VECTOR_MIN ALT_INT_INTERRUPT_SGI0
-#define BSP_INTERRUPT_VECTOR_MAX ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* ASM */
-
-#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */

bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h

@@ -1,150 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/*******************************************************************************
-*                                                                              *
-* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
-*                                                                              *
-* Redistribution and use in source and binary forms, with or without           *
-* modification, are permitted provided that the following conditions are met:  *
-*                                                                              *
-* 1. Redistributions of source code must retain the above copyright notice,    *
-*    this list of conditions and the following disclaimer.                     *
-*                                                                              *
-* 2. Redistributions in binary form must reproduce the above copyright notice, *
-*    this list of conditions and the following disclaimer in the documentation *
-*    and/or other materials provided with the distribution.                    *
-*                                                                              *
-* 3. The name of the author may not be used to endorse or promote products     *
-*    derived from this software without specific prior written permission.     *
-*                                                                              *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
-* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
-*                                                                              *
-*******************************************************************************/
-
-/* Altera - ALT_DMANONSECURE */
-
-#ifndef __ALTERA_ALT_DMANONSECURE_H__
-#define __ALTERA_ALT_DMANONSECURE_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-/*
- * Component : nonsecure DMA Module Address Space - ALT_DMANONSECURE
- * nonsecure DMA Module Address Space
- * 
- * Address space allocated to the nonsecure DMA. For detailed information about the
- * use of this address space,
- * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click
- * here[/url] to access the ARM documentation for the DMA-330.
- * 
- */
-/*
- * Register : Empty - reg
- * 
- * Placeholder
- * 
- * Register Layout
- * 
- *  Bits   | Access | Reset   | Description
- * :-------|:-------|:--------|:------------
- *  [31:0] | RW     | Unknown | Empty      
- * 
- */
-/*
- * Field : Empty - fld
- * 
- * Placeholder
- * 
- * Field Access Macros:
- * 
- */
-/* The Least Significant Bit (LSB) position of the ALT_DMANONSECURE_REG_FLD register field. */
-#define ALT_DMANONSECURE_REG_FLD_LSB        0
-/* The Most Significant Bit (MSB) position of the ALT_DMANONSECURE_REG_FLD register field. */
-#define ALT_DMANONSECURE_REG_FLD_MSB        31
-/* The width in bits of the ALT_DMANONSECURE_REG_FLD register field. */
-#define ALT_DMANONSECURE_REG_FLD_WIDTH      32
-/* The mask used to set the ALT_DMANONSECURE_REG_FLD register field value. */
-#define ALT_DMANONSECURE_REG_FLD_SET_MSK    0xffffffff
-/* The mask used to clear the ALT_DMANONSECURE_REG_FLD register field value. */
-#define ALT_DMANONSECURE_REG_FLD_CLR_MSK    0x00000000
-/* The reset value of the ALT_DMANONSECURE_REG_FLD register field is UNKNOWN. */
-#define ALT_DMANONSECURE_REG_FLD_RESET      0x0
-/* Extracts the ALT_DMANONSECURE_REG_FLD field value from a register. */
-#define ALT_DMANONSECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0)
-/* Produces a ALT_DMANONSECURE_REG_FLD register field value suitable for setting the register. */
-#define ALT_DMANONSECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff)
-
-#ifndef __ASSEMBLY__
-/*
- * WARNING: The C register and register group struct declarations are provided for
- * convenience and illustrative purposes. They should, however, be used with
- * caution as the C language standard provides no guarantees about the alignment or
- * atomicity of device memory accesses. The recommended practice for writing
- * hardware drivers is to use the SoCAL access macros and alt_read_word() and
- * alt_write_word() functions.
- * 
- * The struct declaration for register ALT_DMANONSECURE_REG.
- */
-struct ALT_DMANONSECURE_REG_s
-{
-    uint32_t  fld : 32;  /* Empty */
-};
-
-/* The typedef declaration for register ALT_DMANONSECURE_REG. */
-typedef volatile struct ALT_DMANONSECURE_REG_s  ALT_DMANONSECURE_REG_t;
-#endif  /* __ASSEMBLY__ */
-
-/* The byte offset of the ALT_DMANONSECURE_REG register from the beginning of the component. */
-#define ALT_DMANONSECURE_REG_OFST        0x0
-
-#ifndef __ASSEMBLY__
-/*
- * WARNING: The C register and register group struct declarations are provided for
- * convenience and illustrative purposes. They should, however, be used with
- * caution as the C language standard provides no guarantees about the alignment or
- * atomicity of device memory accesses. The recommended practice for writing
- * hardware drivers is to use the SoCAL access macros and alt_read_word() and
- * alt_write_word() functions.
- * 
- * The struct declaration for register group ALT_DMANONSECURE.
- */
-struct ALT_DMANONSECURE_s
-{
-    volatile ALT_DMANONSECURE_REG_t  reg;  /* ALT_DMANONSECURE_REG */
-};
-
-/* The typedef declaration for register group ALT_DMANONSECURE. */
-typedef volatile struct ALT_DMANONSECURE_s  ALT_DMANONSECURE_t;
-/* The struct declaration for the raw register contents of register group ALT_DMANONSECURE. */
-struct ALT_DMANONSECURE_raw_s
-{
-    volatile uint32_t  reg;  /* ALT_DMANONSECURE_REG */
-};
-
-/* The typedef declaration for the raw register contents of register group ALT_DMANONSECURE. */
-typedef volatile struct ALT_DMANONSECURE_raw_s  ALT_DMANONSECURE_raw_t;
-#endif  /* __ASSEMBLY__ */
-
-
-#ifdef __cplusplus
-}
-#endif  /* __cplusplus */
-#endif  /* __ALTERA_ALT_DMANONSECURE_H__ */
-

bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h

@@ -1,150 +0,0 @@
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMCycVContrib
- */
-
-/*******************************************************************************
-*                                                                              *
-* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
-*                                                                              *
-* Redistribution and use in source and binary forms, with or without           *
-* modification, are permitted provided that the following conditions are met:  *
-*                                                                              *
-* 1. Redistributions of source code must retain the above copyright notice,    *
-*    this list of conditions and the following disclaimer.                     *
-*                                                                              *
-* 2. Redistributions in binary form must reproduce the above copyright notice, *
-*    this list of conditions and the following disclaimer in the documentation *
-*    and/or other materials provided with the distribution.                    *
-*                                                                              *
-* 3. The name of the author may not be used to endorse or promote products     *
-*    derived from this software without specific prior written permission.     *
-*                                                                              *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
-* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO  *
-* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,       *
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;  *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,     *
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR      *
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF       *
-* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                                   *
-*                                                                              *
-*******************************************************************************/
-
-/* Altera - ALT_DMASECURE */
-
-#ifndef __ALTERA_ALT_DMASECURE_H__
-#define __ALTERA_ALT_DMASECURE_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif  /* __cplusplus */
-
-/*
- * Component : secure DMA Module Address Space - ALT_DMASECURE
- * secure DMA Module Address Space
- * 
- * Address space allocated to the secure DMA. For detailed information about the
- * use of this address space,
- * [url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424b/index.html]click
- * here[/url] to access the ARM documentation for the DMA-330.
- * 
- */
-/*
- * Register : Empty - reg
- * 
- * Placeholder
- * 
- * Register Layout
- * 
- *  Bits   | Access | Reset   | Description
- * :-------|:-------|:--------|:------------
- *  [31:0] | RW     | Unknown | Empty      
- * 
- */
-/*
- * Field : Empty - fld
- * 
- * Placeholder
- * 
- * Field Access Macros:
- * 
- */
-/* The Least Significant Bit (LSB) position of the ALT_DMASECURE_REG_FLD register field. */
-#define ALT_DMASECURE_REG_FLD_LSB        0
-/* The Most Significant Bit (MSB) position of the ALT_DMASECURE_REG_FLD register field. */
-#define ALT_DMASECURE_REG_FLD_MSB        31
-/* The width in bits of the ALT_DMASECURE_REG_FLD register field. */
-#define ALT_DMASECURE_REG_FLD_WIDTH      32
-/* The mask used to set the ALT_DMASECURE_REG_FLD register field value. */
-#define ALT_DMASECURE_REG_FLD_SET_MSK    0xffffffff
-/* The mask used to clear the ALT_DMASECURE_REG_FLD register field value. */
-#define ALT_DMASECURE_REG_FLD_CLR_MSK    0x00000000
-/* The reset value of the ALT_DMASECURE_REG_FLD register field is UNKNOWN. */
-#define ALT_DMASECURE_REG_FLD_RESET      0x0
-/* Extracts the ALT_DMASECURE_REG_FLD field value from a register. */
-#define ALT_DMASECURE_REG_FLD_GET(value) (((value) & 0xffffffff) >> 0)
-/* Produces a ALT_DMASECURE_REG_FLD register field value suitable for setting the register. */
-#define ALT_DMASECURE_REG_FLD_SET(value) (((value) << 0) & 0xffffffff)
-
-#ifndef __ASSEMBLY__
-/*
- * WARNING: The C register and register group struct declarations are provided for
- * convenience and illustrative purposes. They should, however, be used with
- * caution as the C language standard provides no guarantees about the alignment or
- * atomicity of device memory accesses. The recommended practice for writing
- * hardware drivers is to use the SoCAL access macros and alt_read_word() and
- * alt_write_word() functions.
- * 
- * The struct declaration for register ALT_DMASECURE_REG.
- */
-struct ALT_DMASECURE_REG_s
-{
-    uint32_t  fld : 32;  /* Empty */
-};
-
-/* The typedef declaration for register ALT_DMASECURE_REG. */
-typedef volatile struct ALT_DMASECURE_REG_s  ALT_DMASECURE_REG_t;
-#endif  /* __ASSEMBLY__ */
-
-/* The byte offset of the ALT_DMASECURE_REG register from the beginning of the component. */
-#define ALT_DMASECURE_REG_OFST        0x0
-
-#ifndef __ASSEMBLY__
-/*
- * WARNING: The C register and register group struct declarations are provided for
- * convenience and illustrative purposes. They should, however, be used with
- * caution as the C language standard provides no guarantees about the alignment or
- * atomicity of device memory accesses. The recommended practice for writing
- * hardware drivers is to use the SoCAL access macros and alt_read_word() and
- * alt_write_word() functions.
- * 
- * The struct declaration for register group ALT_DMASECURE.
- */
-struct ALT_DMASECURE_s
-{
-    volatile ALT_DMASECURE_REG_t  reg;  /* ALT_DMASECURE_REG */
-};
-
-/* The typedef declaration for register group ALT_DMASECURE. */
-typedef volatile struct ALT_DMASECURE_s  ALT_DMASECURE_t;
-/* The struct declaration for the raw register contents of register group ALT_DMASECURE. */
-struct ALT_DMASECURE_raw_s
-{
-    volatile uint32_t  reg;  /* ALT_DMASECURE_REG */
-};
-
-/* The typedef declaration for the raw register contents of register group ALT_DMASECURE. */
-typedef volatile struct ALT_DMASECURE_raw_s  ALT_DMASECURE_raw_t;
-#endif  /* __ASSEMBLY__ */
-
-
-#ifdef __cplusplus
-}
-#endif  /* __cplusplus */
-#endif  /* __ALTERA_ALT_DMASECURE_H__ */
-