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Author SHA1 Message Date
Joel Sherrill
ff7ff62a0f 2011-05-05 Joel Sherrill <joel.sherrill@oarcorp.com> 
* psx04/task3.c, psxfile01/test.c, psxhdrs/Makefile.am,
	psxmsgq01/init.c, psxreaddir/test.c, psxsignal01/init.c,
	psxtimes01/init.c, psxualarm/init.c: Remove warnings.
 2011-05-05 16:45:52 +00:00
Joel Sherrill
6f27ba8077 2011-05-05 Joel Sherrill <joel.sherrill@oarcorp.com> 
* devnullfatal01/testcase.h, malloc02/init.c, malloc04/init.c,
	malloctest/init.c, termios03/termios_testdriver_polled.c,
	termios04/termios_testdriver_intr.c: Remove warnings.
 2011-05-05 16:45:47 +00:00
Joel Sherrill
7c1e69429a 2011-05-05 Joel Sherrill <joel.sherrill@oarcorp.com> 
* base_sp/apptask.c, base_sp/init.c, fileio/init.c, fileio/system.h,
	nsecs/init.c, ticker/init.c, ticker/system.h, ticker/tasks.c: Remove
	warnings.
 2011-05-05 16:45:40 +00:00
Ralf Corsepius
355d79fae6 2011-05-05 Ralf Corsépius <ralf.corsepius@rtems.org> 
* librpc/include/rpc/auth.h, librpc/include/rpc/auth_unix.h,
	librpc/include/rpc/clnt.h, librpc/include/rpc/clnt_soc.h,
	librpc/include/rpc/pmap_clnt.h, librpc/include/rpc/pmap_prot.h,
	librpc/include/rpc/pmap_rmt.h, librpc/include/rpc/rpc_msg.h,
	librpc/include/rpc/svc.h, librpc/include/rpc/svc_auth.h,
	librpc/include/rpc/svc_soc.h: Make self-contained.
 2011-05-05 12:30:36 +00:00
Ralf Corsepius
bc38915f90 Make self-contained. 2011-05-05 12:30:09 +00:00
Ralf Corsepius
56a1d1cdf7 Abandon _without_sources. 2011-05-05 12:00:37 +00:00
Ralf Corsepius
78e99f534c Regenerate. 2011-05-04 15:25:21 +00:00
Ralf Corsepius
0b555d82f9 New. 2011-05-04 15:22:23 +00:00
Ralf Corsepius
b9a2aae15b gcc-4.5.3. 2011-05-04 15:21:11 +00:00
Jennifer Averett
15cf2cb507 2011-04-27 Jennifer Averett <Jennifer.Averett@OARcorp.com> 
PR 1784
	* sptests/spsize/size.c: Split bspsmp.h into two files smp.h and
	bspsmp.h
 2011-04-27 17:20:35 +00:00
Jennifer Averett
0d5a9f1bb7 2011-04-27 Jennifer Averett <Jennifer.Averett@OARcorp.com> 
PR 1784
	* sapi/src/exinit.c, score/Makefile.am, score/preinstall.am,
	score/include/rtems/bspsmp.h, score/src/percpu.c, score/src/smp.c,
	score/src/threadcreateidle.c: Split bspsmp.h into two files smp.h and
	bspsmp.h
	* score/include/rtems/score/smp.h: New file.
 2011-04-27 17:18:59 +00:00
Ralf Corsepius
5f82db901b Regenerate. 2011-04-27 16:43:23 +00:00
Ralf Corsepius
e8e60bfa5c w32api-3.17-2. 2011-04-27 16:43:09 +00:00
Ralf Corsepius
663310ac4b Regenerate. 2011-04-27 16:38:51 +00:00
Ralf Corsepius
a33220f378 w32api-3.17-1. 2011-04-27 16:38:28 +00:00
Ralf Corsepius
feead8bf30 Housekeeping. 2011-04-27 16:37:36 +00:00
Ralf Corsepius
2f7574f1b6 Regenerate. 2011-04-27 15:54:04 +00:00
Ralf Corsepius
f143baf0f3 Housekeeping. 2011-04-27 15:53:51 +00:00
Ralf Corsepius
db7332bf6f cygwin-1.7.9-1 2011-04-27 15:53:14 +00:00
Ralf Corsepius
0c18a8604a Regenerate. 2011-04-27 15:36:41 +00:00
Ralf Corsepius
f0c27b4f9b Housekeeping. 2011-04-27 15:36:10 +00:00
Ralf Corsepius
c118117711 Cygwin binutils-2.20.51-2. 2011-04-27 15:34:00 +00:00
Ralf Corsepius
6bbc5e0fd6 Make sure not to be using GPLed parts of newlib. 2011-04-27 12:25:13 +00:00
Ralf Corsepius
18b885ea8a Preps for gcc-4.5.3. 2011-04-27 08:21:01 +00:00
Ralf Corsepius
8b11074e4d Preps for fedora 16. 2011-04-27 08:16:21 +00:00
Joel Sherrill
a87878bfc4 2011-04-25 Jennifer Averett <jennifer.averett@OARcorp.com> 
PR 1783/bsps
	* include/bsp.h: Remove dead prototypes of Clock_delay() and delay().
	Neither had bodies.
 2011-04-25 19:39:31 +00:00
Jennifer Averett
fe40096f2e 2011-04-25 Jennifer Averett <Jennifer.Averett@OARcorp.com> 
* score/include/rtems/bspsmp.h: Did some prototype cleanup.
 2011-04-25 15:06:41 +00:00
Ralf Corsepius
9e01d150f5 New. 2011-04-23 08:34:46 +00:00
Ralf Corsepius
ae312f4725 Regenerate. 2011-04-22 22:19:35 +00:00
Ralf Corsepius
2f873e3b76 GCC_RPMREL = 9, 2011-04-22 22:17:05 +00:00
Ralf Corsepius
2c368ef226 newlib-1.19.0-rtems4.11-20110423.diff 2011-04-22 22:02:20 +00:00
Ralf Corsepius
be654f48e8 New. 2011-04-22 21:58:38 +00:00
Joel Sherrill
451a46fae0 2011-04-22 Joel Sherrill <joel.sherrill@oarcorp.com> 
PR 1782/cpukit
	* porting/taskcontext.t: Disable deferred FPU context switches when SMP
	is enabled. Per code tracking of deferred contexts is not
	implemented.
 2011-04-22 17:54:38 +00:00
Joel Sherrill
f78831f13b 2011-04-22 Joel Sherrill <joel.sherrill@oarcorp.com> 
PR 1782/cpukit
	* score/include/rtems/score/thread.h: Disable deferred FPU context
	switches when SMP is enabled. Per code tracking of deferred contexts
	is not implemented.
 2011-04-22 17:54:31 +00:00
Joel Sherrill
4802bfabc8 2011-04-22 Joel Sherrill <joel.sherrilL@OARcorp.com> 
* console/console.c: Now compiles.
 2011-04-22 17:07:51 +00:00
Jennifer Averett
469a993f14 2011-04-21 Jennifer Averett <Jennifer.Averett@OARcorp.com 
PR 1777/cpukit
	* tools/schedsim/rtems/rtems_init.c: Consolidated access to
	_Thread_Dispatch_disable_level.
 2011-04-21 19:09:13 +00:00
Jennifer Averett
1c95d94af6 2011-04-21 Jennifer Averett <Jennifer.Averett@OARcorp.com 
PR 1777/cpukit
	* support/include/tmacros.h, tmtests/tm26/task1.c,
	tmtests/tm27/task1.c: Consolidated access to
	_Thread_Dispatch_disable_level.
 2011-04-21 19:05:34 +00:00
Jennifer Averett
d7c388321a 2011-04-21 Jennifer Averett <Jennifer.Averett@OARcorp.com 
PR 1777/cpukit
	* libcsupport/src/malloc_deferred.c, libcsupport/src/realloc.c,
	score/Makefile.am, score/cpu/lm32/irq.c, score/cpu/nios2/irq.c,
	score/include/rtems/score/coremutex.h,
	score/include/rtems/score/thread.h,
	score/inline/rtems/score/thread.inl, score/src/heapfree.c,
	score/src/pheapwalk.c, score/src/smp.c, score/src/threaddispatch.c:
	Consolidated access to _Thread_Dispatch_disable_level.
	* score/src/threaddisabledispatch.c, score/src/threadenabledispatch.c:
	New files.
 2011-04-21 19:05:15 +00:00
Jennifer Averett
85f5c14bd0 2011-04-21 Jennifer Averett <Jennifer.Averett@OARcorp.com 
PR 1777/cpukit
	* src/lib/libbsp/powerpc/shared/startup/panic.c,
	src/lib/libcpu/sh/sh7032/score/cpu_asm.c,
	src/lib/libcpu/sh/sh7045/score/cpu_asm.c,
	src/lib/libcpu/sh/sh7750/score/cpu_asm.c,
	src/lib/libcpu/sh/shgdb/score/cpu_asm.c: Consolidated access to
	_Thread_Dispatch_disable_level.
 2011-04-21 19:04:50 +00:00
Joel Sherrill
0e89af816c 2011-04-20 Joel Sherrill <joel.sherrill@oarcorp.com> 
* configure.ac: Add fstests.
 2011-04-20 21:30:36 +00:00
Joel Sherrill
a2f875f222 2011-04-20 Joel Sherrill <joel.sherrill@oarcorp.com> 
Add initial test to File System Test Suite.
	* .cvsignore, ChangeLog, Makefile.am, configure.ac, fs01/fs91.doc,
	fs01/init.c, imfs_fs01/.cvsignore, imfs_fs01/Makefile.am,
	imfs_fs01/imfs_fs01.scn, imfs_support/fs_config.h,
	imfs_support/fs_support.c, mimfs_fs01/.cvsignore,
	mimfs_fs01/Makefile.am, mimfs_fs01/mimfs_fs01.scn,
	mimfs_support/fs_config.h, mimfs_support/fs_support.c: New files.
 2011-04-20 21:30:15 +00:00
Joel Sherrill
25e9d2fb93 2011-04-20 Joel Sherrill <joel.sherrilL@OARcorp.com> 
* acinclude.m4: Regenerated for TLL6527M.
 2011-04-20 20:25:06 +00:00
Joel Sherrill
550e2efc0f 2011-04-20 Joel Sherrill <joel.sherrilL@OARcorp.com> 
* console/console-io.c: Regenerated for TLL6527M.
 2011-04-20 20:24:41 +00:00
Joel Sherrill
ad65fc7fb7 2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu> 
PR 1781/bsps
	* ChangeLog, Makefile.am, README, bsp_specs, configure.ac,
	preinstall.am, times, console/console.c, include/bsp.h,
	include/cplb.h, include/tm27.h, make/custom/TLL6527M.cfg,
	startup/bspstart.c, startup/linkcmds: New files.
	Initial port for the TLL6527Mboard that contains blackfin 52X
	range of processors. Used eZKit533 as a reference for building
	the port.
 2011-04-20 20:23:39 +00:00
Joel Sherrill
cb4c90b227 2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu> 
PR 1781/bsps
	* bf52x/include: Added additional MMR.
	* bf52x/interrupt: The BF52X processors have a different
	System interrupt controller than present in the 53X range of
	processors. The 52X have 8 interrupt assignment registers. The
	implementation uses tables to increase predictability.
	* serial/uart.?: Added DMA based and interrupt based transfer
	support. The uart code used a single ISR for TX and RX and tried
	to identify and multiplex inside the ISR. In the new code the
	type of interrupt is identified by the central ISR dispatcher
	bf52x/interrupt or interrupt/.	This simplifies the UART ISR.
 2011-04-20 20:20:47 +00:00
Joel Sherrill
5eb50f38e9 2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu> 
PR 1781/bsps
	* console/console-io.c: The UART RX and TX are different ISR
	now. So the array containing the registeration changes. The
	change is due to change in the libcup uart function.
 2011-04-20 20:20:17 +00:00
Joel Sherrill
ca11004d24 2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu> 
PR 1781/bsps
	* bfin/rtems/bf52x.h: This file defines basic MMR for the Blackfin
	52x CPU.  The MMR have been taken from the ADSP-BF52x Blackfin
	Processor Hardware Reference from Analog Devices. Mentioned
	Chapters refer to this Documentation.
 2011-04-20 20:19:08 +00:00
Joel Sherrill
0e501eae8f 2011-04-20 Joel Sherrill <joel.sherrill@oarcorp.com> 
* README, psxtmtests_plan.csv: Add more possible test cases.
 2011-04-20 16:22:14 +00:00
Ralf Corsepius
b714a34a8b Add gcc/base-go.add and gcc/target-go.add. 2011-04-20 13:53:39 +00:00
Ralf Corsepius
19527c6a3f Eliminate $optargs 2011-04-20 13:36:33 +00:00