The i.MXRT1166 has three iomux controllers. The driver in RTEMS
(originally for i.MX6) doesn't support that. Switching to absolute
addresses for the pins in the FDT works around that.
Compared to changing the IOMUX driver, it has the following advantages:
- If a devicetree is written, the pinctrl-groups don't have to be split
up between different iomux controllers which makes device trees simpler
to read.
- A driver or application doesn't has to handle multiple pinctrl-groups
which simplifies the drivers.
The C files that provide the device trees are generated with
rtems-bin2c. Due to that, the license information in these files is
lost. Therefore this patch adds the header manually. Also adapt the
commands that are used to generate the files to reflect that.
This makes the active level of the FDT available to the user. It doesn't
change the current behaviour. It only provides a function to get the
active or inactive level of a pin.
## Implement a new ST Nucleo STM32H755ZI BSP
Hi all, for a project I recently acquired a Nucleo STM32H755ZI. Thanks to the work of @sebhub, @c-mauderer, and Karel Gardas, it was pretty easy to create a new Nucleo BSP for this chip by copying the Nucleo H743 BSP. I was not able to get the 8 MHz HSE clock enabled, so this is currently clocked off of the PLL using the 64 MHz HSI clock and the RTC clock is disabled. Other features haven't been thoroughly tested, but since they rely on the high quality STM32H7 HAL from ST, I have pretty high confidence in them. I've been able to run most testsuites.
I have tested:
* The CM7 core
* The CM4 core
* Console output on UART3 (the default USB UART) and the shell
* GPIO
* Sample programs like `hello`, `fileio` (and shell), `paranoia`, `unlimited`, etc.
Known Broken:
* Debugging with OpenOCD is wonky. I can set breakpoints, halt the processor and inspect memory and registers and return from functions, but stepping does not work.
* The program begins to run after being flashed but soon (under 1 second) stops running. Pressing the reset button makes the program run continuously afterward. The board resets nearly instantly.
* Shell commands `ls`, `cd`, `cpuuse`, etc. hang for a while before executing. I'm not sure where the time is spent because the built-in `time` command reports that these commands execute nearly instantly.
I haven't tested:
* Pretty much everything else
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This function may be used to ensure that a count of processors performed a set
of actions and then wait on the barrier performing only memory loads (no memory
stores).
The clock tick rate was off by a factor of two in some configurations.
Use the maximum counter frequency to get the best time resolution. Do
not use the automatic interrupt clear feature.
Update #4982.
The rtems_cache_get_data_cache_size() and
rtems_cache_get_instruction_cache_size() functions shall return the entire
cache size for a level of 0. Levels greater than 0 shall return the size of
the associated level.
Update #4982.
Created an helper method that will be called by rtems_aio_handle().
The method will process the various types of aio requests.
Converted the old style documentation to Doxygen.
Formatted the code to adhere to rtems formatting rules.
Closes#5017
The _ARMV7M_Pendable_service_call() and _ARMV7M_Supervisor_call() work
as a team. The --ef and ++ef is there to preserve the original exception
frame across the jump to and from _ARMV7M_Thread_dispatch().
void _ARMV7M_Pendable_service_call( void )
{
Per_CPU_Control *cpu_self = _Per_CPU_Get();
/*
* We must check here if a thread dispatch is allowed. Right after a
* "msr basepri_max, %[basepri]" instruction an interrupt service may
still
* take place. However, pendable service calls that are activated during
* this interrupt service may be delayed until interrupts are enable
again.
*/
if (
( cpu_self->isr_nest_level |
cpu_self->thread_dispatch_disable_level ) == 0
) {
ARMV7M_Exception_frame *ef;
cpu_self->isr_nest_level = 1;
_ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR;
_ARMV7M_Trigger_lazy_floating_point_context_save();
At this point, the floating point context should be saved on the
exception frame. The FPCCR.LSPACT bit should be 0, to indicate that lazy
state preservation is no longer active.
ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
--ef;
_ARMV7M_Set_PSP( (uint32_t) ef );
This new exception frame is just there to jump to
_ARMV7M_Thread_dispatch(). Here was the problem, that FPCCR.LSPACT was
not set to 1. This resulted in a floating-point context from
uninitialized memory which could corrupt the floating-point state. See
also:
https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Level-Programmers--Model/ARMv7-M-exception-model/Exception-return-behavior?lang=en
/*
* According to "ARMv7-M Architecture Reference Manual" section B1.5.6
* "Exception entry behavior" the return address is half-word aligned.
*/
ef->register_pc = (void *)
((uintptr_t) _ARMV7M_Thread_dispatch & ~((uintptr_t) 1));
ef->register_xpsr = 0x01000000U;
}
}
Close#4923.
Makes the code in bsp/x86_64/amd64/start/start.S and the stack frame
setup by _CPU_Context_Initialize align the stack properly according to
what is expected by the x86-64 SysV ABI
Interrupt IDs 1020, 1021, 1022, and 1023 are reserved as special INTIDs
and should be ignored for normal RTEMS operation as they signal internal
changes in the interrupt controller that RTEMS itself is directly
causing.
There were some problems in the math calculating RAM length and NOCACHE
origin location. These have been resolved in this patch allowing RTEMS
RAM space to be relocated above 0xfe00000 to better accomodate other
elements in the system.
In e95dabc77 approvers/maintainer was moved to general/maintainer. It was moved
back in the last commit to test permissions though I forgot to note it there.
Re-add since things are working as expected.
This change is to avoid anyone who is in the 'approvers' group for maintenance
showing up as approvers. Access goes only one level up from the current group
so having approval groups one level down was causing issues with me, Chris and
Kinsey showing up.
Add directives to get and set the priority of an interrupt vector.
Implement the directives for the following BSP families:
* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq
Implement the directives for the following interrupt controllers:
* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)
Update #5002.
Move the timerfd impelemntation from linux compat code to cpukit/score/src. Use
it to implement the new system calls for timerfd. Add a hook to kern_tc
to allow timerfd to know when the system time has stepped. Add kqueue
support to timerfd. Adjust a few names to be less Linux centric.
RelNotes: YES
Reviewed by: markj (on irc), imp, kib (with reservations), jhb (slack)
Differential Revision: https://reviews.freebsd.org/D38459
