Commit Graph

31 Commits

Author SHA1 Message Date
Matt Joyce
d735d4459c bsps/stm32u5-grisp-nano: New BSP
This BSP supports a custom STM32U5 based board. It uses a similar
structure like the existing STM32H7 BSP and therefore should be well
adaptable to other boards.

Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
2025-07-02 23:41:01 -04:00
Sebastian Huber
4b1e80dff5 bsps/aarch64: Improve MMU mapping
Produce only one fatal error.  Fix potential integer overflow errors.
2024-10-11 01:27:48 +02:00
Kinsey Moore
6dee307542 bsps/stm32h7: Add SPI support
This adds support for the 6 SPI interfaces on the STM32H7 series chips
with an initial example for the stm32h750b discovery kit development
board. Configuration is similar to existing peripherals. Chip select
lines are software-controlled since the SPI peripheral only supports a
single hardware-controlled chip select line. This implementation does
not use interrupts.
2024-09-06 01:15:21 +00:00
Kinsey Moore
b48166b9b6 bsps/aarch64/zynqmp: Add memory error reporting
This adds error reporting for ZynqMP including L1 and L2 cache, on-chip
memory (OCM) error correcting code (ECC), and DDR ECC. OCM ECC supports
fault injection from within RTEMS. DDR ECC technically supports fault
injection as well, but requires that the program injecting faults
operate exclusively outside of DDR. The AArch64 port is not currently
capable of operating exclusively in OCM due to size constraints and
would need to be booted via JTAG or via a non-relocating u-boot to
accomplish this.
2024-06-21 05:57:21 +00:00
Sebastian Huber
1421b9f7c0 bsps/aarch64: Use BSP fatal error 2024-06-10 18:01:08 +00:00
Sebastian Huber
cb43ee6969 bsp/tms570: Add TMS570_FATAL_RTI_IRQ_INSTALL
Update #4982.
2024-06-04 15:50:57 +00:00
Sebastian Huber
5a8e99546f bsps/xil-ttc: Add XIL_FATAL_TTC_IRQ_INSTALL 2024-04-30 01:39:05 -04:00
Sebastian Huber
4fd930b7f0 bsp/qoriq: Use bsp_fatal() 2024-02-27 14:13:13 +01:00
Sebastian Huber
8fe0fc4721 bsps/leon3: Optional IRQ(A)MP timestamp support
This is necessary to run the tests on SIS with profiling enabled.

Update #4954.
2023-10-20 11:16:53 +02:00
Sebastian Huber
bcef89f236 Update company name
The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
2023-05-20 11:05:26 +02:00
Sebastian Huber
47d156d706 bsps/riscv: bsp_interrupt_get/set_affinity()
Provide bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
RTEMS_SMP is enabled.  Replace fatal error with a status code.
2022-11-10 08:55:38 +01:00
Martin Aberg
9ec9be834d bsp/riscv: Add NOEL-V BSP
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
  https://www.gaisler.com/NOELV

Compatible with the following NOEL-V FPGA example design ranges
available from Cobham Gaisler. Follow the links for free
bit-streams, DTS/DTB, user's manuals and quick-start guides:
- NOEL-ARTYA7-EX    (https://www.gaisler.com/NOEL-ARTYA7)
- NOEL-PF-EX        (https://www.gaisler.com/NOEL-PF)
- NOEL-XCKU-EX      (https://www.gaisler.com/NOEL-XCKU)

Uses the shared GRLIB APBUART console driver "apbuart_termios.c".
APBUART devices are probed using device tree.

Closes #4225.
2022-09-06 16:15:58 +02:00
Chris Johns
51ffa21011 aarch64/versal: Support DDRMC0 region 0 and 1
- Support DDRMC0 region 0 up to 2G in size

- Support DDRMC0 region 1 with DDR memory greater than 2G
  up to the DDRMC0 max amount

- Extend the heap with region 1's memory

Closes #4684
2022-07-28 09:04:46 +10:00
Kinsey Moore
10ef7087f6 aarch64: Use page table level 0
This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
2022-07-21 12:26:35 -05:00
Sebastian Huber
6476cdc67c bsps: Relicense <bsp/fatal.h>
Add Doxygen documentation.  Change license to BSD-2-Clause according
to file history.

Update #3053.
2022-05-18 11:34:45 +02:00
Joel Sherrill
fe6d96cc85 bsps/include/: Scripted embedded brains header file clean up
Updates #4625.
2022-03-10 08:43:50 +01:00
Alex White
d03776e804 microblaze: Rework for RTEMS 6
This reworks the existing MicroBlaze architecture port and BSP to
achieve basic functionality using the latest RTEMS APIs.
2021-10-13 14:45:37 -05:00
Sebastian Huber
01d22f7f79 bsps/leon3: Rename fatal error code
Rename LEON3_FATAL_INVALID_CACHE_CONFIG_MAIN_PROCESSOR in
LEON3_FATAL_INVALID_CACHE_CONFIG_BOOT_PROCESSOR since the term
"boot processor" is used elsewhere in the code base.
2021-09-02 09:22:38 +02:00
Jan Sommer
1343fb5f01 bsps/riscv: Add per cpu clock interrupt
- Fixes failure of test smpclock01
2021-03-23 09:17:38 +01:00
Christian Mauderer
7141afbb0e bsp/imxrt: Add new BSP
Update #4180
2020-11-20 08:53:19 +01:00
Joel Sherrill
560c08cc3d bsps/include/bsp/fatal.h: Add GRLIB specific fatal error
updates #4028.
2020-10-08 08:30:00 -05:00
Christian Mauderer
0f4b911c01 bsp/imx: Add a GPIO driver
Update 3869
2020-07-31 08:26:14 +02:00
Pragnesh Patel
a7f5e42cc5 riscv: add freedom E310 Arty A7 bsp
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2019-10-23 08:11:50 +02:00
Sebastian Huber
581a0f8866 bsp/riscv: Use interrupt driven NS16550 driver
Update #3433.
2018-07-25 10:07:44 +02:00
Sebastian Huber
adede135e7 bsp/riscv: Add PLIC support
Update #3433.
2018-07-25 10:07:44 +02:00
Sebastian Huber
447fd894ae bsp/riscv: Add basic SMP startup
Update #3433.
2018-07-25 10:07:44 +02:00
Sebastian Huber
3a263a9b02 bsp/riscv: Add and use riscv_fdt_get_address()
Update #3433.
2018-07-25 10:07:43 +02:00
Sebastian Huber
8db3f0e878 riscv: Rework exception handling
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions.  Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.
2018-07-25 10:07:43 +02:00
Sebastian Huber
1a192398bf bsp/riscv: Add console support for NS16550 devices
Update #3433.
2018-07-06 14:27:39 +02:00
Sebastian Huber
cdfed94f34 bsp/riscv: Rework clock driver
Use device tree provided timebase frequency.  Do not write to read-only
mtime register.

Update #3433.
2018-06-28 15:03:19 +02:00
Chris Johns
2afb22b7e1 Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
2018-01-25 08:45:26 +01:00