forked from Imagelibrary/rtems
10ef7087f6
This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
227 lines
7.5 KiB
C
227 lines
7.5 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsSharedFatal
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*
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* @brief This header file provides fatal codes for ::RTEMS_FATAL_SOURCE_BSP.
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*/
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/*
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* Copyright (C) 2012, 2022 embedded brains GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_SHARED_BSP_FATAL_H
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#define LIBBSP_SHARED_BSP_FATAL_H
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#include <rtems.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/**
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* @defgroup RTEMSBSPsSharedFatal BSP-Specific Fatal Codes
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*
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* @ingroup RTEMSBSPsShared
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*
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* @brief This group contains fatal codes for ::RTEMS_FATAL_SOURCE_BSP.
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*
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* @{
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*/
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#define BSP_FATAL_CODE_BLOCK(idx) ((unsigned long) (idx) * 256UL)
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/**
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* @brief BSP fatal error codes.
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*/
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typedef enum {
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/* Generic BSP fatal codes */
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BSP_FATAL_INTERRUPT_INITIALIZATION = BSP_FATAL_CODE_BLOCK(0),
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BSP_FATAL_SPURIOUS_INTERRUPT,
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BSP_FATAL_CONSOLE_MULTI_INIT,
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BSP_FATAL_CONSOLE_NO_MEMORY_0,
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BSP_FATAL_CONSOLE_NO_MEMORY_1,
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BSP_FATAL_CONSOLE_NO_MEMORY_2,
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BSP_FATAL_CONSOLE_NO_MEMORY_3,
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BSP_FATAL_CONSOLE_REGISTER_DEV_0,
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BSP_FATAL_CONSOLE_REGISTER_DEV_1,
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BSP_FATAL_CONSOLE_NO_DEV,
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BSP_FATAL_CONSOLE_INSTALL_0,
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BSP_FATAL_CONSOLE_INSTALL_1,
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BSP_FATAL_CONSOLE_REGISTER_DEV_2,
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BSP_FATAL_MMU_ADDRESS_INVALID,
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/* ARM fatal codes */
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BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(1),
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BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE,
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BSP_ARM_PL111_FATAL_REGISTER_DEV,
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BSP_ARM_PL111_FATAL_SEM_CREATE,
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BSP_ARM_PL111_FATAL_SEM_RELEASE,
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BSP_ARM_A9MPCORE_FATAL_CLOCK_SMP_INIT,
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BSP_ARM_ARMV7M_CPU_COUNTER_INIT,
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BSP_ARM_FATAL_GENERIC_TIMER_CLOCK_IRQ_INSTALL,
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/* LEON3 fatal codes */
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LEON3_FATAL_NO_IRQMP_CONTROLLER = BSP_FATAL_CODE_BLOCK(2),
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LEON3_FATAL_CONSOLE_REGISTER_DEV,
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LEON3_FATAL_CLOCK_INITIALIZATION,
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LEON3_FATAL_INVALID_CACHE_CONFIG_BOOT_PROCESSOR,
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LEON3_FATAL_INVALID_CACHE_CONFIG_SECONDARY_PROCESSOR,
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LEON3_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT,
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/* LPC24XX fatal codes */
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LPC24XX_FATAL_PL111_SET_UP = BSP_FATAL_CODE_BLOCK(3),
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LPC24XX_FATAL_PL111_PINS_SET_UP,
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LPC24XX_FATAL_PL111_PINS_TEAR_DOWN,
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LPC24XX_FATAL_PL111_TEAR_DOWN,
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/* MPC5200 fatal codes */
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MPC5200_FATAL_PCF8563_INVALID_YEAR = BSP_FATAL_CODE_BLOCK(4),
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MPC5200_FATAL_SLICETIMER_0_IRQ_INSTALL,
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MPC5200_FATAL_SLICETIMER_1_IRQ_INSTALL,
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MPC5200_FATAL_TM27_IRQ_INSTALL,
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MPC5200_FATAL_MSCAN_A_INIT,
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MPC5200_FATAL_MSCAN_B_INIT,
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MPC5200_FATAL_MSCAN_A_SET_MODE,
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MPC5200_FATAL_MSCAN_B_SET_MODE,
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MPC5200_FATAL_ATA_DISK_IO_INIT,
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MPC5200_FATAL_ATA_DISK_CREATE,
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MPC5200_FATAL_ATA_DMA_SINGLE_IRQ_INSTALL,
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MPC5200_FATAL_ATA_LOCK_CREATE,
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MPC5200_FATAL_ATA_LOCK_DESTROY,
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/* MPC55XX fatal codes */
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MPC55XX_FATAL_FMPLL_LOCK = BSP_FATAL_CODE_BLOCK(5),
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MPC55XX_FATAL_CLOCK_EMIOS_IRQ_INSTALL,
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MPC55XX_FATAL_CLOCK_EMIOS_PRESCALER,
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MPC55XX_FATAL_CLOCK_EMIOS_INTERVAL,
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MPC55XX_FATAL_CLOCK_PIT_IRQ_INSTALL,
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MPC55XX_FATAL_CONSOLE_GENERIC_COUNT,
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MPC55XX_FATAL_CONSOLE_GENERIC_REGISTER,
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MPC55XX_FATAL_CONSOLE_GENERIC_REGISTER_CONSOLE,
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MPC55XX_FATAL_CONSOLE_ESCI_BAUD,
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MPC55XX_FATAL_CONSOLE_ESCI_ATTRIBUTES,
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MPC55XX_FATAL_CONSOLE_ESCI_IRQ_INSTALL,
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MPC55XX_FATAL_CONSOLE_LINFLEX_BAUD,
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MPC55XX_FATAL_CONSOLE_LINFLEX_ATTRIBUTES,
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MPC55XX_FATAL_CONSOLE_LINFLEX_RX_IRQ_INSTALL,
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MPC55XX_FATAL_CONSOLE_LINFLEX_TX_IRQ_INSTALL,
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MPC55XX_FATAL_CONSOLE_LINFLEX_ERR_IRQ_INSTALL,
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MPC55XX_FATAL_CONSOLE_LINFLEX_RX_IRQ_REMOVE,
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MPC55XX_FATAL_CONSOLE_LINFLEX_TX_IRQ_REMOVE,
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MPC55XX_FATAL_CONSOLE_LINFLEX_ERR_IRQ_REMOVE,
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MPC55XX_FATAL_EDMA_IRQ_INSTALL,
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MPC55XX_FATAL_EDMA_IRQ_REMOVE,
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/* MRM332 fatal codes */
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MRM332_FATAL_SPURIOUS_INTERRUPT = BSP_FATAL_CODE_BLOCK(6),
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/* PowerPC fatal codes */
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PPC_FATAL_EXCEPTION_INITIALIZATION = BSP_FATAL_CODE_BLOCK(7),
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/* Libchip fatal codes */
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DWMAC_FATAL_TOO_MANY_RBUFS_CONFIGURED = BSP_FATAL_CODE_BLOCK(8),
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/* ARM fatal codes */
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ARM_FATAL_L2C_310_UNEXPECTED_ID = BSP_FATAL_CODE_BLOCK(9),
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ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS,
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ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG,
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/* QorIQ fatal codes */
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QORIQ_FATAL_SMP_IPI_HANDLER_INSTALL = BSP_FATAL_CODE_BLOCK(10),
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QORIQ_FATAL_FDT_NO_BUS_FREQUENCY,
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QORIQ_FATAL_FDT_NO_CLOCK_FREQUENCY,
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QORIQ_FATAL_FDT_NO_TIMEBASE_FREQUENCY,
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QORIQ_FATAL_RESTART_FAILED,
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QORIQ_FATAL_RESTART_INSTALL_INTERRUPT,
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QORIQ_FATAL_RESTART_INTERRUPT_FAILED,
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/* ATSAM fatal codes */
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ATSAM_FATAL_XDMA_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(11),
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ATSAM_FATAL_PIO_IRQ_A,
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ATSAM_FATAL_PIO_IRQ_B,
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ATSAM_FATAL_PIO_IRQ_C,
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ATSAM_FATAL_PIO_IRQ_D,
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ATSAM_FATAL_PIO_IRQ_E,
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ATSAM_FATAL_PIO_CONFIGURE_IT,
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/* i.MX fatal codes */
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IMX_FATAL_GENERIC_TIMER_FREQUENCY = BSP_FATAL_CODE_BLOCK(12),
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IMX_FATAL_GPIO_UNEXPECTED_FDT,
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/* RISC-V fatal codes */
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RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE = BSP_FATAL_CODE_BLOCK(13),
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RISCV_FATAL_NO_NS16550_REG_IN_DEVICE_TREE,
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RISCV_FATAL_NO_NS16550_CLOCK_FREQUENCY_IN_DEVICE_TREE,
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RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION,
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RISCV_FATAL_CLOCK_IRQ_INSTALL,
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RISCV_FATAL_NO_CLINT_REG_IN_DEVICE_TREE,
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RISCV_FATAL_INVALID_HART_REG_IN_DEVICE_TREE,
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RISCV_FATAL_INVALID_CLINT_IRQS_EXTENDED_IN_DEVICE_TREE,
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RISCV_FATAL_NO_PLIC_REG_IN_DEVICE_TREE,
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RISCV_FATAL_INVALID_PLIC_NDEV_IN_DEVICE_TREE,
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RISCV_FATAL_TOO_LARGE_PLIC_NDEV_IN_DEVICE_TREE,
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RISCV_FATAL_INVALID_INTERRUPT_AFFINITY,
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RISCV_FATAL_NO_NS16550_INTERRUPTS_IN_DEVICE_TREE,
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RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE,
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RISCV_FATAL_CLOCK_SMP_INIT,
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/* GRLIB fatal codes */
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GRLIB_FATAL_CLOCK_NO_IRQMP_TIMESTAMP_SUPPORT = BSP_FATAL_CODE_BLOCK(14),
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/* i.MXRT fatal codes */
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IMXRT_FATAL_NO_CONSOLE = BSP_FATAL_CODE_BLOCK(15),
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IMXRT_FATAL_LPUART_INVALID_FDT,
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IMXRT_FATAL_LPUART_ALLOC_FAILED,
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IMXRT_FATAL_LPUART_INSTALL_FAILED,
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IMXRT_FATAL_LPSPI_INVALID_FDT,
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IMXRT_FATAL_LPSPI_ALLOC_FAILED,
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IMXRT_FATAL_LPSPI_HW_INIT_FAILED,
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IMXRT_FATAL_LPSPI_REGISTER_FAILED,
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IMXRT_FATAL_LPI2C_INVALID_FDT,
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IMXRT_FATAL_LPI2C_ALLOC_FAILED,
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IMXRT_FATAL_LPI2C_HW_INIT_FAILED,
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IMXRT_FATAL_LPI2C_REGISTER_FAILED,
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IMXRT_FATAL_LPI2C_UNSUPPORTED_HARDWARE,
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/* MicroBlaze fatal codes */
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MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(16),
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} bsp_fatal_code;
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RTEMS_NO_RETURN static inline void
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bsp_fatal( bsp_fatal_code code )
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{
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rtems_fatal( RTEMS_FATAL_SOURCE_BSP, (rtems_fatal_code) code );
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}
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/** @} */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_SHARED_BSP_FATAL_H */
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