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26,350 Commits 7 Branches 54 Tags
f412e126d04ab8fb030e3ee3d430c7e132950e5c
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Author SHA1 Message Date
Joel Sherrill
f412e126d0 mcf52235/configure.ac: Delete junk line 2014-04-24 08:21:00 -05:00
Chris Johns
b74c9cfb76 bootstrap: Sort the contents of the prinstall.am files. 
Sorting removed the variations across different host operating systems
and file systems.
 2014-04-23 14:32:34 +10:00
Joel Sherrill
1450de0d7e shsim: Correct linking for C++ 2014-04-22 15:12:11 -05:00
Joel Sherrill
25c3208aef gensh4: Correct linking for C++ 2014-04-22 15:12:11 -05:00
Joel Sherrill
851e64321b gensh2: Correct linking for C++ 2014-04-22 15:12:11 -05:00
Joel Sherrill
3191b42681 gensh1: Correct linking for C++ 2014-04-22 15:12:11 -05:00
Joel Sherrill
b6a2e57ba9 score603e: Add rtems_crti 2014-04-22 15:12:11 -05:00
Joel Sherrill
77737ad104 ss555: Add rtems_crti/n 2014-04-22 15:12:10 -05:00
Joel Sherrill
812c9d68c3 sim68000/bsp_specs: Add crtbegin/end, crt[in] 2014-04-22 15:12:09 -05:00
Joel Sherrill
2f36f5a500 mpc8260ads: Add rtems_crti/n 2014-04-22 15:12:07 -05:00
Joel Sherrill
8c18adde1a h8sim/bsp_specs: Add crtbegin/end, crt[in] 2014-04-22 09:45:55 -05:00
Joel Sherrill
1ed8762ed6 mpci.c: Now compiles again 2014-04-22 08:37:03 -05:00
Joel Sherrill
d47904f3e1 niagara/Makefile.am: Fix rule for start.o 2014-04-22 08:37:03 -05:00
Joel Sherrill
a44fa5a7ce utf8proc01: Honor BSP_SMALL_MEMORY 2014-04-22 08:37:02 -05:00
Joel Sherrill
faa4e4c08d flashdisk01: Honor BSP_SMALL_MEMORY 2014-04-22 08:37:02 -05:00
Joel Sherrill
2bea49479a fsdosfsname01: Honor BSP_SMALL_MEMORY 2014-04-22 08:37:02 -05:00
Joel Sherrill
97ae79d762 fsdosfsformat01: Honor BSP_SMALL_MEMORY 2014-04-22 08:37:02 -05:00
Joel Sherrill
90bc4d03f0 libcpu/sh: Build cache stubs so apps usign cache API link 2014-04-22 08:37:01 -05:00
Joel Sherrill
614fefecf8 dummy_printk_support.c: Comment clean up 2014-04-22 08:37:01 -05:00
Joel Sherrill
a531683ae9 shsim: Add printk() support and move all code to console subdirectory 2014-04-22 08:37:01 -05:00
Sebastian Huber
d60e760e80 bsps: Fix TLS support in linker command files 
The TLS section symbols had wrong values in case of an empty TLS data
section and a nonempty TLS BSS section.
 2014-04-22 09:51:17 +02:00
Sebastian Huber
e2782684f2 bsp/mbx8xx: Fix Makefile.am and bsp_specs 2014-04-22 09:36:48 +02:00
Sebastian Huber
e10574a4c2 bsps/powerpc: Fix linker command files 2014-04-22 08:34:46 +02:00
Sebastian Huber
3380ee8194 score: Use common names for per-CPU variables 
Use "cpu" for an arbitrary Per_CPU_Control variable.

Use "cpu_self" for the Per_CPU_Control of the current processor.

Use "cpu_index" for an arbitrary processor index.

Use "cpu_index_self" for the processor index of the current processor.

Use "cpu_count" for the processor count obtained via
_SMP_Get_processor_count().

Use "cpu_max" for the processor maximum obtained by
rtems_configuration_get_maximum_processors().
 2014-04-22 08:34:45 +02:00
Sebastian Huber
f17e171687 score: Fix warning 2014-04-22 08:34:45 +02:00
Sebastian Huber
861346d18e score: Delete superfluous assignments 
These values are already zero initialized by C run-time setup.
 2014-04-22 08:34:45 +02:00
Sebastian Huber
4c23fa4b7d score: Simplify Giant lock 2014-04-22 08:34:45 +02:00
Sebastian Huber
774edf2c9b score: Use _Per_CPU_Get_snapshot() 2014-04-22 08:34:45 +02:00
Sebastian Huber
fab2f1885c doc: Setting Affinity to a Single Processor 2014-04-22 08:34:45 +02:00
Ralf Kirchner
d98eea06dc bsp/arm: Cleanup L2 cache handling 2014-04-17 13:25:12 +02:00
Ralf Kirchner
127634c358 bsp/arm: Correct L2 cache enable method 2014-04-17 13:25:12 +02:00
Ralf Kirchner
62fa1ea25e bsp/arm: Add cache size methods 
Add new methods which deliver the cache sizes of for supported cache levels.
 2014-04-17 13:25:12 +02:00
Ralf Kirchner
1c62f74d22 bsp/arm: Add L2 cache locking 
This level 2 cache is a shared data and instruction cache and thus needs locking.
 2014-04-17 13:25:12 +02:00
Ralf Kirchner
bebcfa57a8 bsp/arm: Remove unused cache store methods 2014-04-17 13:25:12 +02:00
Ralf Kirchner
db5a84d0ad bsp/arm: Correct cache misalignment handling 
Correct misalignment handling and prepare for locking.
 2014-04-17 13:25:11 +02:00
Ralf Kirchner
92e2757b0b bsp/arm: Correct L2 cache flushing 
Correct misalignment handling and prepare for locking.
 2014-04-17 13:25:11 +02:00
Ralf Kirchner
cbd9e634ee bsp/arm: Remove arm erratum 764369 from L2 cache 
Arm erratum 764369 only applies to the level 1 cache.
 2014-04-17 13:25:11 +02:00
Ralf Kirchner
9ee2ec56b5 bsp/arm: Consistenly same handling for flushing 
It is importeant to consistently apply the same handling for flushing within
level 2 and level 1 cache handling. In this case now both handling use clean and invalidate.
 2014-04-17 13:25:11 +02:00
Ralf Kirchner
e331e69a47 bsp/arm: RTEMS_SMP to arm erratum 764369 detection 
Move the RTEMS_SMP conditional compilation to the detection method of arm erratum 764369
 2014-04-17 13:25:11 +02:00
Ralf Kirchner
707b617294 bsp/arm: Erratum 764369 after enabling SCU 
Execute the SCU part of the workaround of arm erratum 764368 after the SCU was enabled.
 2014-04-17 13:25:11 +02:00
Ralf Kirchner
d9e7d1e414 bsp/arm: Correct detection of arm erratum 764368 2014-04-17 13:25:10 +02:00
Ralf Kirchner
924b47a548 bsp/arm: Cleanup L1 cache 2014-04-17 13:25:10 +02:00
Ralf Kirchner
a38d4a37bc libchip: Correct error handling in dwmac driver 
By fault an rtems_status_code has been expected instead of an errno error number.
 2014-04-17 13:24:08 +02:00
Ralf Kirchner
1613a01bb0 libchip: Reduce tx interrupts 
Reduce number of packet transmitted interrupts by using the interrupt mechanism only
if we run out of DMA descriptors.
Under normal conditions regaining DMA descriptors, mbufs and clusters is handled
via a counter.
 2014-04-17 13:24:07 +02:00
Ralf Kirchner
f28b8d4595 libchip: Cleanup 2014-04-17 13:24:07 +02:00
Ralf Kirchner
18fe64a2ca libchip: Improve handling of DMA suspends 
Reset the corresponding DMA status bit
 2014-04-17 13:24:07 +02:00
Ralf Kirchner
6ac39691a2 bsp/altera-cyclone-v: Cleanup 2014-04-17 13:24:07 +02:00
Ralf Kirchner
782182eba4 bsp/altera-cyclone-v: Change console baud rate 
The baud rate of the altera cyclone-V U-Boot can not be changed at the
u-Boot console prompt. Thus we use the same baud rate as the U-Boot for
the BSP.
 2014-04-17 13:24:07 +02:00
Sebastian Huber
320faf8e68 score: Clarify TLS support 2014-04-17 08:06:40 +02:00
Sebastian Huber
10e613ba52 doc: Typo 2014-04-17 08:06:39 +02:00