The clock from the ARM timer is derived from the system clock. This clock can
change dynamically e.g. if the system goes into reduced power or in low power
mode. Thus the clock speed adapts to the overall system performance
capabilities. For accurate timing it is recommended to use the system timers.
if BSP_CLOCK_USE_SYSTEMTIMER = 1, use the System Timer, otherwise use the ARM
Timer.
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
Make the clock driver parameters configurable. Use the maximum counter
frequency to get the best time resolution. Decouple the CPU counter from the
timecounter. Make the tick catch up handling more robust. Add a validation
test for the tick catch up.
Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
Make the initialization and polled functions independent of the Termios
context. This helps to implement the kernel I/O support without a dependency
on the Termios framework.
Move declarations of bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the
<bsp/irq.h> includes.
Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
needed (usually RTEMS_SMP).
Provide stub implementations for i386 to fix build errors.
The parameters are unused due to API constraints. The functions are
used through function pointers. Alternative implementations may use the
parameters.
Update #4862.
Pass the parameter of the clock interrupt handler to
Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes
it possible to use the interrupt handler argument in clock drivers.
Use the interrupt handler provided by Clock_driver_support_install_isr() to
avoid local delarations of Clock_isr().
Update #4862.
We observed a strange behavior of the 1Hz timer when running cFS on Zynq
RPU. After some investigation, we reduced the error to the truncation
issue. This patch fixes the issue.
When resetting the QSPI FIFOs, the driver was reading write-only bits of
a register for status information when it was actually in a different
register. This corrects the driver so that it reads the correct status
bits.
Add an opportunistic page cache to the xnandpsu driver since it does not
implement partial page reads and common filesystem access patterns
perform multiple reads from the same page. This has been seen to provide
a 10x speedup to read speeds and a 2x speedup on first initialization
when used with JFFS2.
This fixes a logic inversion that was preventing creation of a Bad Block
Table (BBT) from scratch on devices that lack one. This was discovered
during upstream integration testing. The BBT management layer in this
driver is not designed to be easily testable other than on real hardware.
Stacked mode doubles the number of sectors and device size while
parallel mode doubles the sector size and the device size. Make sure
that this is accounted for in the device size accessor.
`tms570_sci_interrupt_handler()` is called when an RX interrupt fires. It checks
in the register `FLR`, the `RXRDY` bit (Receiver ready flag - indicate that the
SCIRD contains new data). If it is set, it calls
`tms570_sci_read_received_chars()`.
`tms570_sci_read_received_chars()` checks the register `RD` against 0. If it is
non zero, it returns 1 to indicate that one byte was read.
In the old behavior, if it is zero, the function returns 0 to indicate that no
data was read.
The new behavior is to not silently drop 0x00 bytes. Ignoring 0x00 bytes is fine
when working with printable text (which, I assume, is how this driver was
tested), but as soon as the UART is used in non canonical (raw) mode, with
potentially 0x00 bytes, these bytes will be silently dropped, causing issues in
the data/protocol layer above.
Update #4982.
This enables the VME support for the MVME2500. Note that the PCIe
support from libbsd is used. So you need the related libbsd patches for
this to work.
If the drivers in libbsd are not enabled, the linker should not pick up
anything from this patch.
Add a function that allows to set the polarity (active-low / negative
edge triggered or active-high / positive edge triggered) and sense
(level or edge sensitive) of the external interrupts.
