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bsps/arm: Improve GICv3 support

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In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.

Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
This commit is contained in:
Sebastian Huber
2024-04-16 10:20:48 +02:00
committed by Amar Takhar
parent 901e893087
commit 76462bb64c
1 changed files with 11 additions and 5 deletions
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16
bsps/shared/dev/irq/arm-gicv3.c
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@@ -42,12 +42,18 @@
void bsp_interrupt_dispatch(void)
{
uint32_t icciar = READ_SR(ICC_IAR1);
rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
rtems_vector_number spurious = 1023;
while (true) {
uint32_t icciar = READ_SR(ICC_IAR1);
rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);
uint32_t status;
if (vector != spurious) {
arm_interrupt_handler_dispatch(vector);
if (!bsp_interrupt_is_valid_vector(vector)) {
break;
}
status = arm_interrupt_enable_interrupts();
bsp_interrupt_handler_dispatch_unchecked(vector);
arm_interrupt_restore_interrupts(status);
WRITE_SR(ICC_EOIR1, icciar);
}