Add support for the BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY build option
for the GICv2 support. This option is useful for multiprocessor systems
without SMP support.
- Refactor the pl011 driver to be extensible.
- Add IRQ support and baudrate configuration support for pl011 driver.
- Modify related BSP.
- Add doxygen comments for arm-pl011.
Close#5026
Co-authored-by: Ning Yang <yangn0@qq.com>
It is not clear why this is necessary. For example, the
zynq_uart_initialize() does not issue the '\r' before waiting for an
inactive transmission state.
Similar to the recent commit in tms570-sci.c, the assumption that a UART will
only see printable ASCII characters, instead of any value in the range
0x00-0xFF, is wrong.
A non forgiving binary protocol will be thrown off by this driver sending
"\r\r\r\r" when initializing.
If a user wants to flush the interface, they should explicitely use the
dedicated function `tcflush(fd, TCIOFLUSH);`.
Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM
GIC support. Enable this option for arm/altera-cyclone-v and
arm/xilinx-zynq BSPs by default.
The EOZ9 RTC has a similar register interface like the MCP7940M (and
quite some other I2C RTCs). This commit:
* Extracts the generic parts from MCP7940M and moves it into a generic
i2c-rtc driver.
* Uses the new i2c-rtc for the MCP7940M.
* Uses the new i2c-rtc for the new Abracom EOZ9.
This switches the XQspiPsu NOR driver layer to use the RTEMS event
system so that waits for interrupt-based data transfers can time out
instead of waiting indefinitely. It is sometimes possible for either the
controller or the NOR chip to fail to issue a transfer completion event
and recovery is preferable to a hang.
Add directives to get and set the priority of an interrupt vector.
Implement the directives for the following BSP families:
* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq
Implement the directives for the following interrupt controllers:
* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)
Update #5002.
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
Make the clock driver parameters configurable. Use the maximum counter
frequency to get the best time resolution. Decouple the CPU counter from the
timecounter. Make the tick catch up handling more robust. Add a validation
test for the tick catch up.
Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
Make the initialization and polled functions independent of the Termios
context. This helps to implement the kernel I/O support without a dependency
on the Termios framework.
Move declarations of bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the
<bsp/irq.h> includes.
Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
needed (usually RTEMS_SMP).
Provide stub implementations for i386 to fix build errors.
Pass the parameter of the clock interrupt handler to
Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes
it possible to use the interrupt handler argument in clock drivers.
Use the interrupt handler provided by Clock_driver_support_install_isr() to
avoid local delarations of Clock_isr().
Update #4862.
We observed a strange behavior of the 1Hz timer when running cFS on Zynq
RPU. After some investigation, we reduced the error to the truncation
issue. This patch fixes the issue.
When resetting the QSPI FIFOs, the driver was reading write-only bits of
a register for status information when it was actually in a different
register. This corrects the driver so that it reads the correct status
bits.
Add an opportunistic page cache to the xnandpsu driver since it does not
implement partial page reads and common filesystem access patterns
perform multiple reads from the same page. This has been seen to provide
a 10x speedup to read speeds and a 2x speedup on first initialization
when used with JFFS2.
This fixes a logic inversion that was preventing creation of a Bad Block
Table (BBT) from scratch on devices that lack one. This was discovered
during upstream integration testing. The BBT management layer in this
driver is not designed to be easily testable other than on real hardware.
Stacked mode doubles the number of sectors and device size while
parallel mode doubles the sector size and the device size. Make sure
that this is accounted for in the device size accessor.
This cleans up outputUsesInterrupts usage with rtems_termios_device_mode
enum values. The outputUsesInterrupts member was typed as an int, named
as if it were a boolean value, and used as if it were a
rtems_termios_device_mode enum. In this patch, values assigned to
outputUsesInterrupts have been converted to the corresponding
rtems_termios_device_mode enum value, conversions from
deviceOutputUsesInterrupts have been made explicit, and uses of
rtems_termios_device_mode enum values with deviceOutputUsesInterrupts
have been converted to booleans.
