* new-exceptions/bspsupport/irq.c: don't disable irqs
at the interrupt controller (PIC) during initialization -- this
caused problems where some BSPs's BSP_disable_irq_at_pic() routine
did not ignore IRQ lines associated with cascaded PICs.
Rely on the BSP (BSP_setup_the_pic()) to provide a good
initial setup.
* new-exceptions/bspsupport/ppc_exc_asm_macros.h,
new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/README,
new-exceptions/bspsupport/ppc_exc_hdl.c:
Thomas Doerfler clarified (thanks!) that raising an
exception and executing the 1st instruction is not
an atomical operation. I added a fix to the code that
checks if a lower-priority interrupt is under way:
we now not only test if the 'lock' variable was set
but also check if the interrupted PC points to the
'write lock' instruction.
Added more comments and updated README.
* Makefile.am, new-exceptions/bspsupport/README:
provide new irq_bspsupport.rel which was
split out of exc_bspsupport.rel to provide finer-grained
control over what BSPs want to use.
* new-exceptions/e500_raw_exc_init.c: map DEC
exception to ASM_BOOKE_DEC_VECTOR instead of ASM_DEC_VECTOR.
Fixed wrong mapping of ASM_BOOKE_FIT_VECTOR
(was ASM_BOOKE_PIT_VECTOR).
* new-exceptions/raw_exception.c, new_exceptions/raw_exception.h,
new_exceptions/bspsupport/irq.c: renamed ASM_BOOKE_PIT_VECTOR
to ASM_BOOKE_DEC_VECTOR to be closer to 'official'
nomenclature.
* new-exceptions/bspsupport/ppc_exc_hdl.c: make sure
RI is set in the exception frame and panic if it isn't
(state info might have been lost). This only affects
classic PPC.
* new-exceptions/bspsupport/README,
new-exceptions/bspsupport/ppc_exc_bspsupp.h
new-exceptions/bspsupport/vectors_init.c:
added crude test to make sure MMU maps memory as
write-back enabled.
* new-exceptions/bspsupport/ppc_exc_test.c,
new-exceptions/bspsupport/vectors_init.c,
new-exceptions/bspsupport/ppc_exc_bspsupp.h,
new-exceptions/bspsupport/README,
new-exceptions/bspsupport/irq_supp.h:
Added README and some comments; now use TRAP exception
in ppc_exc_test.c so that it works on PSIM.
* new-exceptions/bspsupport/, new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/ppc_exc_test.c,
new-exceptions/bspsupport/vectors.h,
new-exceptions/bspsupport/vectors_init.c,
new-exceptions/bspsupport/irq.c,
new-exceptions/bspsupport/ppc_exc_bspsupp.h,
new-exceptions/bspsupport/ppc_exc_hdl.c,
new-exceptions/bspsupport/ppc_exc_asm_macros.h,
new-exceptions/bspsupport/nested_irq_test.c:
New files. Added 'middleware' code for helping BSPs implement
exception and interrupt handling and implementing the 'new'
RTEMS IRQ API (which I personally dislike).
* new-exceptions/e500_raw_exc_init.c, new-exceptions/raw_exception.c,
shared/include/cpuIdent.c, shared/include/cpuIdent.h:
Added different kinds of 'bookE' to the ppc_cpu_is_bookE feature
check; unfortunately...
* new-exceptions/raw_exception.c, new-exceptions/raw_exception.h:
Removed all #ifdef <cpu_flavor>. All exception vectors are now
always defined.
Changed implementation of <cpu>_vector_is_valid() from 'case'
statements to table lookup.
Replaced 'ASM_VECTORS_CRITICAL' by a variable
'bsp_raw_vector_is_405_critical' which is set at run-time.
Removed PPC_MSR_EXC_BITS. The exception handling code
(libbsp/shared/vectors/vectors.S and ../irq/irq_asm.S) now
has a run-time check for these bits.
Both files are now free of #if <cpu_flavor> constructs.
* Makefile.am, configure.ac, preinstall.am,
new-exceptions/e500_raw_exc_init.c: Started adding
support for e500 CPU. Most stuff is borrowed from mpc6xx.
* new-exceptions/raw_exception.c, new-exceptions/raw_exception.h:
Qualified all exception vector symbols that are only defined
#ifdef <cpu_flavor> with <cpu_flavor> in the symbol name.
If the special flavor __ppc_generic is effective the ALL
vector symbols are available and ppc_vector_is_valid() works
for all supported CPUs (run-time check).
This is work towards a #ifdef <cpu_flavor> free libcpu and
exception framework.
* mpc5xx/console-generic/console-generic.c, mpc8260/timer/timer.c,
new-exceptions/cpu.c, old-exceptions/cpu.c: Move interrupt_stack_size
field from CPU Table to Configuration Table. Eliminate CPU Table from
all ports. Delete references to CPU Table in all forms.
* new-exceptions/raw_exception.c, new-exceptions/raw_exception.h,
old-exception/cpu.c: define bsp_exceptions_in_RAM variable.
This is probably only used by the simulator (were else
can you install something to ROM ??).
* mpc5xx/clock/clock.c, mpc5xx/timer/timer.c, mpc8260/clock/clock.c,
mpc8260/cpm/brg.c, mpc8260/timer/timer.c, mpc8xx/clock/clock.c,
mpc8xx/console-generic/console-generic.c, mpc8xx/timer/timer.c,
new-exceptions/raw_exception.c, old-exceptions/cpu.c,
ppc403/clock/clock.c, ppc403/console/console.c,
ppc403/console/console.c.polled, ppc403/console/console405.c,
ppc403/ictrl/ictrl.c, ppc403/irq/ictrl.c, ppc403/timer/timer.c,
ppc403/tty_drv/tty_drv.c: Eliminate PowerPC specific elements from
the CPU Table. They have been replaced with variables named bsp_XXX
as needed.
* mpc5xx/irq/irq.c, mpc5xx/exceptions/raw_exception.c,
new-exceptions/raw_exception.c: test for non-NULL-ness before calling
'on'/'off' methods so that users don't have to provide
no-ops if they don't want this feature.
PR 1257/bsps
* mpc5xx/exceptions/raw_exception.c, mpc5xx/irq/irq.c,
mpc6xx/exceptions/raw_exception.c,
mpc8260/exceptions/raw_exception.c,
mpc8xx/exceptions/raw_exception.c, new-exceptions/raw_exception.c,
ppc403/ictrl/ictrl.c, ppc403/irq/ictrl.c: Code outside of cpukit
should use the public API for
rtems_interrupt_disable/rtems_interrupt_enable. By bypassing the
public API and directly accessing _CPU_ISR_Disable and
_CPU_ISR_Enable, they were bypassing the compiler memory barrier
directive which could lead to problems. This patch also changes the
type of the variable passed into these routines and addresses minor
style issues.
* new-exceptions/cpu_asm.S: the book says a context
synchronizing instruction (isync) is necessary after flipping
certain bits (e.g, MSR_FP) in msr -- since this could happen as
part of a context switch I added 'isync'.
