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2007-12-05 Till Straumann <strauman@slac.stanford.edu>

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* new-exceptions/raw_exception.c, new-exceptions/raw_exception.h:
	Qualified all exception vector symbols that are only defined
	#ifdef <cpu_flavor> with <cpu_flavor> in the symbol name.
	If the special flavor __ppc_generic is effective the ALL
	vector symbols are available and ppc_vector_is_valid() works
	for all supported CPUs (run-time check).
	This is work towards a #ifdef <cpu_flavor> free libcpu and
	exception framework.
This commit is contained in:
Till Straumann
2007-12-05 08:33:11 +00:00
parent 1051054f84
commit 7df69c3716
3 changed files with 323 additions and 175 deletions
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11
c/src/lib/libcpu/powerpc/ChangeLog
View File

@@ -1,3 +1,14 @@
2007-12-05 Till Straumann <strauman@slac.stanford.edu>
* new-exceptions/raw_exception.c, new-exceptions/raw_exception.h:
Qualified all exception vector symbols that are only defined
#ifdef <cpu_flavor> with <cpu_flavor> in the symbol name.
If the special flavor __ppc_generic is effective the ALL
vector symbols are available and ppc_vector_is_valid() works
for all supported CPUs (run-time check).
This is work towards a #ifdef <cpu_flavor> free libcpu and
exception framework.
2007-12-04 Joel Sherrill <joel.sherrill@OARcorp.com>
* mpc5xx/console-generic/console-generic.c, mpc8260/timer/timer.c,

297
c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.c
View File

@@ -24,6 +24,7 @@
*
* $Id$
*/
#include <rtems.h>
#include <rtems/system.h>
#include <rtems/score/powerpc.h>
#include <rtems/score/isr.h>
@@ -33,6 +34,10 @@
#include <string.h>
#ifdef __ppc_generic
#define PPC_HAS_60X_VECTORS
#endif
static rtems_raw_except_connect_data* raw_except_table;
static rtems_raw_except_connect_data default_raw_except_entry;
static rtems_raw_except_global_settings* local_settings;
@@ -41,10 +46,11 @@ void * codemove(void *, const void *, unsigned int, unsigned long);
boolean bsp_exceptions_in_RAM = TRUE;
static void* ppc_get_vector_addr(rtems_vector vector)
void* ppc_get_vector_addr(rtems_vector vector)
{
unsigned vaddr;
extern boolean bsp_exceptions_in_RAM;
vaddr = ((unsigned)vector) << 8;
switch(vector) {
/*
@@ -52,29 +58,34 @@ static void* ppc_get_vector_addr(rtems_vector vector)
* on some CPU derivates. this construct will handle them
* if available
*/
#if defined(PPC_HAS_60X_VECTORS)
/* Special case; altivec unavailable doesn't fit :-( */
case ASM_VEC_VECTOR:
vaddr = ASM_VEC_VECTOR_OFFSET;
case ASM_60X_VEC_VECTOR:
#ifndef ASM_60X_VEC_VECTOR_OFFSET
#define ASM_60X_VEC_VECTOR_OFFSET 0xf20
#endif
if ( ppc_cpu_has_altivec() )
vaddr = ASM_60X_VEC_VECTOR_OFFSET;
break;
#if defined(ASM_BOOKE_FIT_VECTOR)
case ASM_BOOKE_FIT_VECTOR:
#ifndef ASM_BOOKE_FIT_VECTOR_OFFSET
#define ASM_BOOKE_FIT_VECTOR_OFFSET 0x1010
#endif
if ( PPC_405 == current_ppc_cpu )
vaddr = ASM_BOOKE_FIT_VECTOR_OFFSET;
break;
#endif
#if defined(ASM_PIT_VECTOR)
case ASM_PIT_VECTOR:
vaddr = ASM_PIT_VECTOR_OFFSET;
break;
#if defined(ASM_BOOKE_WDOG_VECTOR)
case ASM_BOOKE_WDOG_VECTOR:
#ifndef ASM_BOOKE_WDOG_VECTOR_OFFSET
#define ASM_BOOKE_WDOG_VECTOR_OFFSET 0x1020
#endif
#if defined(ASM_FIT_VECTOR)
case ASM_FIT_VECTOR:
vaddr = ASM_FIT_VECTOR_OFFSET;
break;
#endif
#if defined(ASM_WDOG_VECTOR)
case ASM_WDOG_VECTOR:
vaddr = ASM_WDOG_VECTOR_OFFSET;
if ( PPC_405 == current_ppc_cpu )
vaddr = ASM_BOOKE_WDOG_VECTOR_OFFSET;
break;
#endif
default:
vaddr = ((unsigned)vector) << 8;
break;
}
if ( bsp_exceptions_in_RAM )
@@ -84,7 +95,7 @@ static void* ppc_get_vector_addr(rtems_vector vector)
}
#if ( defined(mpc860) || defined(mpc821) )
#if ( defined(mpc860) || defined(mpc821) || defined(__ppc_generic) )
int mpc860_vector_is_valid(rtems_vector vector)
{
@@ -101,25 +112,25 @@ int mpc860_vector_is_valid(rtems_vector vector)
case ASM_SYS_VECTOR:
case ASM_TRACE_VECTOR:
case ASM_FLOATASSIST_VECTOR:
case ASM_8XX_FLOATASSIST_VECTOR:
case ASM_SOFTEMUL_VECTOR:
case ASM_ITLBMISS_VECTOR:
case ASM_DTLBMISS_VECTOR:
case ASM_ITLBERROR_VECTOR:
case ASM_DTLBERROR_VECTOR:
case ASM_8XX_SOFTEMUL_VECTOR:
case ASM_8XX_ITLBMISS_VECTOR:
case ASM_8XX_DTLBMISS_VECTOR:
case ASM_8XX_ITLBERROR_VECTOR:
case ASM_8XX_DTLBERROR_VECTOR:
case ASM_DBREAK_VECTOR:
case ASM_IBREAK_VECTOR:
case ASM_PERIFBREAK_VECTOR:
case ASM_DEVPORT_VECTOR:
case ASM_8XX_DBREAK_VECTOR:
case ASM_8XX_IBREAK_VECTOR:
case ASM_8XX_PERIFBREAK_VECTOR:
case ASM_8XX_DEVPORT_VECTOR:
return 1;
default: return 0;
}
}
#endif
#if (defined(mpc555) || defined(mpc505))
#if (defined(mpc555) || defined(mpc505) || defined(__ppc_generic))
int mpc5xx_vector_is_valid(rtems_vector vector)
{
@@ -137,17 +148,17 @@ int mpc5xx_vector_is_valid(rtems_vector vector)
case ASM_SYS_VECTOR:
case ASM_TRACE_VECTOR:
case ASM_FLOATASSIST_VECTOR:
case ASM_5XX_FLOATASSIST_VECTOR:
case ASM_SOFTEMUL_VECTOR:
case ASM_5XX_SOFTEMUL_VECTOR:
case ASM_IPROT_VECTOR:
case ASM_DPROT_VECTOR:
case ASM_5XX_IPROT_VECTOR:
case ASM_5XX_DPROT_VECTOR:
case ASM_DBREAK_VECTOR:
case ASM_IBREAK_VECTOR:
case ASM_MEBREAK_VECTOR:
case ASM_NMEBREAK_VECTOR:
case ASM_5XX_DBREAK_VECTOR:
case ASM_5XX_IBREAK_VECTOR:
case ASM_5XX_MEBREAK_VECTOR:
case ASM_5XX_NMEBREAK_VECTOR:
return 1;
default:
return 0;
@@ -160,7 +171,7 @@ int mpc5xx_vector_is_valid(rtems_vector vector)
}
#endif
#if defined(ppc405)
#if ( defined(ppc405) || defined(__ppc_generic) )
int ppc405_vector_is_valid(rtems_vector vector)
{
@@ -173,9 +184,9 @@ int ppc405_vector_is_valid(rtems_vector vector)
case ASM_ALIGN_VECTOR:
case ASM_PROG_VECTOR:
case ASM_SYS_VECTOR:
case ASM_PIT_VECTOR:
case ASM_ITLBMISS_VECTOR:
case ASM_DTLBMISS_VECTOR:
case ASM_BOOKE_PIT_VECTOR:
case ASM_BOOKE_ITLBMISS_VECTOR:
case ASM_BOOKE_DTLBMISS_VECTOR:
return 1;
default: return 0;
}
@@ -186,13 +197,15 @@ int ppc405_vector_is_valid(rtems_vector vector)
int altivec_vector_is_valid(rtems_vector vector)
{
switch(vector) {
case ASM_VEC_VECTOR:
case ASM_VEC_ASSIST_VECTOR:
return 1;
default:
break;
}
if ( ppc_cpu_has_altivec() ) {
switch(vector) {
case ASM_60X_VEC_VECTOR:
case ASM_60X_VEC_ASSIST_VECTOR:
return 1;
default:
break;
}
}
return 0;
}
@@ -211,9 +224,9 @@ int mpc750_vector_is_valid(rtems_vector vector)
case ASM_DEC_VECTOR:
case ASM_SYS_VECTOR:
case ASM_TRACE_VECTOR:
case ASM_ADDR_VECTOR:
case ASM_SYSMGMT_VECTOR:
case ASM_ITM_VECTOR:
case ASM_60X_ADDR_VECTOR:
case ASM_60X_SYSMGMT_VECTOR:
case ASM_60X_ITM_VECTOR:
return 1;
default: return 0;
}
@@ -236,15 +249,15 @@ int PSIM_vector_is_valid(rtems_vector vector)
return 0;
case ASM_TRACE_VECTOR:
return 1;
case ASM_PERFMON_VECTOR:
case ASM_60X_PERFMON_VECTOR:
return 0;
case ASM_IMISS_VECTOR: /* fall through */
case ASM_DLMISS_VECTOR:
case ASM_DSMISS_VECTOR:
case ASM_ADDR_VECTOR:
case ASM_SYSMGMT_VECTOR:
case ASM_60X_IMISS_VECTOR: /* fall through */
case ASM_60X_DLMISS_VECTOR:
case ASM_60X_DSMISS_VECTOR:
case ASM_60X_ADDR_VECTOR:
case ASM_60X_SYSMGMT_VECTOR:
return 1;
case ASM_ITM_VECTOR:
case ASM_60X_ITM_VECTOR:
return 0;
}
return 0;
@@ -265,15 +278,15 @@ int mpc603_vector_is_valid(rtems_vector vector)
case ASM_SYS_VECTOR:
case ASM_TRACE_VECTOR:
return 1;
case ASM_PERFMON_VECTOR:
case ASM_60X_PERFMON_VECTOR:
return 0;
case ASM_IMISS_VECTOR: /* fall through */
case ASM_DLMISS_VECTOR:
case ASM_DSMISS_VECTOR:
case ASM_ADDR_VECTOR:
case ASM_SYSMGMT_VECTOR:
case ASM_60X_IMISS_VECTOR: /* fall through */
case ASM_60X_DLMISS_VECTOR:
case ASM_60X_DSMISS_VECTOR:
case ASM_60X_ADDR_VECTOR:
case ASM_60X_SYSMGMT_VECTOR:
return 1;
case ASM_ITM_VECTOR:
case ASM_60X_ITM_VECTOR:
return 0;
}
return 0;
@@ -293,21 +306,52 @@ int mpc604_vector_is_valid(rtems_vector vector)
case ASM_DEC_VECTOR:
case ASM_SYS_VECTOR:
case ASM_TRACE_VECTOR:
case ASM_PERFMON_VECTOR:
case ASM_60X_PERFMON_VECTOR:
return 1;
case ASM_IMISS_VECTOR: /* fall through */
case ASM_DLMISS_VECTOR:
case ASM_DSMISS_VECTOR:
case ASM_60X_IMISS_VECTOR: /* fall through */
case ASM_60X_DLMISS_VECTOR:
case ASM_60X_DSMISS_VECTOR:
return 0;
case ASM_ADDR_VECTOR: /* fall through */
case ASM_SYSMGMT_VECTOR:
case ASM_60X_ADDR_VECTOR: /* fall through */
case ASM_60X_SYSMGMT_VECTOR:
return 1;
case ASM_ITM_VECTOR:
case ASM_60X_ITM_VECTOR:
return 0;
}
return 0;
}
int e500_vector_is_valid(rtems_vector vector)
{
switch (vector) {
case ASM_RESET_VECTOR:
case ASM_MACH_VECTOR:
case ASM_PROT_VECTOR:
case ASM_ISI_VECTOR:
case ASM_EXT_VECTOR:
case ASM_ALIGN_VECTOR:
case ASM_PROG_VECTOR:
case ASM_FLOAT_VECTOR:
case ASM_SYS_VECTOR:
case /* APU unavailable */ 0x0b:
case ASM_DEC_VECTOR:
case ASM_60X_DLMISS_VECTOR:
case ASM_60X_DSMISS_VECTOR:
case ASM_TRACE_VECTOR:
case ASM_60X_VEC_VECTOR:
case ASM_60X_PERFMON_VECTOR:
case 0x13 /*ASM_BOOKE_FIT_VECTOR*/:
case 0x14 /*ASM_BOOKE_WDOG_VECTOR*/:
case /* emb FP data */ 0x15:
case /* emb FP round */ 0x16:
return 1;
default:
break;
}
return 0;
}
#endif /* 60x style cpu types */
int ppc_vector_is_valid(rtems_vector vector)
@@ -354,22 +398,27 @@ int ppc_vector_is_valid(rtems_vector vector)
return 0;
}
break;
case PPC_8540:
if ( !e500_vector_is_valid(vector) ) {
return 0;
}
break;
#endif
#if ( defined(mpc555) || defined(mpc505) )
#if ( defined(mpc555) || defined(mpc505) || defined(__ppc_generic) )
case PPC_5XX:
if (!mpc5xx_vector_is_valid(vector)) {
return 0;
}
break;
#endif
#if ( defined(mpc860) || defined(mpc821) )
#if ( defined(mpc860) || defined(mpc821) || defined(__ppc_generic) )
case PPC_860:
if (!mpc860_vector_is_valid(vector)) {
return 0;
}
break;
#endif
#if defined(ppc405)
#if ( defined(ppc405) || defined(__ppc_generic) )
case PPC_405:
if (!ppc405_vector_is_valid(vector)) {
return 0;
@@ -387,11 +436,11 @@ int ppc_vector_is_valid(rtems_vector vector)
int ppc_set_exception (const rtems_raw_except_connect_data* except)
{
ISR_Level level;
rtems_interrupt_level k;
if (!ppc_vector_is_valid(except->exceptIndex)) {
if (!ppc_vector_is_valid(except->hdl.vector)) {
printk("ppc_set_exception: vector %d is not valid\n",
except->exceptIndex);
except->hdl.vector);
return 0;
}
/*
@@ -402,43 +451,56 @@ int ppc_set_exception (const rtems_raw_except_connect_data* except)
* to get the previous handler before accepting to disconnect.
*/
if (memcmp(ppc_get_vector_addr(except->exceptIndex),
if (memcmp(ppc_get_vector_addr(except->hdl.vector),
(void*)default_raw_except_entry.hdl.raw_hdl,
default_raw_except_entry.hdl.raw_hdl_size)) {
printk("ppc_set_exception: raw vector not installed\n");
return 0;
}
_ISR_Disable(level);
rtems_interrupt_disable(k);
raw_except_table [except->exceptIndex] = *except;
codemove((void*)ppc_get_vector_addr(except->exceptIndex),
codemove(ppc_get_vector_addr(except->hdl.vector),
except->hdl.raw_hdl,
except->hdl.raw_hdl_size,
PPC_CACHE_ALIGNMENT);
if (except->on)
except->on(except);
_ISR_Enable(level);
rtems_interrupt_enable(k);
return 1;
}
int ppc_get_current_exception (rtems_raw_except_connect_data* except)
{
if (!ppc_vector_is_valid(except->exceptIndex)){
return 0;
}
rtems_interrupt_level k;
int i;
*except = raw_except_table [except->exceptIndex];
if (!ppc_vector_is_valid(except->hdl.vector)){
return 0;
}
return 1;
for (i=0; i < local_settings->exceptSize; i++) {
if ( raw_except_table[i].hdl.vector == except->hdl.vector ) {
rtems_interrupt_disable(k);
if ( raw_except_table[i].hdl.vector == except->hdl.vector ) {
*except = raw_except_table[i];
rtems_interrupt_enable(k);
return 1;
}
rtems_interrupt_enable(k);
}
}
return 0;
}
int ppc_delete_exception (const rtems_raw_except_connect_data* except)
{
ISR_Level level;
rtems_interrupt_level k;
if (!ppc_vector_is_valid(except->exceptIndex)){
if (!ppc_vector_is_valid(except->hdl.vector)){
return 0;
}
/*
@@ -448,16 +510,16 @@ int ppc_delete_exception (const rtems_raw_except_connect_data* except)
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
if (memcmp(ppc_get_vector_addr(except->exceptIndex),
if (memcmp(ppc_get_vector_addr(except->hdl.vector),
(void*)except->hdl.raw_hdl,
except->hdl.raw_hdl_size)) {
return 0;
}
_ISR_Disable(level);
rtems_interrupt_disable(k);
if (except->off)
except->off(except);
codemove((void*)ppc_get_vector_addr(except->exceptIndex),
except->off(except);
codemove(ppc_get_vector_addr(except->hdl.vector),
default_raw_except_entry.hdl.raw_hdl,
default_raw_except_entry.hdl.raw_hdl_size,
PPC_CACHE_ALIGNMENT);
@@ -465,8 +527,9 @@ int ppc_delete_exception (const rtems_raw_except_connect_data* except)
raw_except_table[except->exceptIndex] = default_raw_except_entry;
raw_except_table[except->exceptIndex].exceptIndex = except->exceptIndex;
raw_except_table[except->exceptIndex].hdl.vector = except->hdl.vector;
_ISR_Enable(level);
rtems_interrupt_enable(k);
return 1;
}
@@ -476,8 +539,8 @@ int ppc_delete_exception (const rtems_raw_except_connect_data* except)
*/
int ppc_init_exceptions (rtems_raw_except_global_settings* config)
{
rtems_interrupt_level k;
int i;
ISR_Level level;
/*
* store various accelerators
@@ -486,26 +549,30 @@ int ppc_init_exceptions (rtems_raw_except_global_settings* config)
local_settings = config;
default_raw_except_entry = config->defaultRawEntry;
_ISR_Disable(level);
rtems_interrupt_disable(k);
for (i=0; i <= LAST_VALID_EXC; i++) {
if (!ppc_vector_is_valid(i)){
continue;
}
codemove((void*)ppc_get_vector_addr(i),
raw_except_table[i].hdl.raw_hdl,
raw_except_table[i].hdl.raw_hdl_size,
PPC_CACHE_ALIGNMENT);
if (raw_except_table[i].hdl.raw_hdl != default_raw_except_entry.hdl.raw_hdl) {
if (raw_except_table[i].on)
raw_except_table[i].on(&raw_except_table[i]);
}
else {
if (raw_except_table[i].off)
raw_except_table[i].off(&raw_except_table[i]);
}
}
_ISR_Enable(level);
if ( ppc_cpu_is_bookE() ) {
e500_setup_raw_exceptions();
}
for (i=0; i < config->exceptSize; i++) {
if (!ppc_vector_is_valid(raw_except_table[i].hdl.vector)){
continue;
}
codemove(ppc_get_vector_addr(raw_except_table[i].hdl.vector),
raw_except_table[i].hdl.raw_hdl,
raw_except_table[i].hdl.raw_hdl_size,
PPC_CACHE_ALIGNMENT);
if (raw_except_table[i].hdl.raw_hdl != default_raw_except_entry.hdl.raw_hdl) {
if (raw_except_table[i].on)
raw_except_table[i].on(&raw_except_table[i]);
}
else {
if (raw_except_table[i].off)
raw_except_table[i].off(&raw_except_table[i]);
}
}
rtems_interrupt_enable(k);
return 1;
}

190
c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.h
View File

@@ -31,6 +31,16 @@
#define _LIBCPU_RAW_EXCEPTION_H
#include <rtems/powerpc/powerpc.h>
/* For now, many BSPs still rely on <cpu_flavor> being defined
* but that should be phased out.
* The BSP support for exceptions and interrupts under 'bspsupp'
* is designed to be #ifdef <flavor> FREE.
* BSPs using 'bspsupp' should work with __ppc_generic
*/
#ifndef __ppc_generic
/*
* find out, whether we want to (re)enable the MMU in the assembly code
* FIXME: move this to a better location
@@ -79,8 +89,8 @@
* size LAST_VALID_EXC.
* So until there is a CPU that uses 0xA we'll just use that :-(
*/
#define ASM_VEC_VECTOR 0x0A
#define ASM_VEC_VECTOR_OFFSET (0xf20)
#define ASM_60X_VEC_VECTOR 0x0A
#define ASM_60X_VEC_VECTOR_OFFSET (0xf20)
#define ASM_SYS_VECTOR 0x0C
#define ASM_SYS_VECTOR_OFFSET (ASM_SYS_VECTOR << 8)
@@ -92,25 +102,25 @@
/*
* vectors for PPC405
*/
#define ASM_CRIT_VECTOR ASM_RESET_VECTOR
#define ASM_CRIT_VECTOR_OFFSET (ASM_CRIT_VECTOR << 8)
#define ASM_BOOKE_CRIT_VECTOR ASM_RESET_VECTOR
#define ASM_BOOKE_CRIT_VECTOR_OFFSET (ASM_BOOKE_CRIT_VECTOR << 8)
#define ASM_PIT_VECTOR 0x10
#define ASM_PIT_VECTOR_OFFSET (ASM_PIT_VECTOR << 8)
#define ASM_BOOKE_PIT_VECTOR 0x10
#define ASM_BOOKE_PIT_VECTOR_OFFSET (ASM_BOOKE_PIT_VECTOR << 8)
#define ASM_ITLBMISS_VECTOR 0x11
#define ASM_ITLBMISS_VECTOR_OFFSET (ASM_ITLBMISS_VECTOR << 8)
#define ASM_BOOKE_ITLBMISS_VECTOR 0x11
#define ASM_BOOKE_ITLBMISS_VECTOR_OFFSET (ASM_BOOKE_ITLBMISS_VECTOR << 8)
#define ASM_DTLBMISS_VECTOR 0x12
#define ASM_DTLBMISS_VECTOR_OFFSET (ASM_DTLBMISS_VECTOR << 8)
#define ASM_BOOKE_DTLBMISS_VECTOR 0x12
#define ASM_BOOKE_DTLBMISS_VECTOR_OFFSET (ASM_BOOKE_DTLBMISS_VECTOR << 8)
#define ASM_FIT_VECTOR 0x13
#define ASM_FIT_VECTOR_OFFSET (0x1010)
#define ASM_BOOKE_FIT_VECTOR 0x13
#define ASM_BOOKE_FIT_VECTOR_OFFSET (0x1010)
#define ASM_WDOG_VECTOR 0x14
#define ASM_WDOG_VECTOR_OFFSET (0x1020)
#define ASM_BOOKE_WDOG_VECTOR 0x14
#define ASM_BOOKE_WDOG_VECTOR_OFFSET (0x1020)
#define LAST_VALID_EXC ASM_WDOG_VECTOR
#define LAST_VALID_EXC ASM_BOOKE_WDOG_VECTOR
/*
* bit mask of all exception vectors, that are handled
@@ -119,7 +129,7 @@
* code to determine, whether to use SRR0/SRR1/rfi or SRR2/SRR3/rfci
*/
#define ASM_VECTORS_CRITICAL \
(( 1 << (31-ASM_CRIT_VECTOR)) \
(( 1 << (31-ASM_BOOKE_CRIT_VECTOR)) \
|(1 << (31-ASM_MACH_VECTOR)) \
|(1 << (31-ASM_WDOG_VECTOR)))
@@ -132,81 +142,81 @@
* FIXME: even more vector names might get used in common,
* but the names have diverged between different PPC families
*/
#define ASM_FLOATASSIST_VECTOR 0x0E
#define ASM_FLOATASSIST_VECTOR_OFFSET (ASM_FLOATASSIST_VECTOR << 8)
#define ASM_8XX_FLOATASSIST_VECTOR 0x0E
#define ASM_8XX_FLOATASSIST_VECTOR_OFFSET (ASM_8XX_FLOATASSIST_VECTOR << 8)
#define ASM_SOFTEMUL_VECTOR 0x10
#define ASM_SOFTEMUL_VECTOR_OFFSET (ASM_SOFTEMUL_VECTOR << 8)
#define ASM_8XX_SOFTEMUL_VECTOR 0x10
#define ASM_8XX_SOFTEMUL_VECTOR_OFFSET (ASM_8XX_SOFTEMUL_VECTOR << 8)
#define ASM_ITLBMISS_VECTOR 0x11
#define ASM_ITLBMISS_VECTOR_OFFSET (ASM_ITLBMISS_VECTOR << 8)
#define ASM_8XX_ITLBMISS_VECTOR 0x11
#define ASM_8XX_ITLBMISS_VECTOR_OFFSET (ASM_8XX_ITLBMISS_VECTOR << 8)
#define ASM_DTLBMISS_VECTOR 0x12
#define ASM_DTLBMISS_VECTOR_OFFSET (ASM_DTLBMISS_VECTOR << 8)
#define ASM_8XX_DTLBMISS_VECTOR 0x12
#define ASM_8XX_DTLBMISS_VECTOR_OFFSET (ASM_8XX_DTLBMISS_VECTOR << 8)
#define ASM_ITLBERROR_VECTOR 0x13
#define ASM_ITLBERROR_VECTOR_OFFSET (ASM_ITLBERROR_VECTOR << 8)
#define ASM_8XX_ITLBERROR_VECTOR 0x13
#define ASM_8XX_ITLBERROR_VECTOR_OFFSET (ASM_8XX_ITLBERROR_VECTOR << 8)
#define ASM_DTLBERROR_VECTOR 0x14
#define ASM_DTLBERROR_VECTOR_OFFSET (ASM_DTLBERROR_VECTOR << 8)
#define ASM_8XX_DTLBERROR_VECTOR 0x14
#define ASM_8XX_DTLBERROR_VECTOR_OFFSET (ASM_8XX_DTLBERROR_VECTOR << 8)
#define ASM_DBREAK_VECTOR 0x1C
#define ASM_DBREAK_VECTOR_OFFSET (ASM_DBREAK_VECTOR << 8)
#define ASM_8XX_DBREAK_VECTOR 0x1C
#define ASM_8XX_DBREAK_VECTOR_OFFSET (ASM_8XX_DBREAK_VECTOR << 8)
#define ASM_IBREAK_VECTOR 0x1D
#define ASM_IBREAK_VECTOR_OFFSET (ASM_IBREAK_VECTOR << 8)
#define ASM_8XX_IBREAK_VECTOR 0x1D
#define ASM_8XX_IBREAK_VECTOR_OFFSET (ASM_8XX_IBREAK_VECTOR << 8)
#define ASM_PERIFBREAK_VECTOR 0x1E
#define ASM_PERIFBREAK_VECTOR_OFFSET (ASM_PERIFBREAK_VECTOR << 8)
#define ASM_8XX_PERIFBREAK_VECTOR 0x1E
#define ASM_8XX_PERIFBREAK_VECTOR_OFFSET (ASM_8XX_PERIFBREAK_VECTOR << 8)
#define ASM_DEVPORT_VECTOR 0x1F
#define ASM_DEVPORT_VECTOR_OFFSET (ASM_DEVPORT_VECTOR_OFFSET << 8)
#define ASM_8XX_DEVPORT_VECTOR 0x1F
#define ASM_8XX_DEVPORT_VECTOR_OFFSET (ASM_8XX_DEVPORT_VECTOR_OFFSET << 8)
#define LAST_VALID_EXC ASM_DEVPORT_VECTOR
#define LAST_VALID_EXC ASM_8XX_DEVPORT_VECTOR
#elif (defined(mpc555) || defined(mpc505))
/*
* vectorx for MPC5xx
*/
#define ASM_FLOATASSIST_VECTOR 0x0E
#define ASM_5XX_FLOATASSIST_VECTOR 0x0E
#define ASM_SOFTEMUL_VECTOR 0x10
#define ASM_5XX_SOFTEMUL_VECTOR 0x10
#define ASM_IPROT_VECTOR 0x13
#define ASM_DPROT_VECTOR 0x14
#define ASM_5XX_IPROT_VECTOR 0x13
#define ASM_5XX_DPROT_VECTOR 0x14
#define ASM_DBREAK_VECTOR 0x1C
#define ASM_IBREAK_VECTOR 0x1D
#define ASM_MEBREAK_VECTOR 0x1E
#define ASM_NMEBREAK_VECTOR 0x1F
#define ASM_5XX_DBREAK_VECTOR 0x1C
#define ASM_5XX_IBREAK_VECTOR 0x1D
#define ASM_5XX_MEBREAK_VECTOR 0x1E
#define ASM_5XX_NMEBREAK_VECTOR 0x1F
#define LAST_VALID_EXC ASM_NMEBREAK_VECTOR
#define LAST_VALID_EXC ASM_5XX_NMEBREAK_VECTOR
#else /* 60x style cpu types */
#define PPC_HAS_60X_VECTORS
#define ASM_PERFMON_VECTOR 0x0F
#define ASM_PERFMON_VECTOR_OFFSET (ASM_PERFMON_VECTOR << 8)
#define ASM_60X_PERFMON_VECTOR 0x0F
#define ASM_60X_PERFMON_VECTOR_OFFSET (ASM_60X_PERFMON_VECTOR << 8)
#define ASM_IMISS_VECTOR 0x10
#define ASM_60X_IMISS_VECTOR 0x10
#define ASM_DLMISS_VECTOR 0x11
#define ASM_60X_DLMISS_VECTOR 0x11
#define ASM_DSMISS_VECTOR 0x12
#define ASM_60X_DSMISS_VECTOR 0x12
#define ASM_ADDR_VECTOR 0x13
#define ASM_ADDR_VECTOR_OFFSET (ASM_ADDR_VECTOR << 8)
#define ASM_60X_ADDR_VECTOR 0x13
#define ASM_60X_ADDR_VECTOR_OFFSET (ASM_60X_ADDR_VECTOR << 8)
#define ASM_SYSMGMT_VECTOR 0x14
#define ASM_SYSMGMT_VECTOR_OFFSET (ASM_SYSMGMT_VECTOR << 8)
#define ASM_60X_SYSMGMT_VECTOR 0x14
#define ASM_60X_SYSMGMT_VECTOR_OFFSET (ASM_60X_SYSMGMT_VECTOR << 8)
#define ASM_VEC_ASSIST_VECTOR 0x16
#define ASM_VEC_ASSIST_VECTOR_OFFSET (ASM_VEC_ASSIST_VECTOR << 8)
#define ASM_60X_VEC_ASSIST_VECTOR 0x16
#define ASM_60X_VEC_ASSIST_VECTOR_OFFSET (ASM_60X_VEC_ASSIST_VECTOR << 8)
#define ASM_ITM_VECTOR 0x17
#define ASM_ITM_VECTOR_OFFSET (ASM_ITM_VECTOR << 8)
#define ASM_60X_ITM_VECTOR 0x17
#define ASM_60X_ITM_VECTOR_OFFSET (ASM_60X_ITM_VECTOR << 8)
#define LAST_VALID_EXC ASM_ITM_VECTOR
#define LAST_VALID_EXC ASM_60X_ITM_VECTOR
#endif
@@ -222,6 +232,61 @@
#else
#endif
#else /* __ppc_generic */
#define ASM_RESET_VECTOR 0x01
#define ASM_MACH_VECTOR 0x02
#define ASM_PROT_VECTOR 0x03
#define ASM_ISI_VECTOR 0x04
#define ASM_EXT_VECTOR 0x05
#define ASM_ALIGN_VECTOR 0x06
#define ASM_PROG_VECTOR 0x07
#define ASM_FLOAT_VECTOR 0x08
#define ASM_DEC_VECTOR 0x09
#define ASM_60X_VEC_VECTOR 0x0A
#define ASM_SYS_VECTOR 0x0C
#define ASM_TRACE_VECTOR 0x0D
#define ASM_BOOKE_CRIT_VECTOR 0x01
#define ASM_BOOKE_PIT_VECTOR 0x10
#define ASM_BOOKE_ITLBMISS_VECTOR 0x11
#define ASM_BOOKE_DTLBMISS_VECTOR 0x12
#define ASM_BOOKE_FIT_VECTOR 0x13
#define ASM_BOOKE_WDOG_VECTOR 0x14
#define ASM_8XX_FLOATASSIST_VECTOR 0x0E
#define ASM_8XX_SOFTEMUL_VECTOR 0x10
#define ASM_8XX_ITLBMISS_VECTOR 0x11
#define ASM_8XX_DTLBMISS_VECTOR 0x12
#define ASM_8XX_ITLBERROR_VECTOR 0x13
#define ASM_8XX_DTLBERROR_VECTOR 0x14
#define ASM_8XX_DBREAK_VECTOR 0x1C
#define ASM_8XX_IBREAK_VECTOR 0x1D
#define ASM_8XX_PERIFBREAK_VECTOR 0x1E
#define ASM_8XX_DEVPORT_VECTOR 0x1F
#define ASM_5XX_FLOATASSIST_VECTOR 0x0E
#define ASM_5XX_SOFTEMUL_VECTOR 0x10
#define ASM_5XX_IPROT_VECTOR 0x13
#define ASM_5XX_DPROT_VECTOR 0x14
#define ASM_5XX_DBREAK_VECTOR 0x1C
#define ASM_5XX_IBREAK_VECTOR 0x1D
#define ASM_5XX_MEBREAK_VECTOR 0x1E
#define ASM_5XX_NMEBREAK_VECTOR 0x1F
#define ASM_60X_PERFMON_VECTOR 0x0F
#define ASM_60X_IMISS_VECTOR 0x10
#define ASM_60X_DLMISS_VECTOR 0x11
#define ASM_60X_DSMISS_VECTOR 0x12
#define ASM_60X_ADDR_VECTOR 0x13
#define ASM_60X_SYSMGMT_VECTOR 0x14
#define ASM_60X_VEC_ASSIST_VECTOR 0x16
#define ASM_60X_ITM_VECTOR 0x17
#define LAST_VALID_EXC 0x1F
#endif /* __ppc_generic */
#ifndef ASM
@@ -319,6 +384,11 @@ extern int ppc_vector_is_valid(rtems_vector vector);
extern int ppc_init_exceptions (rtems_raw_except_global_settings* config);
extern int ppc_get_exception_config (rtems_raw_except_global_settings** config);
void* ppc_get_vector_addr(rtems_vector vector);
int ppc_is_e500();
void e500_setup_raw_exceptions();
/* This variable is initialized to 'TRUE' by default;
* BSPs which have their vectors in ROM should set it
* to FALSE prior to initializing raw exceptions.