There is support for the LEON3 processor available in Binutils 2.24 and
the GCC 4.8 branch and GCC mainline.
GCC 4.8 branch:
http://gcc.gnu.org/viewcvs/gcc/branches/?view=log&pathrev=205331
GCC mainline:
http://gcc.gnu.org/viewcvs/gcc/trunk/?view=log&pathrev=202664
It is mandatory to use this option for SMP on LEON3 since it enables
usage of C11 atomic operations. It makes it also possible to use an
inline function for _CPU_SMP_Get_current_processor() which avoids the
function call overhead in critical sections.
OpenRISC/or1ksim BSP: The new sim.cfg file configures or1ksim emulator with HW
capabilities that the current RTEMS/or1ksim BSP supports.
README: HOWTO run the or1ksim simulator.
Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the "flush instruction cache" bit in the cache control register.
A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
This patch allows the user to configure the PHY address for the DWMAC
driver by giving a pointer to a dwmac_user_cfg structure to network
stack via rtems_bsdnet_ifconfig::drv_ctrl.
BSP completes build with tests and debug enabled for all three variants now
tms570ls3137_hdk
tms570ls3137_hdk_intram
tms570ls3137_hdk_sdram
Even that all enabled tests builds for internal RAM variant, many
of them are expected to fail on hardware because whole tests
including code, data and runtime work area demands has to fit
into 256 kB of RAM.
This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram
BSP variant in in default build. Debug build with --enable-rtems-debug set
has succeed for samples subset of tests as well.
Also cleanup:
* Remove un-needed interrupt disables.
* Address errata "e989: FLASH: Disable Prefetch during programming and erase"
* Use RTEMS_ARRAY_SIZE() macro instead of own macro.
Included variants:
tms570ls3137_hdk_intram - place code and data into internal SRAM
tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM
tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication
stored and running directly from flash. Not working yet.
Chip initialization code not included in BSP.
External startup generated by TI's HalCoGen was used for
testing and debugging.
More information about TMS570 BSP can be found at
http://www.rtems.org/wiki/index.php/Tms570
Patch version 2
- most of the formatting suggestion applied.
- BSP converted to use clock shell
- console driver "set attributes" tested. Baudrate change working
Patch version 3
- more formatting changes.
- removed leftover defines and test functions
Todo:
refactor header files (name register fields)
The problem wit incorrect switching of pins into analog mode manifestes
on LPC4088 based board.
LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin
with analog option). The pin was listed as D category on LPC1788
which does not have analog mode control bit. If analog option is
not explicitly switched off on LPC4088 then the pin does not work
as digital pin.
Code tested on LPC1788 and no problems has been observed even that
manual specifies the IOCON_ADMODE field as reserved and should
be written as zero. But even RTEMS lpc24xx_gpio_config sets this
bit unconditionally.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
The first pass at building these was without networking enabled.
This pass addresses that plus accounts for some new BSPs which
needed testsuite.tcfg files and BSPs which could not link tests
which had been added since the first pass.
