Add support for the BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY build option
for the GICv2 support. This option is useful for multiprocessor systems
without SMP support.
Do not wait in the individual _CPU_SMP_Start_processor() for the
secondary processor. Wait for all of them in
_CPU_SMP_Finalize_initialization() before the L2 cache is enabled.
There is no need to wait for the secondary processor in
_CPU_SMP_Start_processor() since _CPU_SMP_Finalize_initialization() does
nothing.
The caller of _CPU_SMP_Start_processor() ensures that we do not start
the current processor.
Remove copy and paste from the arm SMP support. The shared aarch64
implementation of rtems_cache_enable_data() does not enable a particular
cache, it just enables the C bit in the SCTLR_EL1. This is already done
in aarch64_mmu_enable(). There is no need to wait for secondary
processors in _CPU_SMP_Start_processor().
Calls from Thumb code into ARM code require the use of a BLX instruction
and an optional offset prefix instruction. The BLX instruction encoding
requires that the least significant bit be 0 in all cases while the BL
instruction for Thumb-to-Thumb calls includes that bit as part of the
offset. This ensures that bit 0 of the BLX is set to 0 as required by
the instruction encoding specification.
Fix _CPU_SMP_Get_current_processor(), since read from register MPIDR_EL1
(the least significant byte) is not always right,for example the least
significant byte of MPIDR_EL1 is always zero for cortex-a55.
aarch64 has a thread ID register TPIDR_EL1 available for for OS management
purposes. RTEMS stores per-CPU control in TPIDR_EL1 when the core startup,
so we can use _Per_CPU_Get_index() to get current processor index.
update #5064
- Refactor the pl011 driver to be extensible.
- Add IRQ support and baudrate configuration support for pl011 driver.
- Modify related BSP.
- Add doxygen comments for arm-pl011.
Close#5026
Co-authored-by: Ning Yang <yangn0@qq.com>
It is not clear why this is necessary. For example, the
zynq_uart_initialize() does not issue the '\r' before waiting for an
inactive transmission state.
Similar to the recent commit in tms570-sci.c, the assumption that a UART will
only see printable ASCII characters, instead of any value in the range
0x00-0xFF, is wrong.
A non forgiving binary protocol will be thrown off by this driver sending
"\r\r\r\r" when initializing.
If a user wants to flush the interface, they should explicitely use the
dedicated function `tcflush(fd, TCIOFLUSH);`.
Coverity CID 1619144
In rtems_aio_completed_list_op() memory was getting freed without releasing
a lock.
This commit should also solve coverity issues 1619145, 1619143 and 1619142
since they all seem to be generated by rtems_aio_completed_list_op().
Closes#5127
- change type unsigned to uint64_t, it might overflowed if
the size is greater the 4GB.
- increase buffer size is to eliminate the compiler's warning
that the buffer might be too small
