When encountering an error during filesystem creation, fat_fd must be
cleaned up appropriately once the file is opened. There was an
opportunity for a resource leak due to jumping to the incorrect error
handling label.
Revert JFFS2 to non-granular locking. This makes the superblock
available to the delayed work that it owns so that delayed work
processing can ensure that shared resources are being exclusively
accessed. This change only affects NAND systems. Moving forward with
granular locking will require a significant investment of time in
producing a test harness that doesn't require hardware such that this
can get a reasonable amount of test coverage.
The TM27 support may define TM27_INTERRUPT_VECTOR_ALTERNATIVE to provide
an alternative software generated interrupt request which is raised by
_TM27_Raise_alternative() and cleared by _TM27_Clear_alternative().
Both functions shall return an RTEMS status code. This interrupt vector
may be used to test the interrupt controller support on targets which do
not provide generic software generated interrupts.
Update #3716.
Expose functions to directly manipulate the bad block table (BBT). These
functions are necessary to correct possible BBT corruption caused by
bugs in the BBT management layer.
The XNandPsu_EraseBlock function takes a target device and a block
offset for erasure. Ensure the block offset is within the size of the
target device.
When marking the trailing blocks on a device as reserved for Bad Block
Table usage, ensure that the correct blocks are marked. This resolves an
off-by-one error that was marking one block too low and leaving the last
block in the device unmarked.
The Bad Block Table is a per-device catalog of the dispositions of each
block in the device. Only read enough data to determine the dispositions
of blocks for the device being read.
The xnandpsu driver includes functionality to map back and forth between
the flash-based BBT and the memory-based BBT with the values in each
being a bitwise inversion of each other. This resolves several bugs in
this process and simplifies the inversion from operating on the block
representation to operating on the entire BBT entry (4 blocks, 2 bits
per block, one byte total).
Bugs resolved in XNandPsu_ConvertBbt():
* The calculation of memory BBT entry offset was off by a factor of 4
* The entry offset into the flash BBT has been removed since each flash
BBT directly describes the flash space it is contained within and has
no reference to other devices in the chip
Bugs resolved in XNandPsu_WriteBbt():
* The BBT length calculated was reduced to NumTargetBlocks from
NumBlocks since only the relevant portion of the in-memory BBT should
be written to the flash-based BBT space
* An offset was applied to values retrieved from the in-memory BBT so
that only the relevant portion was converted and written to the
flash-based BBT
The XNandPsu_IsBlockBad() function is insufficient for JFFS2 to
determine whether a block is usable since the function does not report
reserved blocks. JFFS2 is also unable to use the last 4 blocks of each
target attached to the NAND controller since they are reserved for the
Bad Block Table (BBT), but not necessarily marked as such.
Hi all, this is my first email patch submission and my first contribution to RTEMS, so please give any
feedback you have!
This patch enables interrupt driven data reception on USART ports on
STM32F4 series chips. This feature is gated behind the config flag
BSP_CONSOLE_USE_INTERRUPTS. If this flag is not set to True, the older
polling implementation will be used. I tested this feature on STM32F401CE
(blackpill) and STM32 Nucleo F411RE boards, with both capable of keeping
up with a 115200 baud continous data stream. With the older polling
implementation, both would drop bytes at 9600 baud. In addition, I
updated the implementation of usart_set_attributes to support changing
the baud rate of the USART port based on the input speed.
Place the vector table in the start section so that the overlay can be
avoided if we execute from internal flash. The problem is that when the
POM is enabled, the ECC cannot be enabled for the internal flash.
