In SMP configurations, check that we run on a configured processor. If not,
then there is not much that can be done since we do not have a stack available
for this processor. Just loop forever in this case. Do this in assemlby to
ensure that no stack memory is used.
Make the support for starting in EL2/EL3 customizable. A boot loader or
the Arm Trusted Firmware should start RTEMS in non-secure EL1 mode.
In start.S, use local labels.
For the aarch64/xilinx-zynqmp the support for starting in EL2/EL3 is
disabled by default. For the Qemu xlnx-zcu102 machine, the default is
to start in non-secure EL1 mode. This can be controlled by options, for
example "-machine xlnx-zcu102,secure=on,virtualization=on".
The information from the README.md have been merged into the
documentation.
The necessary tools for the sdcard.sh are quite tricky to build. All
necessary information to create an SD image are in the documentation
already. So the script isn't necessary any more.
Update #5088
Dynamically mapped blocks must be aligned to the MMU page size just like
startup-configured blocks. This was not being enforced and could cause a
hang with bad input.
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to
emphasize that this BSP is for the lock-step mode RPU configuration.
Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split
mode RPU configuration for core 0 and 1 respectively.
Remove copyright from DornerWorks since the files contain not contributions
from this company. Fix the copyright years of the embedded brains
contributions.
Add support for the BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY build option
for the GICv2 support. This option is useful for multiprocessor systems
without SMP support.
Do not wait in the individual _CPU_SMP_Start_processor() for the
secondary processor. Wait for all of them in
_CPU_SMP_Finalize_initialization() before the L2 cache is enabled.
There is no need to wait for the secondary processor in
_CPU_SMP_Start_processor() since _CPU_SMP_Finalize_initialization() does
nothing.
The caller of _CPU_SMP_Start_processor() ensures that we do not start
the current processor.
Remove copy and paste from the arm SMP support. The shared aarch64
implementation of rtems_cache_enable_data() does not enable a particular
cache, it just enables the C bit in the SCTLR_EL1. This is already done
in aarch64_mmu_enable(). There is no need to wait for secondary
processors in _CPU_SMP_Start_processor().
Fix _CPU_SMP_Get_current_processor(), since read from register MPIDR_EL1
(the least significant byte) is not always right,for example the least
significant byte of MPIDR_EL1 is always zero for cortex-a55.
aarch64 has a thread ID register TPIDR_EL1 available for for OS management
purposes. RTEMS stores per-CPU control in TPIDR_EL1 when the core startup,
so we can use _Per_CPU_Get_index() to get current processor index.
update #5064
- Refactor the pl011 driver to be extensible.
- Add IRQ support and baudrate configuration support for pl011 driver.
- Modify related BSP.
- Add doxygen comments for arm-pl011.
Close#5026
Co-authored-by: Ning Yang <yangn0@qq.com>
It is not clear why this is necessary. For example, the
zynq_uart_initialize() does not issue the '\r' before waiting for an
inactive transmission state.
Similar to the recent commit in tms570-sci.c, the assumption that a UART will
only see printable ASCII characters, instead of any value in the range
0x00-0xFF, is wrong.
A non forgiving binary protocol will be thrown off by this driver sending
"\r\r\r\r" when initializing.
If a user wants to flush the interface, they should explicitely use the
dedicated function `tcflush(fd, TCIOFLUSH);`.
The IRQ list in this file are specific to PC hardware and should be
part of the BSP. Further, there are paravirtualized environments which
do not follow the PC hardware IRQ list. Moving this avoids collisions.
This adds support for the 6 SPI interfaces on the STM32H7 series chips
with an initial example for the stm32h750b discovery kit development
board. Configuration is similar to existing peripherals. Chip select
lines are software-controlled since the SPI peripheral only supports a
single hardware-controlled chip select line. This implementation does
not use interrupts.
The default exception handler uses the Save Program Status Register
(SPSR), however, if _ARMV4_Exception_reserved_default() would get
called, the state of this register is unpredictable. Replace potential
calls to _ARMV4_Exception_reserved_default() with an undefined
instruction.
Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM
GIC support. Enable this option for arm/altera-cyclone-v and
arm/xilinx-zynq BSPs by default.
The EOZ9 RTC has a similar register interface like the MCP7940M (and
quite some other I2C RTCs). This commit:
* Extracts the generic parts from MCP7940M and moves it into a generic
i2c-rtc driver.
* Uses the new i2c-rtc for the MCP7940M.
* Uses the new i2c-rtc for the new Abracom EOZ9.
