Commit Graph

171 Commits

Author SHA1 Message Date
Purva Yeshi
eaaeebedda riscv/beaglevfire: Rename 'bvf' to 'beaglevfire' 2024-10-25 21:23:23 +00:00
Francescodario Cuzzocrea
9d45cf1b44 riscv: add bsp for beagle v fire
Signed-off-by: Francescodario Cuzzocrea <bosconovic@gmail.com>
2024-10-25 21:23:23 +00:00
Francescodario Cuzzocrea
0e3792edbf riscv: Work area size based on /memory node in fdt
* It is not granted that we will always access to natually aligned
   access. So, before handling endianess do byte-a-byte load using
   the appropriate libfdt function to avoid unaligned access issues

Signed-off-by: Francescodario Cuzzocrea <bosconovic@gmail.com>
2024-10-25 21:23:23 +00:00
Kevin Kirspel
e9957cd8e3 riscv/niosv: Adding a new NIOS V BSP to RISC-V 2024-10-25 13:49:36 +00:00
Sebastian Huber
f43042cd06 bsps: Move <bsp/linker-symbols.h> to shared
Move architecture-independent items to a shared <bsp/linker-symbols.h>.
Allow architectures to customize it through <bsp/linker-symbols-arch.h>.
2024-10-11 01:27:48 +02:00
Sebastian Huber
e81a5db70e score: Remove unused _CPU_Fatal_halt()
Update #5067.
2024-08-23 14:54:37 +00:00
Sebastian Huber
5ea022ff12 bsps/riscv: Provide bsp_reset()
Update #5067.
2024-08-23 14:54:37 +00:00
Sebastian Huber
ab8817ca03 rtems: Add get/set interrupt priorities
Add directives to get and set the priority of an interrupt vector.

Implement the directives for the following BSP families:

* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq

Implement the directives for the following interrupt controllers:

* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)

Update #5002.
2024-05-10 13:26:22 +00:00
Sebastian Huber
5b0e355ed7 bsps: Move declarations to <bsp/irq-generic.h>
Move declarations of bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() to <bsp/irq-generic.h>.  Canonicalize the
<bsp/irq.h> includes.

Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
needed (usually RTEMS_SMP).

Provide stub implementations for i386 to fix build errors.
2024-03-27 20:20:38 +01:00
Sebastian Huber
1eed6f8bfc bsps: Avoid unused argument in clock interrupt
Pass the parameter of the clock interrupt handler to
Clock_driver_support_at_tick() and Clock_driver_timecounter_tick().  This makes
it possible to use the interrupt handler argument in clock drivers.

Use the interrupt handler provided by Clock_driver_support_install_isr() to
avoid local delarations of Clock_isr().

Update #4862.
2024-03-20 16:34:09 +01:00
Sebastian Huber
8fdecf6c55 bsps: Use new APBUART register block API 2023-07-14 12:21:33 +02:00
Sebastian Huber
2d71cba033 bsps/grlib: Add generated headers
Close #4828.
2023-07-14 09:11:19 +02:00
Sebastian Huber
4e3e9df1b4 bsps: Remove uses of BSP-specific interrupt API
Update #3269.
2023-06-16 07:30:50 +02:00
Sebastian Huber
bcef89f236 Update company name
The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
2023-05-20 11:05:26 +02:00
Alan Cudmore
26853a0624 bsps/riscv: add riscv/kendrytek210 BSP variant source changes
This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.

Updates #4876
2023-03-28 14:04:04 -05:00
Alan Cudmore
ca1c4e70f5 bsps/riscv: add device tree source and device tree blob header for k210 bsp variant
This patch adds the k210 device tree source and the corresponding
device tree blob encoded in the header which is used for the
embedded device tree blob for the Kendryte K210 BSP variant.

Updates #4876
2023-03-28 14:04:04 -05:00
Sebastian Huber
11cc51ef27 bsps/riscv: Use per-CPU mtimecmp in clock driver
Use the mtimecmp from the PLIC/CLINT initialization in the clock driver.  This
register is defined by the device tree and does not assume a fixed mapping.
2023-03-17 07:25:34 +01:00
Sebastian Huber
cbddf5decd bsps/riscv: Fix riscv_get_hart_index_by_phandle()
Take a non-zero RISCV_BOOT_HARTID into account.
2023-03-17 07:25:34 +01:00
Sebastian Huber
e5233057be bsps/riscv: Make SMP start more robust
In SMP configurations, check that we run on a configured processor.  If not,
then there is not much that can be done since we do not have a stack available
for this processor.  Just loop forever in this case.  Do this in assemlby to
ensure that no stack memory is used.
2023-03-17 07:25:23 +01:00
Sebastian Huber
bb465c8548 doxygen: Add Doxygen files to a group
Update #3707.
2023-02-16 08:27:09 +01:00
Sebastian Huber
6136e28bf9 clockdrv: Add clock driver implementation group
Use standard wording in Clock Driver related files.

Update #3706.
2023-01-24 09:56:53 +01:00
Sebastian Huber
10ee41a8a3 tm27: Avoid function pointer casts
Add TM27_USE_VECTOR_HANDLER to select the interrupt handler type used by
the <tm27.h> implementation.

Close #4820.
2023-01-24 09:56:53 +01:00
Sebastian Huber
d46366a2e7 riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORT
Low-end configurations may want to have the HTIF support removed.
Enable the option by default.  Fix formatting.  Fix node validity
checks.

Updates #4779.
2023-01-12 08:15:58 +01:00
Hesham Almatary
88b80a5fd0 RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORT
Updates #4779
2022-12-23 09:21:14 +00:00
Sebastian Huber
71d1acd41d bsps/irq: Rename handler in dispatch table
The name handler table was a bit misleading after the last rework.
Rename it to distach table.  Update the documentation accordingly.

Update #4769.
2022-12-02 10:25:39 +01:00
Sebastian Huber
d9c7db505c bsps/riscv: Simplify PLIC support
In uniprocessor configurations there is no need to take interrupt affinities
into account for the interrupt vector enable/disable.
2022-11-23 07:56:12 +01:00
Sebastian Huber
d448aa4d05 bsps/riscv: Fix PLIC enable register count 2022-11-23 07:56:12 +01:00
Sebastian Huber
733d9b750c bsps/riscv: Add riscv_plic_cpu_0_init()
Move boot processor initialization of PLIC to separate function.
2022-11-23 07:56:12 +01:00
Sebastian Huber
5756a6af10 bsps/riscv: Fix bsp_fdt_map_intr()
The interrupt numbers in the device tree are usually PLIC interrupts.  Map the
number to the vector number associated with an external interrupt.
2022-11-23 07:56:12 +01:00
Daniel Cederman
18a181c267 bsps/riscv: Change license to BSD-2 for files with Gaisler copyright
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.

Updates #3053.
2022-11-14 11:00:14 +01:00
Sebastian Huber
77c8d822c3 bsps/riscv: Fix software interrupt dispatching
In SMP configurations, there may be no software interrupt handler
installed when the software interrupt is processed.  Add the new
interrupt handler dispatch variant
bsp_interrupt_handler_dispatch_unlikely() for this special case.
2022-11-11 16:38:25 +01:00
Sebastian Huber
908ffc7a93 bsps/noel: Fix interrupt support 2022-11-11 16:38:25 +01:00
Sebastian Huber
bfdfc979fd bsps/riscv: Fix PLIC enable register count
Each PLIC enable register has 32 bits, so we have to divide by 32.
2022-11-10 15:17:07 +01:00
Sebastian Huber
e4210d5a08 bsps/riscv: Skip init on not configured processors 2022-11-10 08:55:38 +01:00
Sebastian Huber
3e5ccdd34e bsps/riscv: Simplify riscv_plic_init() 2022-11-10 08:55:38 +01:00
Sebastian Huber
d2bac3d730 bsps/riscv: Simplify riscv_clint_init() 2022-11-10 08:55:38 +01:00
Sebastian Huber
ccf09a6e16 bsps/riscv: Add tm27 support 2022-11-10 08:55:38 +01:00
Sebastian Huber
ba53a177ab bsps/riscv: Always dispatch software interrupts
This helps to run the interrupt API validation tests.
2022-11-10 08:55:38 +01:00
Sebastian Huber
47d156d706 bsps/riscv: bsp_interrupt_get/set_affinity()
Provide bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
RTEMS_SMP is enabled.  Replace fatal error with a status code.
2022-11-10 08:55:38 +01:00
Sebastian Huber
1bf1c779e1 bsps/riscv: bsp_interrupt_raise_on()
Implement bsp_interrupt_raise_on() and bsp_interrupt_raise().
2022-11-10 08:55:38 +01:00
Sebastian Huber
8a51ecc7b9 bsps/riscv: bsp_interrupt_is_pending()
Implement this function.
2022-11-10 08:55:38 +01:00
Sebastian Huber
d156d7b2f8 bsps/riscv: bsp_interrupt_get_attributes()
Implement this function.
2022-11-10 08:55:38 +01:00
Sebastian Huber
a52fc42454 bsps/riscv: Improve bsp_interrupt_vector_disable()
Add support for hart-specific software and timer interrupts.
2022-11-10 08:55:38 +01:00
Sebastian Huber
e19d490fbe bsps/riscv: Improve bsp_interrupt_vector_enable()
Add support for hart-specific software and timer interrupts.
2022-11-10 08:55:38 +01:00
Sebastian Huber
16c352de2f bsps/riscv: bsp_interrupt_vector_is_enabled()
Implement this function.
2022-11-10 08:55:38 +01:00
Sebastian Huber
9c80a88694 bsps/riscv: bsp_interrupt_is_valid_vector()
Implement this function.
2022-11-10 08:55:38 +01:00
Sebastian Huber
b4ffaa7cdc bsps/riscv: Use start data for object
Maybe this helps to ensure that the object is properly aligned.

Update #4658.
2022-11-04 14:01:44 +01:00
Sebastian Huber
89ba2a9838 bsps/riscv: Workaround for sporadic linker issues
Disable the linker relaxation in start.S to work around an issue described
here:

https://mail.gnu.org/archive/html/bug-binutils/2021-03/msg00164.html

The real issue is probably in the linker command file or the linker itself.

Update #4658.
2022-10-28 14:05:02 +02:00
Alan Cudmore
1d2fab8a79 bsps: Improve riscv console FDT parsing
This fixes a problem with parsing the FDT compatible property by
replacing the RISCV_CONSOLE_IS_COMPATIBLE macro with calls to
the fdt_stringlist_contains function. The macro only works when
the compatible FDT entry is a single string and not a list of
strings. The new call will compare each item in the string list.

Close #4728.
2022-10-14 08:15:14 -05:00
Sebastian Huber
e9a69c5744 riscv: Move functions to avoid build issues
The _RISCV_Map_cpu_index_to_hardid() and _RISCV_Map_hardid_to_cpu_index()
functions must be available to all riscv BSPs.
2022-10-14 10:52:52 +02:00