* Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
* rtems/score/mipstypes.h: Removed.
* rtems/score/types.h: New file via CVS magic.
* Makefile.am, rtems/score/cpu.h: Account for name change.
* cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
* rtems/score/cpu.h: Fixed register numbering in comments and made
interrupt enable/disable more robust.
* cpu_asm.S: Added support for the debug exception vector, cleaned
up the exception processing & exception return stuff. Re-added
EPC in the task context structure so the gdb stub will know where
a thread is executing. Should've left it there in the first place...
* idtcpu.h: Added support for the debug exception vector.
* cpu.c: Added ___exceptionTaskStack to hold a pointer to the
stack frame in an interrupt so context switch code can get the
userspace EPC when scheduling.
* rtems/score/cpu.h: Re-added EPC to the task context.
* cpu_asm.S: Fixed exception return address, modified FP context
switch so FPU is properly enabled and also doesn't screw up the
exception FP handling.
* idtcpu.h: Added C0_TAR, the MIPS target address register used for
returning from exceptions.
* iregdef.h: Added R_TAR to the stack frame so the target address
can be saved on a per-exception basis. The new entry is past the
end of the frame gdb cares about, so doesn't affect gdb or cpu.h
stuff.
* rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
to obtain FPU defines without systax errors generated by the C
defintions.
* cpu.c: Improved interrupt level saves & restores.
* cpu_asm.S: Enhanced to save/restore more registers on
exceptions.
* rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
register individually and document when it is saved.
* idtcpu.h: Added constants for the coprocessor 1 registers
revision and status.
* cpu.c: Enhancements and fixes for modifying the SR when changing
the interrupt level.
* cpu_asm.S: Fixed handling of FP enable bit so it is properly
managed on a per-task basis, improved handling of interrupt levels,
and made deferred FP contexts work on the MIPS.
* rtems/score/cpu.h: Modified to support above changes.
This was tracked as PR91.
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
is used to specify if the port uses the standard macro for this (FALSE).
A TRUE setting indicates the port provides its own implementation.
* cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
compilation block with (CPU_HARDWARE_FP == FALSE). Reported by
Wayne Bullaughey <wayne@wmi.com>.
* rtems/score/mips.h: Added constants for MIPS exception numbers.
All exceptions should be given low numbers and thus can be installed
and processed in a uniform manner. Variances between various MIPS
ISA levels were not accounted for.
* rtems/score/cpu.h: Add the interrupt stack structure and enhance
the context initialization to account for floating point tasks.
* rtems/score/mips.h: Added the routines mips_set_cause(),
mips_get_fcr31(), and mips_set_fcr31().
* Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
* cpu_asm.S: Added code to save and restore SR and EPC to
properly support nested interrupts. Note that the ISR
(not RTEMS) enables interrupts allowing the nesting to occur.
* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
Also reimplemented some assembly routines in C further reducing
the amount of assembly and increasing maintainability.
