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2001-01-09 Joel Sherrill <joel@OARcorp.com>

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* cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
	to make it easier to conditionalize the code for various ISA levels.
This commit is contained in:
Joel Sherrill
2001-01-09 16:48:26 +00:00
parent 96e34e007f
commit 16ad7eafed
8 changed files with 54 additions and 12 deletions
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5
c/src/exec/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,8 @@
2001-01-09 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
to make it easier to conditionalize the code for various ISA levels.
2001-01-08 Joel Sherrill <joel@OARcorp.com>
* idtcpu.h: Commented out definition of "wait". It was stupid to

10
c/src/exec/score/cpu/mips/cpu_asm.S
View File

@@ -367,7 +367,7 @@ ENDFRAME(_CPU_Context_switch)
FRAME(_CPU_Context_switch,sp,0,ra)
mfc0 t0,C0_SR
li t1,~SR_IEC
li t1,~(SR_INTERRUPT_ENABLE_BITS)
sw t0,C0_SR_OFFSET*4(a0) /* save status register */
and t0,t1
mtc0 t0,C0_SR /* first disable ie bit (recommended) */
@@ -402,12 +402,12 @@ _CPU_Context_switch_restore:
lw t0,C0_EPC_OFFSET*4(a1)
mtc0 t0,C0_EPC
lw t0, C0_SR_OFFSET*4(a1)
andi t0,SR_IEC /* we know IEC=0, e.g. disabled */
beq t0,$0,_CPU_Context_1 /* set IEC level from restore context */
andi t0,(SR_INTERRUPT_ENABLE_BITS) /* we know 0 disabled */
beq t0,$0,_CPU_Context_1 /* set level from restore context */
mfc0 t0,C0_SR
nop
or t0,SR_IEC /* new_sr = sr | SR_IEC */
mtc0 t0,C0_SR /* set with enabled */
or t0,(SR_INTERRUPT_ENABLE_BITS) /* new_sr = old sr with enabled */
mtc0 t0,C0_SR /* set with enabled */
_CPU_Context_1:

2
c/src/exec/score/cpu/mips/rtems/score/cpu.h
View File

@@ -599,7 +599,7 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define _CPU_ISR_Disable( _level ) \
do { \
mips_get_sr( _level ); \
mips_set_sr( (_level) & ~SR_IMASK ); \
mips_set_sr( (_level) & ~SR_INTERRUPT_ENABLE_BITS ); \
} while(0)
/*

16
c/src/exec/score/cpu/mips/rtems/score/mips.h
View File

@@ -22,6 +22,22 @@ extern "C" {
#include <idtcpu.h>
#endif
/*
* SR bits that enable/disable interrupts
*
* NOTE: XXX what about SR_ERL?
*/
#if __mips == 3
#ifdef ASM
#define SR_INTERRUPT_ENABLE_BITS 0x03
#else
#define SR_INTERRUPT_ENABLE_BITS SR_IE|SR_EXL
#endif
#else
#define SR_INTERRUPT_ENABLE_BITS SR_IEC
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the "no cpu"

5
cpukit/score/cpu/mips/ChangeLog
View File

@@ -1,3 +1,8 @@
2001-01-09 Joel Sherrill <joel@OARcorp.com>
* cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
to make it easier to conditionalize the code for various ISA levels.
2001-01-08 Joel Sherrill <joel@OARcorp.com>
* idtcpu.h: Commented out definition of "wait". It was stupid to

10
cpukit/score/cpu/mips/cpu_asm.S
View File

@@ -367,7 +367,7 @@ ENDFRAME(_CPU_Context_switch)
FRAME(_CPU_Context_switch,sp,0,ra)
mfc0 t0,C0_SR
li t1,~SR_IEC
li t1,~(SR_INTERRUPT_ENABLE_BITS)
sw t0,C0_SR_OFFSET*4(a0) /* save status register */
and t0,t1
mtc0 t0,C0_SR /* first disable ie bit (recommended) */
@@ -402,12 +402,12 @@ _CPU_Context_switch_restore:
lw t0,C0_EPC_OFFSET*4(a1)
mtc0 t0,C0_EPC
lw t0, C0_SR_OFFSET*4(a1)
andi t0,SR_IEC /* we know IEC=0, e.g. disabled */
beq t0,$0,_CPU_Context_1 /* set IEC level from restore context */
andi t0,(SR_INTERRUPT_ENABLE_BITS) /* we know 0 disabled */
beq t0,$0,_CPU_Context_1 /* set level from restore context */
mfc0 t0,C0_SR
nop
or t0,SR_IEC /* new_sr = sr | SR_IEC */
mtc0 t0,C0_SR /* set with enabled */
or t0,(SR_INTERRUPT_ENABLE_BITS) /* new_sr = old sr with enabled */
mtc0 t0,C0_SR /* set with enabled */
_CPU_Context_1:

2
cpukit/score/cpu/mips/rtems/score/cpu.h
View File

@@ -599,7 +599,7 @@ extern unsigned int mips_interrupt_number_of_vectors;
#define _CPU_ISR_Disable( _level ) \
do { \
mips_get_sr( _level ); \
mips_set_sr( (_level) & ~SR_IMASK ); \
mips_set_sr( (_level) & ~SR_INTERRUPT_ENABLE_BITS ); \
} while(0)
/*

16
cpukit/score/cpu/mips/rtems/score/mips.h
View File

@@ -22,6 +22,22 @@ extern "C" {
#include <idtcpu.h>
#endif
/*
* SR bits that enable/disable interrupts
*
* NOTE: XXX what about SR_ERL?
*/
#if __mips == 3
#ifdef ASM
#define SR_INTERRUPT_ENABLE_BITS 0x03
#else
#define SR_INTERRUPT_ENABLE_BITS SR_IE|SR_EXL
#endif
#else
#define SR_INTERRUPT_ENABLE_BITS SR_IEC
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the "no cpu"