In case the length of cwd path plus the userScriptName exceeds
PATH_MAX (255), the strncat calls will overflow scriptFile. Also
check for getcwd failure.
Use unsigned long instead of uint_fast32_t since C11 provides only a
ATOMIC_LONG_LOCK_FREE macro constant. This makes it also possible to
use properly typed integer literals like 123UL. It is now clear which
compatible type should be used for the atomic integer.
Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
Add ISR lock to chain control for proper SMP protection. Replace
rtems_chain_extract() with rtems_chain_explicit_extract() and
rtems_chain_insert() with rtems_chain_explicit_insert() on SMP
configurations. Use rtems_chain_explicit_extract() and
rtems_chain_explicit_insert() to provide SMP support.
Delete _Atomic_Init_flag(). Change ATOMIC_INITIALIZER_FLAG into a
constant. Rename _Atomic_Clear_flag() to _Atomic_Flag_clear(). Rename
_Atomic_Test_set_flag() to _Atomic_Flag_test_and_set(). This is now in
line with the C11 schema.
Add and use _POSIX_signals_Release(). The post-switch handler is not
protected by disabled thread dispatching. Use proper SMP lock for
signal management.
Add and use _ASR_Get_posted_signals(). The post-switch handler is not
protected by disabled thread dispatching. Use proper SMP lock for
signal management.
pc386 set CLOCK_DRIVER_ISRS_PER_TICK to a
string rather than a numeric value. Add
CLOCK_DRIVER_ISRS_PER_TICK_VALUE and
other clean up on the clock driver.
The _Thread_queue_Process_timeout() operation had several race
conditions in the event of nested interrupts. Protect the critical
sections via disabled interrupts.
