Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
PR 1743/cpu
* tm26/task1.c, tm27/task1.c: Add Simple Priority Scheduler as
complement to existing Deterministic Priority Scheduler. Modify these
tests to verify the scheduler they are designed to work with is the
default scheduler.
* tm01/task1.c, tm02/task1.c, tm03/task1.c, tm04/task1.c, tm05/task1.c,
tm06/task1.c, tm07/task1.c, tm08/task1.c, tm09/task1.c, tm10/task1.c,
tm11/task1.c, tm12/task1.c, tm13/task1.c, tm14/task1.c, tm16/task1.c,
tm17/task1.c, tm18/task1.c, tm19/task1.c, tm20/task1.c, tm21/task1.c,
tm23/task1.c, tm24/task1.c, tm25/task1.c, tm26/task1.c, tm27/task1.c,
tm28/task1.c, tm29/task1.c, tmoverhd/testtask.c: Run all tests
successfully with maxixum number of priorities as 16 instead of 256.
This was done by temporarily modifying the score priority.h maximum.
This allowed testing of all API code to ensure that it worked
properly with a reduced number of priorities. Most modifications were
to switch from hard-coded maximum to using the API provided methods
to determine maximum number of priority levels.
* Per PR47 add support for buffered test output. This involved
adding defines to redirect output to a buffer and dump it when
full, at "test pause", and at exit. To avoid problems when redefining
exit(), all tests were modified to call rtems_test_exit().
Some tests, notable psxtests, had to be modified to include
the standard test macro .h file (pmacros.h or tmacros.h) to
enable this support.
* include/timesys.h, tm01/task1.c, tm02/task1.c, tm03/task1.c,
tm04/task1.c, tm05/task1.c, tm06/task1.c, tm07/task1.c, tm08/task1.c,
tm09/task1.c, tm10/task1.c, tm11/task1.c, tm12/task1.c, tm13/task1.c,
tm14/task1.c, tm15/task1.c, tm16/task1.c, tm17/task1.c, tm18/task1.c,
tm19/task1.c, tm20/task1.c, tm21/task1.c, tm22/task1.c, tm23/task1.c,
tm24/task1.c, tm25/task1.c, tm26/task1.c, tm27/task1.c, tm28/task1.c,
tm29/task1.c, tmck/task1.c, tmoverhd/testtask.c: Modified.
a BSP (c4xsim) supporting the simulator included with gdb. This port
was done by Joel Sherrill and Jennifer Averett of OAR Corporation.
Also included with this port is a space/time optimization to eliminate
FP context switch management on CPUs without hardware or software FP.
An issue with this port was that sizeof(unsigned32) = sizeof(unsigned8)
on this CPU. This required addressing alignment checks and assumptions
as well as fixing code that assumed sizeof(unsigned32) == 4.
single biggest changes were the expansion of the workspace size
macro to include other types of objects and the increase in the
minimum stack size for most CPUs.
Configuration Table Template file added and all tests
modified to use this. All gvar.h and conftbl.h files
removed from test directories.
Configuration parameter maximum_devices added.
Core semaphore and mutex handlers added and RTEMS API Semaphore
Manager updated to reflect this.
Initialization sequence changed to invoke API specific initialization
routines. Initialization tasks table now owned by RTEMS Tasks Manager.
Added user extension for post-switch.
Utilized user extensions to implement API specific functionality
like signal dispatching.
Added extensions to the System Initialization Thread so that an
API can register a function to be invoked while the system
is being initialized. These are largely equivalent to the
pre-driver and post-driver hooks.
Added the Modules file oar-go32_p5, modified oar-go32, and modified
the file make/custom/go32.cfg to look at an environment varable which
determines what CPU model is being used.
All BSPs updated to reflect named devices and clock driver's IOCTL
used by the Shared Memory Driver. Also merged clock isr into
main file and removed ckisr.c where possible.
Updated spsize to reflect new and moved variables.
Makefiles for the executive source and include files updated to show
break down of files into Core, RTEMS API, and Neither.
Header and inline files installed into subdirectory based on whether
logically in the Core or a part of the RTEMS API.
Rearranged code to created thread handler routines to initialize,
start, restart, and "close/delete" a thread.
Made internal threads their own object class. This now uses the
thread support routines for starting and initializing a thread.
Insured deleted tasks are freed to the Inactive pool associated with the
correct Information block.
Added an RTEMS API specific data area to the thread control block.
Beginnings of removing the word "rtems" from the core.
