- Provide an option for a file system to support close wtih
references held. This can happen in more complex file systems
and file descriptor handling with more complete reference
handling implementations where an fd can hold other fds and
close can be call on any fd and succeed.
- Fix open IOP leaks in the error paths.
- Provide better definition of the IOP flags to help clarify
the code.
Fixes#5201Closes#5311
This adds support for the "vGetTLSAddr" GDB query which retrieves the
address of a TLS variable by offset from the beginning of the TLS memory
space for the given thread. This offset does not include the size of the
thread control block which is at the beginning of every TLS area as used
by RTEMS. Notably, the returned address is big-endian rather than the
little-endian typical with other responses.
This functionality does not include retrieval of addresses for TLS
variables hosted in loadable modules, only TLS variables in the host
binary.
Closes#5271
If the Double Trap Extension is implemented, the
MDT bit of the mstatus (or mstatush in RV32)
register will be set when a trap is to be taken.
The MIE (Machine Interrupt Enable) bit can only
be set to 1 if the MDT bit is zero.
Thus, we need to clear MDT first if we want to
enable interrupts when dispatching a thread.
MDT is also cleared in register a1 before
restoring the interrupt frame as writing 1 to MDT
will cause MIE to be set to 0. In RV64 this
happens regardless of the value written to MIE in
the same write.
In RV32, MDT is in the mstatush so we do not need
to clear during restore as this register is not
restored.
With this change all 60 SMP tests pass (compared
to 20/60 before the fix). The tests have been run
on hardware using two RV64 CPUs that implement
the double trap extension.
Close#5288
(cherry picked from commit 19f12d2dca)
Before, the console driver needed
`BSP_CONSOLE_USE_INTERRUPTS` to be defined or it
would not build. The intent was to use polled
mode if the macro was equal to zero.
This change makes it so interrupt mode is used if
the macro is defined and polled mode is used if
the macro is not defined.
(cherry picked from commit 5e0a68d3ab)
Close#5283
The old logic would lead to an error when
multiprocessing was enabled and
`LEON3_GPTIMER_BASE` was defined due to
`leon3_timer_core_index` being undefined.
The new logic fixes this and keeps the same
intent:
- If multiprocessing is not enabled, the timer
index is 0
- If multiprocessing is enabled and
`LEON3_GPTIMER_BASE` is defined, the timer
index is twice the CPU boot index
- If multiprocessing is enabled and
`LEON3_GPTIMER_BASE` is not defined, we
fallback to the old logic using the GPTIMER
core index.
Close#5281
When memory is accessed by the remote debugging client, the access is
sandboxed with setjmp/longjmp and appropriate exception handlers to
prevent the attempted access from causing a failure of the debugger or
otherwise altering execution. The existing implementation works as
expected when the context executing the memory access and the exception
context resulting from a failed access do not share a stack.
In the case of AArch64, a failed access when the debugger is already in
exception context causes a re-entry into exception context where the
machine state is pushed onto the same stack that was in use where the
exception occurred. When setjmp is called inside a stack frame and the
exception occurs outside that stack frame, the stack frame is unwound
before the exception occurs and the exception entry overwrites the area
previously occupied by the stack frame housing the setjmp and corrupting
the link register that is stored there. After restoration of state using
longjmp(), this corrupted link register information is loaded from the
stack frame and undesired behavior occurs.
In the instance of this bug that was encountered, the corrupted link
register contained an unaligned pointer which caused an unending cascade
of prefetch abort exceptions presenting as a hard hang.
Closes#5273
- Assume a relocation record with a symbol name with a length of
0 is resolved. ARM seems to create a symbol with no name for
R_ARM_V4BX relocation records.
- Move the addition of the rtems_rtl_base_sym_global_add symbol
to the global symbol table to the weak
rtems_rtl_base_global_syms_init call. If symbols are
embedded the support for runtime loading symbols is over
loaded. This change is required so the base object has a
valid global symbol table attached to track dependencies.
Fixes#5234
The following files will be installed during SPARC/GRLIB builds:
- bsps/include/grlib/apbuart-regs.h
- bsps/include/grlib/gptimer-regs.h
- bsps/include/grlib/irqamp-regs.h
- bsps/sparc/include/grlib/io.h
Closes issue #5232
For example, with edge triggered external interrupts we may see spurious
interrupts. Ignore them instead of issuing a fatal error.
Use eieio to synchronize access to the IACK and EOI registers.
Use a loop to immediately services the next pending interrupt without
having to go through the exception epiloge and prologue.
Close#5173.
Some pkg-config variants perform transformations on the --libs options.
This may lead to completely broken linker options. Provide the LDFLAGS
as a variable. Remove "Ldflags:" since this is an unsupported field.
Update #5165.
The RTEMS_CAPTURE_OVERFLOW is an overflow flag for each CPU, and its
value is the same as RTEMS_CAPTURE_INIT. Executing rtems_capture_flush
will set the RTEMS_CAPTURE_INIT flag to 0 in the global flags.
Fixes#5184.
This commit aligns trampolines for THUMB and ARM instructions
(CALL/JUMP24 and THM_JUMP24/THM_PC22).
According to the ARM technical reference in section "Register-relative
and PC-relative expressions":
In Thumb code:
- For B, BL, CBNZ, and CBZ instructions, the value of the PC is the
address of the current instruction plus 4 bytes.
- For all other instructions that use labels, the value of the PC is
the address of the current instruction plus 4 bytes, with bit[1]
of the result cleared to 0 to make it word-aligned.
Closes#5189
When compilation and linking are performed separately, some platforms
(i.e. RISC-V) may require that ABI flags are provided during the linking
step as well as the compilation step.
Closes#5183
The POSIX sporadic server may temporarily remove the real priority of a
thread. Check that the priority node is active before the change is
propagated.
Update #5164.
Previously the system event used by lio_listio was manually added to
event.h and not using rtems-central. This patch corrects that and renames
the event to make it clearer.
Some related dead code has also been removed.
(cherry picked from commit cabc8c3a78)
Co-authored-by: alessandronardin <ale.daluch@gmail.com>
This moves the management console implementation into its own file so
that BSPs which do not need it do not carry the code around with them.
Closes#5120
This adds generic JFFS2 interworking code that allows JFFS2 to be used
on top of any flashdev backend. It currently only supports NOR flashdev
backends.
Commit 3d782180ea changed the reported Git
hash to short. Change this back to the normal Git hash. Existing
support code may rely on this. The short hash is generated based on the
current repository state. The reported hash should be useful also for
future states of the repository. If Git changes the hash algorithm in
the future, then the hash length may be used as an indicator for the
hash algorithm. With a variable hash length this is more difficult.
Simplify expression.
Update #5037.
Accesses to the L2C registers performed by the L2C driver are now
serialized with spin locks. This avoids concurrent access to the L2C
registers by multiple processors. Proposed by GRLIB-TN-0021.
Update #4925.
