1. read_mii() now returns 0xffff on failure. It is more robust when it
comes to reading the reset bit in the control register, that is the
first access.
2. write_mii() now has error printout like read_mii().
3. Additional (optional) PHY access debugging is now available by
enabling GRETH_DEBUG_MII. Even successful accesses are printed.
4. Let PHY do power-down (not only reset) to get in a good state,
this is just in case the PHY input pin settings are sampled only
on PHY power-up on some PHYs.
5. PHY GBit advertisement is disabled if Gbit is not supported by MAC.
Or forced if supported.
6. Auto-nego is started if supported by PHY, before it was started only
if default set by PHY.
7. Reset Sequence updated:
* one must wait until reset bit is self-cleared.
* the DD (Disable Duplex Detection) bit is set, only affects
EDCL capable devices. This lets RTEMS handle PHY initialization
Looking at PHY Ctrl register without reseting it will give back
old register content, that is not stable. Instead the PHY is
reset and the autonogotiation capability is read out and
started if present.
In some GRPCI cores not setting the cache line size could result
in long prefetches on the AMBA bus which would lead to bad
performance when doing PCI reads to GRPCI target interface (DMA).
This patch adds a new driver for the GRSPW SpaceWire AMBA
interface family. The new driver does not implement a standard
RTEMS driver, instead it provides only a library interface to
the GRSPW devices. This driver can be used to implement a
RTEMS I/O driver or used directly.
New features compared with old GRSPW driver:
* zero-copy packet interface
* possibility to send/receive mulitple packets per call
* optional interrupt awaken work-task to process TX/RX queues
* DMA channels support. Before only first DMA channel supported
* Separate DMA and link control
* Packet based error flags
The _Watchdog_Nanoseconds_since_tick_handler() function caller does
not take into account that the timer counter may wrap, underflow or
overflow. Instead, the driver must take that into account. This
GPTIMER DrvMgr driver patch makes use of the IRQ-Pending bit to
determine if a underflow has happened. In that case a greater time
than one tick is returned (even considering the function name..).
The TLIB clock layer must also ACK the interrupt pending bit,
otherwise we couldn't determine whether an IRQ is pending or if
belongs to un old already handled tick IRQ.
Note that this patch only fixes the DrvMgr GPTIMER driver and TLIB,
the standard LEON3 GPTIMER driver still needs a fix.
Some bugfixes at the same time. After this patch the drivers
may be used on RASTA systems having a big-endian PCI layout.
Removed not up to date changelogs, rely on git log instead.
The CCHIP driver is replaced with the GR_701 driver. The
RASTA driver is replaced by the GR-RASTA-IO driver.
All drivers are now compatible with both LEON2 and LEON3,
drivers were initialized directly by the PCI-board drivers
are now initialized by the driver manager and therefore
does not require the double code created by including for
example grcan.c into grcan_rasta.c. The other drivers needs
to be updated to the driver manager framework however.
Added support for:
* GR-701 (only LEON2 before)
* GR-RASTA-IO (only LEON2 before)
* GR-RASTA-ADCDAC
* GR-RASTA-TMTC
* GR-RASTA-SPW-ROUTER
* GR-TMTC-1553
In some non-standard designs GRLIB peripherals are used together
LEON2. This patch adds a GRLIB amba Plug&Play driver so that AMBA
devices can be found from Plug&Play the same way as with the LEON3
BSP.
The user is required to add an AMBA-PnP device entry into the LEON2
bus configuration, so that the driver manager unite this driver
with the "fake" device and start scanning after AMBA PnP devices.
The old code used a limited PCI configuration library, which was
duplicated into LEON2 and LEON3 BSP pci.c together with respective
Host controller PCI interface.
The LEON2 BSP had support for AT697 PCI, and LEON3 for GRPCI PCI
Host controller. With this update new PCI Host drivers are added,
and all support the new generic PCI Library:
* AT697 PCI (LEON2 only)
* GRPCI (LEON2-GRLIB and LEON3)
* GRPCI2 (LEON2-GRLIB and LEON3)
* Actel PCIF GRLIB Wrapper (LEON3 only)
The LEON2 BSP is defined as big-endian PCI in bsp.h, since the
AT697 supports only big-endian PCI.
This patch reimplements the console driver of the LEON3 BSP, it
has split up the console driver in two parts: Console driver and
UART driver. Before the only UART supported was APBUART and only
on-chip APBUARTs found during startup. However splitting the
driver in two allows any UART interface to reuse the termios
attach code of the console driver, pratically this has always
been a problem when discovering APBUARTs after startup for
example the PCI board GR-RASTA-IO has APBUARTs and must wait
until after PCI has been setup.
Since the only current driver that supports the new console
driver uses the Driver Manager, the new console driver is
only enabled when Driver Manager is initialized during startup.
The new APBUART driver supports:
* polling mode
* interrupt mode
* task-driven mode
* set UART attributes
* read UART attributes (system console inherit settings from
boot loader)
* Driver manager for finding/initialization of the hardware
With this patch the LEON family can access the GRLIB GPTIMER using
the Timer library (TLIB).
A System Clock driver instead of BSP/clock/ck_init.c is provided
using the TLIB. The classic clock driver is split in two parts,
clock driver and timer driver. The BSPs need only to fullfill the
timer interface instead of the clock interface. Currently only
LEON3 uses it. The LEON2 Timer is not ported to TLIB.
The GPTIMER driver is implemented using the Driver Manager, so the
System Clock Driver is at this point only suitable for LEON3 when
the driver manager is initialized during BSP startup. When the DrvMgr
is not initialized during startup the standard BSP/clock dirver is
used.
LEON2 sometimes also needs to access GPTIMER when a off-chip GRLIB AMBA
systems is connected, for example AMBA-over-PCI.
Remove support for using the second timer for time stamping.
Instead the user can configure the system clock timer to a higher
base clock frequency (lower the prescaler). This change does not
affect the GR712RC or LEON4-N2X. The GR712RC does not have two
GPTIMERs and the N2X uses the Interrupt Controller for time
stamping.
Bow that the AMBA initialization code exports the AMBA device,
the frequency can be obtained without an additional AMBA PnP
scanning.
Its now possible to select which timer core will be used for
system clock timer and to control the timer prescaler that
affects all timer instances on that timer core.
The timer and interrupt controller AMBA devices are exported
to make it possible for other code to get detailed information.
For example the frequency of the timer and interrupt controller
is required by the cpucounter support.
Fix some UART register addresses and implementation bugs that
were causing malfunction of console driver on real hardware.
hello and ticker samples are tested and working fine now on mor1kx
based SoC on Atlys FPGA board.
BSP_OR1K_OR1KSIM_PERIPHCLK has been changed to 50MHz as with mor1kx/atlys
SoC; this change has no effect on the current simulators that RTEMS run
on.
