The original ARM architecture wide cache_.h is changed to dummy version
for targets not implementing/enablig cache at all.
The ARM targets equipped by cache should include
appropriate implementation.
Next options are available for now
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
basic ARM cache integrated on the CPU core directly
which requires only CP15 oparations
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
support for case where ARM L2C-310 cache controller
is used. It is accessible as mmaped peripheral.
c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
Cortex-M specific cache support
Updates #2782
Updates #2783
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used for data and or code and ensures that
there are no partial cache lines overlaps on start and
end of allocated region.
Updates #2782
Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.
Updates #2782
Updates #2783
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
Updates #2783
The current versions of U-boot start kernel/RTEMS application image
with instruction and data caches enabled and it sets exception
base register to new address after its self-relocation.
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
Included changes in bsp_start_hook_0 restore default state to
allow RTEMS image to run after startup from newer U-boot version
on Raspberry Pi.
Clear interrupt enable registers in interrupt controller
to ensure that RTEMS starts from well defined state.
Updates #2783
Only use CPU_Per_CPU_control if it contains at least one filed. In GNU
C empty structures have a size of zero. In C++ structures have a
non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero,
then this structure is not used anymore.
Close#2789.
This patch fixes a number of bugs in the cache when requests are
made to read close to the end of the file and the data is copied
from the top of the cache buffer to the bottom of the buffer. This
was compounded by attempting to read past the end of the file.
Closes#2754.
The window underflow trap handler used %i5 which destroyed the %o5 of
the calling context. Bug introduced by
0d3b5d4742.
Go back to the pre 0d3b5d4742 behaviour
and use the two unused instructions in the trap vector to optimize a
bit.
Close#2651.
Add path length parameter to
rtems_filesystem_eval_path_start_with_root_and_current() so that users
may pass paths without a '\0' termination.
Update #2558.
Under certain conditions a new watchdog was inserted with a wrong
and very large delta interval due to a wrong iterator update.
Bug was introduced by 1ccbd05291.
Close#2507.
Under certain conditions a new watchdog was inserted with a wrong and
very large delta interval due to an incomplete iterator update.
Bug was introduced by 1ccbd05291.
Close#2501.
The problem exists for both RTEMS untar implementations and their
variants: Untar_FromMemory(), Untar_FromFile() and rtems_tarfs_load().
If filesystem object already exists at extracted directory path
then if it is directory, creation is ignored. Attempt
to delete/unlink object and make directory is tried for other cases.
This simple approach problem reported in ticket fixes#2413.
Behavior follows GNU tar and BSD tar practice for directories
but much more work is required to achieve full semantics
of the full featured tar implementation still.
The default tms570ls3137_hdk variant is for building RTEMS
application image starting directly from start of Flash.
Variant tms570ls3137_hdk_with_loader skips 256kB at start
of Flash to allow use with application loader.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Parameters overlay module is initialized and cleared first.
It is used later to replace exception target vectors
only if that is required.
The application loader code with CPU and SDRAM setup
code has to provide well defined pattern of instructions
at addresses 0x00000000 and 0x0000001f, because only data
read accesses can be processed reliably by POM. The expected
instruction pattern can be seen in the next example
https://github.com/hornmich/tms570ls3137-hdk-sdram/blob/master/SDRAM_SCI_configuration/source/sys_intvecs.asm
Comments with detailed description of code, background
and reasons for selected approach have been included
in TMS570 bsp startup code.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Premysl Houdek <kom541000@gmail.com>
We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.
In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.
Close#2472.
We must ensure that the Thread_Control::Wait information update is
visible to the target thread before we update its wait flags, otherwise
we may return out of date events or a wrong status.
Close#2471.
