Commit Graph

21 Commits

Author SHA1 Message Date
Kinsey Moore
698227e6ea bsps/aarch64: Ensure FPU trap state is consistent
RTEMS may be booted from a dirty environment. Ensure that FPU trap
settings are consistent.
2022-11-09 08:14:11 -06:00
Sebastian Huber
21a36ed19b bsps: Fix .data.rel.ro placement
The .data.rel.ro* linker input section pattern accidentally matches with
writeable data those symbol name starts with "ro".

Close #4701.
2022-08-12 10:10:17 +02:00
Chris Johns
b868d0a722 basp/aarch64: Make the unexpected sections origin address 64bit
Update #4684
2022-07-28 09:04:46 +10:00
Sebastian Huber
5ed0035377 bsps: Sort .noinit* sections
Sort the .noinit* input sections by name first, then by alignment if two
sections have the same name.  This allows the placement of begin/end symbols to
initialize some areas with a special value.

Update #4678.
2022-07-15 10:46:02 +02:00
Gedare Bloom
6c36cb7a48 aarch64: always boot into EL1NS
Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.

Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
2022-01-12 09:00:19 -07:00
Gedare Bloom
ea7b1b79f8 bsps/aarch64: refactor register init and hooks 2022-01-12 09:00:19 -07:00
Sebastian Huber
96221e40dd bsps/aarch64: Support .noinit linker section 2021-12-13 07:32:58 +01:00
Kinsey Moore
750bde8c78 bsps/aarch64: Mask debug events from startup
Debug events should be masked at least until after the first context
switch and should usually be masked until a debugger is attached for
application debugging.
2021-11-01 08:39:00 -05:00
Kinsey Moore
5f652cb27e cpukit: Add AArch64 SMP Support
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
2021-09-21 08:58:32 -05:00
Gedare Bloom
17a9103c53 aarch64: whitespace fixes in start.S 2021-06-24 12:55:29 -06:00
Gedare Bloom
93088fb835 bsps/aarch64: replace boot options with asm switch code 2021-06-24 12:55:23 -06:00
Gedare Bloom
76c6caad52 bsps/aarch64: add non-secure mode and versal support 2021-06-24 09:37:31 -06:00
Kinsey Moore
e613068ee6 aarch64: add support to drop EL3 to EL2 2021-06-24 09:37:31 -06:00
Kinsey Moore
a27ba3f20f bsps/aarch64: Add support for EL2 start
Add the stub necessary to boot on AArch64 under EL2 and drop to EL1 for
normal operation.
2021-03-05 08:43:15 -06:00
Kinsey Moore
9951cee08f bsps/aarch64: RTEMS_DEBUG stack alignment faults
Run with stack alignment faults enabled under RTEMS_DEBUG to catch any
stack misalignments early. This makes it easier to track them down
should they ever occur.
2021-03-05 08:43:15 -06:00
Kinsey Moore
6bfbfb5a3d bsps/aarch64: Resolve usage of SUBALIGN()
Remove usage of SUBALIGN() in aarch64 linkcmds which works around a
difference in behavior on AArch64 platforms. This is no longer necessary
since alignment is now enforced explicitly.

Closes #4178.
2021-03-05 08:43:15 -06:00
Sebastian Huber
9eb9813dc1 bsps: Add missing DWARF 5 sections
Sort alphabetically.
2021-01-26 15:29:36 +01:00
Sebastian Huber
33c12d5f92 bsps: Support DWARF 5 sections
GCC 11 uses DWARF 5 by default.
2021-01-25 12:56:00 +01:00
Kinsey Moore
1cbe5773ab spec/aarch64: Only apply SUBALIGN(4) to ILP32
The SUBALIGN(4) required on rtemsroset and rtemsrwset for ILP32 builds
was previously present on LP64 builds and causes no issues within RTEMS,
but causes relocation/alignment issues when building libbsd. This
restricts those alignment changes to ILP32 builds.
2020-11-23 09:57:45 -06:00
Kinsey Moore
ed9c88cea8 bsps: Add Cortex-A53 ILP32 BSP variant
This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.
2020-10-05 16:11:40 -05:00
Kinsey Moore
db68ea1b9b bsps: Add Cortex-A53 LP64 basic BSP
This adds an AArch64 basic BSP based on Qemu's Cortex-A53 emulation with
interrupt support using GICv3 and clock support using the ARM GPT.
2020-10-05 16:11:40 -05:00