bsps: Add Cortex-A53 ILP32 BSP variant

This adds an AArch64 ILP32 BSP variant based on Qemu's Cortex-A53
emulation with interrupt support using GICv3 and clock support using
the ARM GPT.

bsps/aarch64/shared/start/start.S

@@ -101,19 +101,31 @@ _start:
          * Get current per-CPU control and store it in PL1 only Thread ID
          * Register (TPIDRPRW).
          */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+	ldr	w1, =_Per_CPU_Information
+#else
 	ldr	x1, =_Per_CPU_Information
+#endif
 	add	x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2
 	mcr	p15, 0, x1, c13, c0, 4
 
 #endif
 
 	/* Calculate interrupt stack area end for current processor */
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+	ldr	w1, =_ISR_Stack_size
+#else
 	ldr	x1, =_ISR_Stack_size
+#endif
 #ifdef RTEMS_SMP
 	add	x3, x7, #1
 	mul	x1, x1, x3
 #endif
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+	ldr	w2, =_ISR_Stack_area_begin
+#else
 	ldr	x2, =_ISR_Stack_area_begin
+#endif
 	add	x3, x1, x2
 
 	/* Save original DAIF value */
@@ -135,7 +147,11 @@ _start:
 	 * Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
 	 * Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0
 	*/
+#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
+	ldr	w1, =bsp_stack_exception_size
+#else
 	ldr	x1, =bsp_stack_exception_size
+#endif
 	/* Switch to SP0 and set exception stack */
 	msr	spsel, #0
 	mov	sp, x3

spec/build/bsps/aarch64/a53/abi.yml

@@ -8,7 +8,12 @@ copyrights:
 - Copyright (C) 2020 On-Line Applications Research (OAR)
 default:
 - -mcpu=cortex-a53
-default-by-variant: []
+default-by-variant:
+- value:
+  - -mcpu=cortex-a53
+  - -mabi=ilp32
+  variants:
+  - aarch64/a53_ilp32_qemu
 enabled-by: true
 links: []
 name: ABI_FLAGS

spec/build/bsps/aarch64/a53/bspa53ilp32qemu.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+arch: aarch64
+bsp: a53_ilp32_qemu
+build-type: bsp
+cflags: []
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+cppflags: []
+enabled-by: true
+family: a53
+includes: []
+install: []
+links:
+- role: build-dependency
+  uid: grp
+- role: build-dependency
+  uid: linkcmds_ilp32
+source: []
+type: build

spec/build/bsps/aarch64/a53/linkcmds_ilp32.yml

@@ -0,0 +1,71 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+build-type: config-file
+content: |
+  /*
+   * SPDX-License-Identifier: BSD-2-Clause
+   *
+   * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+   * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
+   *
+   * Redistribution and use in source and binary forms, with or without
+   * modification, are permitted provided that the following conditions
+   * are met:
+   * 1. Redistributions of source code must retain the above copyright
+   *    notice, this list of conditions and the following disclaimer.
+   * 2. Redistributions in binary form must reproduce the above copyright
+   *    notice, this list of conditions and the following disclaimer in the
+   *    documentation and/or other materials provided with the distribution.
+   *
+   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   * POSSIBILITY OF SUCH DAMAGE.
+   */
+
+  MEMORY {
+    RAM       : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_LOAD_OFFSET}, LENGTH = ${BSP_A53_RAM_LENGTH} - ${BSP_A53_LOAD_OFFSET} - ${BSP_A53_NOCACHE_LENGTH}
+    NOCACHE   : ORIGIN = ${BSP_A53_RAM_BASE} + ${BSP_A53_RAM_LENGTH} - ${BSP_A53_NOCACHE_LENGTH}, LENGTH = ${BSP_A53_NOCACHE_LENGTH}
+  }
+
+  REGION_ALIAS ("REGION_START",          RAM);
+  REGION_ALIAS ("REGION_VECTOR",         RAM);
+  REGION_ALIAS ("REGION_TEXT",           RAM);
+  REGION_ALIAS ("REGION_TEXT_LOAD",      RAM);
+  REGION_ALIAS ("REGION_RODATA",         RAM);
+  REGION_ALIAS ("REGION_RODATA_LOAD",    RAM);
+  REGION_ALIAS ("REGION_DATA",           RAM);
+  REGION_ALIAS ("REGION_DATA_LOAD",      RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT",      RAM);
+  REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
+  REGION_ALIAS ("REGION_FAST_DATA",      RAM);
+  REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
+  REGION_ALIAS ("REGION_BSS",            RAM);
+  REGION_ALIAS ("REGION_WORK",           RAM);
+  REGION_ALIAS ("REGION_STACK",          RAM);
+  REGION_ALIAS ("REGION_NOCACHE",        NOCACHE);
+  REGION_ALIAS ("REGION_NOCACHE_LOAD",   NOCACHE);
+
+  bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1024;
+
+  bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
+
+  bsp_vector_table_in_start_section = 1;
+
+  OUTPUT_FORMAT ("elf32-littleaarch64")
+  OUTPUT_ARCH (aarch64:ilp32)
+
+  INCLUDE linkcmds.base
+copyrights:
+- Copyright (C) 2020 On-Line Applications Research (OAR)
+enabled-by: true
+install-path: ${BSP_LIBDIR}
+links: []
+target: linkcmds
+type: build