This cleans up outputUsesInterrupts usage with rtems_termios_device_mode
enum values. The outputUsesInterrupts member was typed as an int, named
as if it were a boolean value, and used as if it were a
rtems_termios_device_mode enum. In this patch, values assigned to
outputUsesInterrupts have been converted to the corresponding
rtems_termios_device_mode enum value, conversions from
deviceOutputUsesInterrupts have been made explicit, and uses of
rtems_termios_device_mode enum values with deviceOutputUsesInterrupts
have been converted to booleans.
When the CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS definition was added
to AArch64 cache management, it obsoleted the *_1_data/instruction_line
functions. These have been removed since they are no longer referenced.
The AArch64_instruction_cache_inner_shareable_invalidate_all function is
only used when RTEMS_SMP is defined, so only define it in that
circumstance.
Expose functions to directly manipulate the bad block table (BBT). These
functions are necessary to correct possible BBT corruption caused by
bugs in the BBT management layer.
The XNandPsu_EraseBlock function takes a target device and a block
offset for erasure. Ensure the block offset is within the size of the
target device.
When marking the trailing blocks on a device as reserved for Bad Block
Table usage, ensure that the correct blocks are marked. This resolves an
off-by-one error that was marking one block too low and leaving the last
block in the device unmarked.
The Bad Block Table is a per-device catalog of the dispositions of each
block in the device. Only read enough data to determine the dispositions
of blocks for the device being read.
The xnandpsu driver includes functionality to map back and forth between
the flash-based BBT and the memory-based BBT with the values in each
being a bitwise inversion of each other. This resolves several bugs in
this process and simplifies the inversion from operating on the block
representation to operating on the entire BBT entry (4 blocks, 2 bits
per block, one byte total).
Bugs resolved in XNandPsu_ConvertBbt():
* The calculation of memory BBT entry offset was off by a factor of 4
* The entry offset into the flash BBT has been removed since each flash
BBT directly describes the flash space it is contained within and has
no reference to other devices in the chip
Bugs resolved in XNandPsu_WriteBbt():
* The BBT length calculated was reduced to NumTargetBlocks from
NumBlocks since only the relevant portion of the in-memory BBT should
be written to the flash-based BBT space
* An offset was applied to values retrieved from the in-memory BBT so
that only the relevant portion was converted and written to the
flash-based BBT
The XNandPsu_IsBlockBad() function is insufficient for JFFS2 to
determine whether a block is usable since the function does not report
reserved blocks. JFFS2 is also unable to use the last 4 blocks of each
target attached to the NAND controller since they are reserved for the
Bad Block Table (BBT), but not necessarily marked as such.
Hi all, this is my first email patch submission and my first contribution to RTEMS, so please give any
feedback you have!
This patch enables interrupt driven data reception on USART ports on
STM32F4 series chips. This feature is gated behind the config flag
BSP_CONSOLE_USE_INTERRUPTS. If this flag is not set to True, the older
polling implementation will be used. I tested this feature on STM32F401CE
(blackpill) and STM32 Nucleo F411RE boards, with both capable of keeping
up with a 115200 baud continous data stream. With the older polling
implementation, both would drop bytes at 9600 baud. In addition, I
updated the implementation of usart_set_attributes to support changing
the baud rate of the USART port based on the input speed.
Place the vector table in the start section so that the overlay can be
avoided if we execute from internal flash. The problem is that when the
POM is enabled, the ECC cannot be enabled for the internal flash.
With this, it is possible to use GPIOs as CS pins in the LPSPI. To avoid
additional complexity, the GPIOs will have the same limitations as the
native (hardware) CS pins.
The GPIO CS feature adds a number of extra code when starting SPI
transfers on this controller. Therefore it is possible to disable the
additional code by just setting the IMXRT_LPSPI_MAX_CS option to 0. In
that case only native CS pins are supported.
At the moment, this feature is only enabled on i.MXRT1166 by default
because it is not tested on i.MXRT1050. But it should work there too.
Device trees allow mixing different kinds of GPIOs in one property. For
that it is usefull to only provide a pointer to an arbitrary location in
the property and initialize a GPIO from that.
This imports the TTC hardware definitions for the triple timer counters
on various Xilinx platforms. This was imported as specified in the
VERSION file in this commit.
The xnandpsu driver conditionally tries to wrap page index to NAND chip
size causing an off-by-one error where the first page of the second chip
is not wrapped correctly. This removes the conditional so that page
index is always wrapped.
On configurations where multiple NAND chips are in use, the erasure
loop in XNandPsu_Erase() can reset the loop counter variable once it
gets to blocks in the second chip causing an infinite loop overwriting
parts of the first chip. This change ensures that the loop counter is
not accidentally reset.
Prefer use of XNandPsu_Erase instead of XNandPsu_EraseBlock since the
XNandPsu driver does not expose the primitives necessary to ensure
device readiness after the operation is complete.
This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
Merge the timecounter and CPU counter support for the leon3 BSP family.
Remove now unused functions from the CPU counter support of the erc32
and leon3 BSPs.
Update #4954.
Share the timecounter instance between the clock and the CPU counter.
This greatly simplifies the clock driver since we have to do the device
selection only in one place, the CPU counter support.
Update #4954.
Using the auto reload counter which generates the clock ticks for the
timecounter or CPU counter is quite difficult and only works in
uniprocessor configurations.
Update #4954.
Force use of addresses that would be translated by TTBR1 to cause a
translation fault. RTEMS on AArch64 does not use TTBR1 and so attempted
translation of that address range could cause unexpected behavior in the
form of other exception types since TTBR1 is never set.
Ensure that a single locking session is carried over OOB writes
including the OOB read that is sometimes required. This removes the
possibility of another write occurring between the read and write that
would make the write incorrect.
