* shared/include/cpuIdent.c, shared/include/cpuIdent.h: Added support
for e500v2. Removed IVPR/IVOR/HWIVOR features since they are included
in Book E.
* new-exceptions/bspsupport/vectors.h,
new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/ppc_exc_address.c,
new-exceptions/bspsupport/ppc_exc_categories.c,
new-exceptions/bspsupport/ppc_exc_initialize.c,
new-exceptions/bspsupport/ppc_exc_prologue.c: Added support for
e500v2. Added exception vector defines for Book E types. Removed
e200 exception vector defines. Added e500 exception vector defines.
Unified IVOR calculation for e200 and e500 (e200z1 has hard wired
IVOR values).
* new-exceptions/e500_raw_exc_init.c, new-exceptions/raw_exception.c,
shared/include/cpuIdent.c, shared/include/cpuIdent.h:
Added different kinds of 'bookE' to the ppc_cpu_is_bookE feature
check; unfortunately...
* shared/include/cpuIdent.h, shared/include/cpuIdent.c:
Added a simple 'feature check' facility. Code should
not check for a particular CPU type if possible but
check the respective feature bit (e.g., 'has_altivec').
This makes it much less cumbersome to add more CPU
types in the future.
PR 581/bsps
* mpc6xx/exceptions/raw_exception.c, shared/include/cpuIdent.h:
Converting PSIM to new exception model required adding PSIM as
PowerPC CPU model.
* powerpc/shared/include/cpuIdent.c,
powerpc/shared/include/cpuIdent.h: Add 603le.
(Submitted by Thomas.Doerfler <Thomas.Doerfler@imd-systems.de>
as part of the patch attached to PR 703).
* configure.ac, mpc6xx/exceptions/raw_exception.c,
mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c,
mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, shared/include/cpuIdent.c,
shared/include/cpuIdent.h: Add MPC8240 and MPC8245 support. There was
also a significant amount of spelling and whitespace cleanup.
* README, configure.ac, mpc5xx/Makefile.am,
mpc5xx/exceptions/raw_exception.c, mpc5xx/exceptions/raw_exception.h,
mpc5xx/timer/timer.c, shared/include/cpuIdent.h: addition of a
significant amount of MPC5xx support as part of the addition of the
SS555 BSP.
* mpc5xx/README, mpc5xx/clock/clock.c,
mpc5xx/console-generic/console-generic.c, mpc5xx/include/console.h,
mpc5xx/include/mpc5xx.h, mpc5xx/irq/irq.c, mpc5xx/irq/irq.h,
mpc5xx/irq/irq_asm.S, mpc5xx/irq/irq_init.c,
mpc5xx/vectors/vectors.S, mpc5xx/vectors/vectors.h,
mpc5xx/vectors/vectors_init.c: New files.
* mpc5xx/exceptions/asm_utils.S: Removed.
PR 349/bsps
* mpc6xx/exceptions/raw_exception.c, mpc6xx/mmu/bat.c,
mpc6xx/mmu/pte121.c, shared/include/cpuIdent.c,
shared/include/cpuIdent.h, shared/src/Makefile.am, shared/src/stack.c,
shared/src/stackTrace.h, powerpc/registers.h:
- undo improper 'fix' who broke mpc604r identification
- fix: 7400 identification PVR value was wrong
- enhance 'setdbat()' to switch OFF a given BAT if called with 0 size
- fix: page table support bugfix
- enhancement: provide routines to take and print stack trace
snapshots
- add definitions for HID1 and DABR SPRs
* rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add
the following:
- support for the MPC74000 (AKA G4); there is no
AltiVec support yet, however.
- the cache flushing assembly code uses hardware-flush on the G4.
Also, a couple of hardcoded numerical values were replaced
by more readable symbolic constants.
- extended interrupt-disabled code section so enclose the entire
cache flush/invalidate procedure (as recommended by the book).
This is not (latency) critical as it is only used by
init code but prevents possible corruption.
- Trivial page table support as been added.
(1:1 effective-virtual-physical address mapping which is only
useful only on CPUs which feature hardware TLB replacement,
e.g. >604. This allows for write-protecting memory regions,
e.g. text/ro-data which makes catching corruptors a lot easier.
It also frees one DBAT/IBAT and gives more flexibility
for setting up address maps :-)
- setdbat() allows changing BAT0 also (since the BSP may use
a page table, BAT0 could be available...).
- asm_setdbatX() violated the SVR ABI by using
r20 as a scratch register; changed for r0
- according to the book, a context synchronizing instruction is
necessary prior to and after changing a DBAT -> isync added
