When committed, the MicroBlaze RAM size was hard-coded to 16MB. This
changes the default to 256MB and sets the KCU105 BSPs to 2GB since that
is what the board has on it.
Add MicroBlaze support for libdebugger. This uses only software break
type instructions to provide self-hosted GDB debugging support for
applications since internal control of debug hardware is not possible.
Also of note, this implementation for MicroBlaze would typically use the
brki instruction for software break, but instead uses an illegal opcode
to manage software breaks as exceptions. This is due to poor interaction
with the debug hardware where the debug hardware will intercept software
breaks instead of allowing the software break vector to execute.
This patch adds a vector for debug events along with a hook similar to
the exception framework. The debug vector generates an exception frame
for use by libdebugger.
This patch updates the CPU_Exception_frame to include all necessary
registers, combines hardware snd software exception handlers into a
shared vector, provides an architecture-specific hook for taking
control of exception handling, and moves exception handling over to
actually using the CPU_Exception_frame instead of a minimal interrupt
stack frame. As the significant contents of _exception_handler.S have
been entirely rewritten, the copyright information on this file has been
updated to reflect that.
When the stack checker is not enabled, the stack checker reporting
function can still be called. This prevents that call from performing a
null memory access in trying to find the high water mark if the stack
checker was never initialized.
This also introduces a test to ensure this call does not cause a crash.
Closes#4588
GCC versions prior to 6.1 used a RTEMS thread model based on
rtems_gxx_*() functions. GCC version 6.1 or later uses the
self-contained synchronization objects of Newlib <sys/lock.h> for the
RTEMS thread model.
Remove the obsolete implementation.
Close#3143.
Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
When the cadence I2C code was moved to a shared directory, the
references were updated but the install locations weren't. This updates
the install locations to match what out-of-tree applications expect.
The BSPs provide memory for the separate C Program Heap initialization
via _Memory_Get(). Most BSPs provide exactly one memory area. Only two
BSPs provide more than one memory area (arm/altera-cyclone-v and
bsps/powerpc/mpc55xxevb). Only if more than one memory area is
provided, there is a need to use _Heap_Extend(). Provide two
implementations to initialize the separate C Program Heap and let the
BSP select one of the implementations based on the number of provided
memory areas. This gets rid of a dependency on _Heap_Extend(). It
also avoids dead code sections for most BSPs.
Change licence to BSD-2-Clause according to file history.
Update #3053.
The BSPs provide memory for the workspace initialization via
_Memory_Get(). Most BSPs provide exactly one memory area. Only two
BSPs provide more than one memory area (arm/altera-cyclone-v and
bsps/powerpc/mpc55xxevb). Only if more than one memory area is
provided, there is a need to use _Heap_Extend(). Provide two
implementations to initialize the workspace handler and let the BSP
select one of the implementations based on the number of provided memory
areas. This gets rid of a dependency on _Heap_Extend(). It also avoids
dead code sections for most BSPs.
Remove _Thread_queue_Extract_with_proxy() and move the proxy extraction
to _Thread_MP_Extract_proxy(). Move similar code blocks of the previous
caller of _Thread_queue_Extract_with_proxy() to helper functions.
Update #4546.
This patch fixes the following broken behaviour:
While a thread is scheduled on a helping scheduler, while it does not
own a MrsP semaphore, if it obtains a MrsP semaphore, then no
scheduler node using an idle thread and the ceiling priority of the
semaphore is unblocked for the home scheduler.
This could lead to priority inversion issues and is not in line
with the MrsP protocol.
Introduce two new scheduler operations which are only enabled if
RTEMS_SMP is defined. The operations are used to make the scheduler
node of the home scheduler sticky and to clean the sticky property.
This helps to keep the sticky handing out of the frequently used
priority update operation.
Close#4532.
These external functions rtems_scheduler_get_processor() and
rtems_scheduler_get_processor_maximum() which may be used by bindings
for languages other than C/C++.
This patch set replaces the CPU budget algorithm enumeration with a set of CPU
budget operations which implement a particular CPU budget algorithm. This
helps to hide the CPU budget algorithm implementation details from the general
thread handling. The CPU budget callouts are turned into CPU budget
operations. This slightly reduces the size of the thread control block.
All schedulers used the default scheduler tick implementation. The tick
scheduler operation is removed and the CPU budget operations are directly used
in _Watchdog_Tick() if the executing thread uses a CPU budget algorithm. This
is performance improvement for all threads which do not use a CPU budget
algorithm (default behaviour).
This moves the AArch64 MMU memory type definitions into cpukit for use
by libdebugger since remapping of memory is required to insert software
breakpoints.
This adds a confdef option allowing an application to request mapping
machine exceptions to POSIX signals. This is required for some languages
such as Ada.
This adds the set of functions necessary to allow more generic handling
of machine exceptions. This initial patch offers the ability to
manipulate a CPU_Exception_frame and resume execution using that
exception information with or without thread dispatch. These functions
are gated behind the RTEMS_EXCEPTION_EXTENSIONS configuration option.
The rate monotonic period statistics were affected by
rtems_cpu_usage_reset(). The logic to detect and work around a CPU
usage reset was broken.
The Thread_Contol::cpu_time_used is changed to contain the processor
time used throughout the entire lifetime of the thread. The new member
Thread_Contol::cpu_time_used_at_last_reset is added to contain the
processor time used at the time of the last reset through
rtems_cpu_usage_reset(). This decouples the resets of the CPU usage and
the rate monotonic period statistics.
Update #4528.
The spconfig01 and spmisc01 tests were disabled for all AArch64 BSPs due
to a toolchain issue preventing them from compiling correctly. The
binutils version that contains the fix has been released and integrated
into RSB such that these two tests now build and operate correctly.
Add a stack allocator hook specifically for allocation of IDLE thread stacks.
This allows the user to decide if IDLE thread stacks are statically allocated
or handled by the same custom allocator mechanism as other thread stacks.
Closes#4524.
