Changes include reverting back to setting all page-table section entries
as invalid and modify mm_config_table to apply the correct memory attributes
for raspbberypi memory sections at startup. The newly added entry at mm_config_table
maps raspberrypi GPIO and other registers found at raspberrypi.h
The function
arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache() must
only set the MMU and cache enable flags. Configuration flags must be
set elsewhere.
STOP_TRANSMISSION command is used to finish READ_MULTIPLE_BLOCK
command and its format is regular command format.
It requires valid CRC-7 to have effect at least on
same cards types else it is ignored and attempt
to issue next READ or WRITE commands results in
illegal command condition (0x04) preceded by strange
(0x3f) for tested card.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Add support for MMU initialization for RaspberryPi. Introduce new shared
MMU configuration table that can be used by other BSPs that call the
arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache function.
Demonstrate the use of the generic table with RaspberryPi.
The new ARM_CP15_CTRL_XP is necessary to share ARMv6 and ARMv7
page-table formats and definitions.
It enables the extended page tables (introduced in ARMv6)
to be configured for the hardware page translation mechanism. This way
we can share ARMv6 and ARMv7 page tables entry formats.
Other Fault Status Register Definitions can be useful for debugging or
excpetion handlers.
Add ISR lock to chain control for proper SMP protection. Replace
rtems_chain_extract() with rtems_chain_explicit_extract() and
rtems_chain_insert() with rtems_chain_explicit_insert() on SMP
configurations. Use rtems_chain_explicit_extract() and
rtems_chain_explicit_insert() to provide SMP support.
pc386 set CLOCK_DRIVER_ISRS_PER_TICK to a
string rather than a numeric value. Add
CLOCK_DRIVER_ISRS_PER_TICK_VALUE and
other clean up on the clock driver.
CSB336 i.MX1/i.MXS memory map organization
- SDRAM starts at address 0x08000000 but 2 MB are reserved
for boot-block/loader (or other use) before RTEMS image
origin/load address (that is kept from previous setup)
- Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000)
is changed to writeback mode which provides higher throughput.
- The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0
to provide area for ARM CPU exceptions table.
- Internal registers and rest of the Flash (above 1 MB) are mapped
one to one. Registers region is extended to 2 MB to cover
eSRAM found on i.MX1 chip variant.
- The first two megabytes of SDRAM unused by RTEMS are mapped
with attributes to allow specific purposes.
- the first MB (at address 0x08000000) is nocached to allow
directly set some values read by booot-block after warm reset
- the second MB (at address 0x08100000) is set for write-through
caching. That allows to use memory for LCD frame-buffer without
need to flush cache after each redraw.
Jump to start provided at address 0x08200000 allows
to load application image even as plain binary file
and start it by jump to image start address.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
