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bsp/csb336: Memory map update and jump to start at image start provided.

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CSB336 i.MX1/i.MXS memory map organization

 - SDRAM starts at address 0x08000000 but 2 MB are reserved
   for boot-block/loader (or other use) before RTEMS image
   origin/load address (that is kept from previous setup)

 - Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000)
   is changed to writeback mode which provides higher throughput.

 - The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0
   to provide area for ARM CPU exceptions table.

 - Internal registers and rest of the Flash (above 1 MB) are mapped
   one to one. Registers region is extended to 2 MB to cover
   eSRAM found on i.MX1 chip variant.

 - The first two megabytes of SDRAM unused by RTEMS are mapped
   with attributes to allow specific purposes.

   - the first MB (at address 0x08000000) is nocached to allow
     directly set some values read by booot-block after warm reset

   - the second MB (at address 0x08100000) is set for write-through
     caching.  That allows to use memory for LCD frame-buffer without
     need to flush cache after each redraw.

Jump to start provided at address 0x08200000 allows
to load application image even as plain binary file
and start it by jump to image start address.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
This commit is contained in:
Pavel Pisa
2013-08-09 01:22:06 +02:00
committed by Sebastian Huber
parent 526f895efe
commit 2a2f559957
2 changed files with 14 additions and 3 deletions
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7
c/src/lib/libbsp/arm/csb336/start/start.S
View File

@@ -23,6 +23,13 @@
.equ PSR_F, 0x40
.equ PSR_T, 0x20
.section .bsp_start_text,"ax"
.code 32
_start_jump_at_origin:
ldr pc, _start_address
_start_address:
.word _start
.text
.globl _start
_start:

10
c/src/lib/libbsp/arm/csb336/startup/memmap.c
View File

@@ -16,10 +16,14 @@
*/
mmu_sect_map_t mem_map[] = {
/* <phys addr> <virt addr> <size> <flags> */
{0x08200000, 0x00000000, 1, MMU_CACHE_NONE}, /* Mirror of SDRAM */
{0x08200000, 0x00000000, 1, MMU_CACHE_WBACK}, /* Mirror of SDRAM */
{0x00100000, 0x00100000, 1, MMU_CACHE_NONE}, /* Bootstrap ROM */
{0x00200000, 0x00200000, 1, MMU_CACHE_NONE}, /* Internal Regs */
{0x08000000, 0x08000000, 32, MMU_CACHE_WTHROUGH}, /* SDRAM */
{0x00200000, 0x00200000, 2, MMU_CACHE_NONE}, /* Internal Regs + eSRAM */
{0x08000000, 0x08000000, 1, MMU_CACHE_NONE}, /* SDRAM */
{0x08100000, 0x08100000, 1, MMU_CACHE_WTHROUGH}, /* SDRAM */
{0x08200000, 0x08200000, 30, MMU_CACHE_WBACK}, /* SDRAM */
{0x10000000, 0x10000000, 8, MMU_CACHE_NONE}, /* CS0 - Flash */
{0x12000000, 0x12000000, 1, MMU_CACHE_NONE}, /* CS1 - enet */
{0x13000000, 0x13000000, 1, MMU_CACHE_NONE}, /* CS2 - */